A Single-Stage Bridgeless Power-Factor-Correction Rectifier Based ...

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Rectifier Based on Flyback Topology. K. T. Mok*, Y. M. Lait. Department of Electronic and Information Engineering. The Hong Kong Polytechnic University.
A Single-Stage Bridgeless Power-Factor-Correction Rectifier Based on Flyback Topology K. T. Mok*, Y. M. Lait Department of Electronic and Information Engineering The Hong Kong Polytechnic University Hung Hom, Hong Kong, China *Email: [email protected] tEmail: [email protected]

Abstract-A single-stage bridgeless power-factor-correction (PFC) rectifier based on Ryback topology is presented in this paper. The proposed rectifier substantially improves efficiency and power factor without the use of additional isolation stage. The o peration and performance of the proposed circuit was verified with a 48-V I-A prototype. The experimental results

90 % and power for input range from 110-V to 230-V. The proposed design is suitable for wide-range input low-power off­ line applications. show that the circuit can attain efficiencies over factors over

0.92

Index Terms-Bridgeless, rectification, power factor correction

I.

INTRODUCTION

The traditional AC/DC power converter such as boost and flyback power converters use bridge rectifiers and bulk capaci­ tors to convert the low-frequency AC voltage into a DC, which is used by the subsequent high frequency switching circuits. The existence of the bridge rectifiers in these converters, however, usually leads to the problems of conduction power loss, unwanted current harmonics and input current cusp distortion [ 1]. To alleviate these problems, different rectifier­ less (bridgeless) power converter topologies were proposed by researchers to eliminate the use of the bridge rectifiers at the AC input [2] - [9]. The first bridgeless boost converter was proposed in 1983 by Mitchell [2], where the objective was to improve the power factor by overcoming the cusp distortion problem in the zero voltage crossing region of the AC input voltage. Since then, different versions of bridgeless boost converters had been proposed to enhance system performances such as better magnetic utilization [3], higher power efficiency [4], better EMI noise suppression [5] and improved flexibility in feedback control [6]. A bridgeless buck PFC rectifier [7] and bridgeless buck-boost converter [8] were also proposed to reduce the conduction losses that were caused by the bridge rectifiers. In addition, the bridgeless converters based on fourth-order topologies such as Cuk and SEPIC were studied and analyzed in [9]. All these bridgeless converters show that they are capable to achieve higher efficiency and improved PF. However, they require a post-regulator to provide isolation in

978-1-4577-1250-0/11/$26.00 ©2011 IEEE

K. H. Loo Faculty of Engineering The Hong Kong Polytechnic University Hung Hom, Hong Kong, China Email: [email protected]

order to meet the safety standards of commercial applications. The addition of a post-regulator unavoidably leads to the decline of overall power efficiency in these applications. In this paper, we propose a single-stage bridgeless PFC fly­ back converter that can attain high efficiency and good power factor without using an additional isolation stage. Moreover, the proposed converter offers several advantages over its exist­ ing single-stage counterparts: ( 1) It has a transformer isolation for meeting the international safety standards; (2) A more flexible voltage conversion ratio is achievable by choosing suitable primary and secondary transformer turn ratio; and (3) A zero voltage transition detector, used to determine the line period polarity, is not required in the proposed bridgeless topology so that the control complexity is greatly simplified. To verify the operation and performance of the proposed bridgeless flyback converter, a 48-V I-A output universal­ line experimental prototype was built. The measured efficien­ cies are more than 90 % and the power factors greater than 0.92 over the input voltage range from 100-V to 230-V. II. BRIDGELESS PFC FLYBACK CONVERTER The simplified schematic of the proposed AC/DC bridgeless PFC flyback converter is shown in Fig. 1. The proposed converter consists of two primary windings and two high frequency MOSFETs to control the power flowing to the secondary. The operation of the circuit can be divided into four modes as shown in Fig l(a)-(d) and is briefly described as follows. Mode 1: During the positive half line period, the switch 81 is turned on. Vin is across the primary winding L1 of the transformer. This results a linearly increasing magnetizing current in L1. In this positive half line period, there is no current flowing through winding L2. The voltage Vs across the secondary side winding L3 is negative, and thus the output rectifier Do is in off state. The output capacitor Co is discharging to provide energy for the output. Mode 2: When the switch 81 is turned off, the magnetic energy stored in the transformer in Mode 1 releases in the form of a flyback current flowing through the secondary winding L3 such that the output rectifier Do is turned on and Vs is equal to the output voltage (neglecting diode drop of Do).

D2

C

(a) Mode I

+

through L3, the secondary voltage Vs is now positive and the rectifier diode Do is turned on. The power MOSFETs 81 and 82 switch on and off to provide switching operation during positive and negative line period respectively. During positive line period, the on/off state of 82 will not affect the normal operation of the power converter because the diode D2 preventing current flowing through the primary winding L2. Similarly, the on/off state of power MOSFET 81 is trivial during negative line period. Hence, one pulse-width modulation (PWM) controller is suf­ ficient to control both 81 and 82. This circuit arrangement simplifies the control circuitry as no zero-voltage detection circuit is necessary to detect the polarity of line voltage. III. DESIGN CONSIDERATIONS

(b) Mode 2

The design considerations of the proposed converter are discussed in this section. The detailed circuit schematic of the proposed design is shown in Fig. 2. In order to meet the PFC requirement of ICE6 1000-2-3 standard [ 10], the proposed converter is designed to operate in boundary control mode (BCM) using a Fairchild FAN7530 BCM PFC controller. The circuit equations and transformer construction of the proposed design are discussed as follows. A.

Circuit Equations

The electrical parameters such as the maximum inductor peak currents and minimum primary inductance are required to obtain in order to further analyze the proposed design. The inductor peak currents i L1_pk and i L2_pk flowing through the primary windings L1 and L2 during Mode 1 and Mode 3 operations respectively under BCM can be expressed as: (c) Mode 3

S] 'I"\...J

D] L
---I

Fig. 2.

-....

I

/

/

/

-1

I I

PWM

BY26VC

13'

15 kQ

r

7

ZC

II kQ

RL

N,=36T



110 - 220 V"

48 V

STTH802

FAN7530 Controller

3

0 '"

:0

tv

ZC

4N26

I I

----

;:;

0

5



Isolation

I

8

I

5.1 kQ 47 nF

2.4 kQ

IV

6

1:: "T'I -

Full schematic diagram of the proposed converter.

'-

(5)

The on-time can be found by the inductor charging equation:

(6)

Fig. 3.

Current waveforms of primary and secondary windings.

Combining (4), (5) and (6), the time equation for averaged input current can be written as: indicated in the figure represent the instantaneous primary and secondary current respectively. The top and middle dotted line show the peak current envelopes while the bottom dotted line shows the averaged switching primary current. According to the inductor volt-second balance principle of transformer and negating leakage inductances, the relationship of primary inductor peak current (ip_pk), secondary inductor peak current (is_pk), power MOSFETs on-time (ton), power MOSFETs off-time (toff), the primary to secondary windings turn ratio (Np/Ns), the input voltage Vin(t) and the output voltage Vo can be related by:

Vin(t) ton Vo toff

is_pk ip_pk

Np Ns

(4)

The averaged primary inductor current within one switching period can be found by:

iin(t)

=


sw (t)

=

(J2 2(1+

1 (t) N � -'..!. Np . ip_pk >

Value

0.69 A 4.11 A

30 kHz 596 J.LH

IV. EXPERIMENT RESULTS

v'2Vinsinwt Ns Jin Lp = 2(1+ ) Np Vin

No 2p_pk . (t) Lp+ Lp N Vo p

( 10)

Equation ( 10) can be used to find the critical value of primary inductance given a minimum switching frequency. B.

max

AWG number 26 wire is used and it placed at the outer most of the bobbin. However, the coupling coefficient between primary and secondary windings affects significantly to the power efficiency of the power system. In order to minimize the leakage inductance on those windings, those two primary windings are split into two parts and placed at the bottom and on the top of the secondary winding respectively. In addition, those two primary windings require the same inductance value in the proposed design, two windings should wound in parallel among the bobbin so as to enhance the symmetry of two windings and reduce the inductance variations.

Pin 4

Fig. 4.

Symbol

Min. required primary inductance

Pin 16 Pin

Circuit parameters Max. primary averaged current

Transformer Construction

The transformer of the proposed power converter was built with the standard ETD-39 bobbin and Magnetics R­ type ferrite. The physical construction of the transformer is illustrated in Fig. 4. The transformer consists of two primary windings (red and blue), a secondary winding (green) and an auxiliary winding (yellow). Since the role of auxiliary winding is detecting the zero level of magnetizing current of the trans­ former and providing power for the controller. The auxiliary winding is not required to handle large energy transfer hence

A 48-V I-A output prototype circuit is built to validate the proposed bridgeless /lyback converter. The specifications of the prototype are as follows: 1) Input voltage: wide range voltage ( 1 10-V to 220-V) 2) Output voltage: 48-V The power devices and components of the prototype are listed as follows: 1) Power MOSFET switches: IRF840 2) Primary diodes: BYV26C 3) Output diode: STTH802 4) Transformer: ETD-34, Magnetics R-type ferrite 5) Input filter inductor: BOURNS - 2 100LL, 330 p,H 6) Input filter capacitor: EPCOS - B32652A, 0.47 p,F 7) Input common mode choke: EPCOS - B82732R, 3.3 mH 8) Output filter capacitor: Panasonic CE FC, 680 p,F, 63 V

The electrical parameters are calculated based on Eqs. ( 1) to ( 10) and the results are listed in TABLE I. Fig. 5 and Fig. 6 plot the power efficiency and power factor for the input voltages for the range of 100-V to 230-V under the 48-V 1-A nominal output current condition. The waveforms of in­ put voltage and current are shown in Fig. 7. The measurement results show that the proposed converter can maintain power efficiencies at 90 % while the power factor measured with EMI filter is greater than 0.92 for the entire input voltage. This safely meets the requirement of ICE6 1000-2-3 standard. As mentioned in SECTION II, the proposed design simpli­ fies the the control complexity as only one PWM signal is required to control two MOSFETs. Figure 8 and 9 captured two sets of waveforms during positive and negative line cycles respectively. The voltage reference points A, Band C are indicated in Fig. l(a). During positive line cycle and on-time

120

140

160

180

Line Voltage (Vrms)

200

220 Fig. 7.

Fig. 5.

Experiment waveforms: Top: Input voltage Bottom: Input current.

Measured results of power efficiency. 10.OVI

200V1

1.1 r---��---'----�---r�

120

Fig. 6.

140

160

180

Line Voltage (Vrms)

200

220



200V1

0.0.

1.00011

Stop

f



·200V

Fig. 8. Experiment waveforms captured at positive line cycle: Top: VBA Middle: VCA Bottom: PWM control signal.

Measured results of power factor. 10.OVI

200VI

200VI

0.0.

1.00011

Stop

f



100V

period, VBA is zero and current flows through L1 while the potential at point A is higher than that at point C such that D2 is turned off and no current flows through L2 even S2 is turned on by the PWM control signal. Similar argument can be observed in Fig. 9 during negative line cycle. The waveforms show the viability of the proposed control methodology.

V.

CONCLUSION

A 48-V i-A output prototype was built to validate the proposed design. The measurement results also show that the power efficiency is at around 90 %. This is considerably higher than the traditional two-stage isolated PFC rectifiers of which the overall power efficiency is usually around 70 % to 80 % under low power applications. It is shown that the proposed single-stage bridgeless PFC flyback converter can

Fig. 9. Experiment waveforms captured at negative line cycle: Top: VBA Middle: VCA Bottom: PWM control signal.

provide an effective low-cost solution based on a single-stage

isolated PFC rectifier for an application under 100 W. The proposed design is suitable for wide-range input low-power off-line applications. REFERENCES [1] C. K. T se and M. H. L. Chow, "New single-stage P FC regulator using the Sheppard-Taylor topology," IEEE Trans. Power Electron., vol. 13, no. 5, pp. 842 -851, Sep. 1998. [2] D. M. Mitchell, AC-DC converter having an improved power factor. u.s. Patent, Oct. 1983, no. 4-412-277. [3] Y. lang and M. lovanovic, "A bridgeless P FC boost rectifier with optimized magnetic utilization," IEEE Trans. Power Electron., vol. 24, no. 1, pp. 85 -93, lan. 2009. [4] w.-Y. Choi, l.-M. Kwon, and B.-H. Kwon, "An improved bridgeless P FC boost-doubler rectifier with high-efficiency," in Proc. IEEE 39th PESC Conj., 2008, pp. 1309 -1313. [5] P. Kong, S. Wang, and F. Lee, "Common mode EMI noise suppression for bridgeless P FC converters," IEEE Trans. Power Electron., vol. 23, no. 1, pp. 291 -297, lan. 2008. [6] B. Lu, R. Brown, and M. Soldano, "Bridgeless P FC implementation using one cycle control technique," in Proc. 20th Annu. IEEE APEC, vol. 2, 2005, pp. 812 -817 Vol. 2. [7] Y. lang and M. lovanovic and, "Bridgeless high-power-factor buck converter," IEEE Trans. Power Electron., vol. 26, no. 2, pp. 602 -611, Feb. 2011. [8] W. Wei, L. Hongpeng, 1. Shigong, and X. Dianguo, "A novel bridgeless buck-boost P FC converter," in Proc. IEEE 39th PESC Conj., 2008, pp. 1304 -1308. [9] A. Sabzali, E. Ismail, M. Al-Saffar, and A. Fardoun, "New bridgeless DCM SEPIC and C uk P FC rectifiers with low conduction and switching losses," IEEE Trans. Ind. Appl., vol. 47, no. 2, pp. 873 -881, 2011. [10] IEC 61000-3-2, Electromagnetic Compatibility (EMC) - Part 3-2: Limits for Harmonic Current Emissions (Equipment Input Current . 16A per phase), Edition 2.1.

International Electrotechnical Commission, 2010.