A Single-Stage High-Power-Factor Electronic Ballast ... - IEEE Xplore

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IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 55, NO. 3, MARCH 2008

A Single-Stage High-Power-Factor Electronic Ballast Based on Integrated Buck Flyback Converter to Supply Metal Halide Lamps Marco A. Dalla Costa, Student Member, IEEE, J. Marcos Alonso, Senior Member, IEEE, Jesús Cardesín Miranda, Member, IEEE, Jorge García, Member, IEEE, and Diego G. Lamar, Student Member, IEEE

Abstract—In this paper, a novel single-stage electronic ballast with a high power factor is presented. The ballast circuit is based on the integration of a buck converter to provide the power factor correction, and a flyback converter to control the lamp power and to supply the lamp with a low-frequency square-waveform current. Both converters work in discontinuous conduction mode, which simplifies the control. In spite of being an integrated topology, the circuit does not present additional stress of voltage or current in the main switch, which handles only the flyback or buck current, depending on the operation mode. To supply the lamp with a low-frequency square-wave current to avoid acoustic resonances, the flyback has two secondary windings that operate complementarily at a low frequency. The design procedure of the converters is also detailed. Experimental results from a 35-W metal halide lamp are presented, where the proposed ballast reached a power factor of 0.95, a total harmonic distortion of 30% (complying with IEC 61000-3-2), and an efficiency of 90%. Index Terms—Acoustic resonance (AR), electronic ballast, high power factor (HPF), integrated buck flyback converter, metal halide lamp (MHL), single stage (SS).

I. I NTRODUCTION

M

ETAL HALIDE lamps (MHLs) are widely used because of their merits of high efficacy, compact size, color properties, and compact volume [1]. To achieve good efficiency, have no light flicker and audible noise, and be compact in size, these lamps must be supplied by electronic ballasts. However, this kind of lamp cannot be supplied by a high-frequency voltage plus a resonant filter like fluorescent lamps because of acoustic resonance (AR) [2]–[4]. Many alternatives are being studied to avoid the AR, such as the following: avoiding the frequencies where the AR appears with low-frequency square-waveform (LFSW) ballasts [5] or extra-high-frequency ballasts [6]; lamp operation in a free-resonance window [7]; high-frequency square-waveform supply [8]; lamp operation with suitable frequency modulated waves, where the threshold value to excite the AR is not achieved [9]; and lamp operation with sinusoidal waveform superposed with the third harmonic [10]. Manuscript received May 10, 2005; revised September 19, 2007. This work was supported by the Spanish Education and Science Office, under Research Grant DPI-2003-00308. The authors are with the Department of Electrical Engineering, University of Oviedo, 33204 Gijón, Spain (e-mail: [email protected]). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TIE.2007.909729

In practice, the LFSW ballast is the most effective solution to eliminate AR. The main problem with this circuit is its complexity because conventionally, a three-stage ballast is necessary, which includes the following: 1) power-factorcorrection (PFC) stage, 2) lamp power control (LPC) stage, and 3) inverter stage. This results in an expensive ballast. Therefore, many efforts are being made to integrate the three stages [11]–[21]. However, the integration of the stages results in voltage or current stress in the shared switch. In [22], a single-stage (SS) high-power-factor (HPF) electronic ballast dedicated to supply fluorescent lamps was presented, which was based on the integration of a buck dc–dc converter and a half-bridge resonant inverter. This topology could not be used to supply MHLs because of the problem of AR at high frequencies. Therefore, in this paper, the basic idea of integrating a dc–dc buck converter is used with the flyback topology to obtain an SS HPF LFSW MHL ballast. In this paper, an SS electronic ballast is presented, which is achieved by integrating a buck converter to provide the PFC and a flyback converter to control the lamp power, without overvoltage or current in the main switch. The flyback inductor includes two secondary windings that work complementarily at a low frequency to supply the lamp with an LFSW current.

II. P ROPOSED B ALLAST Fig. 1 illustrates the proposed ballast. The circuit consists of a three-stage ballast, where a preregulator buck dc–dc converter provides the PFC (PFC stage), a flyback converter controls the LPC stage, and a full-bridge inverter supplies the lamp with an LFSW current (inverter stage). Both converters (buck and flyback) operate in discontinuous conduction mode (DCM). The lamp power is regulated by the duty cycle of switch Sfly . Besides, the LFSW current through the lamp is obtained by the low-frequency commutation of the switches SLF1 , SLF2 , SLF3 , and SLF4 . To decrease EMI, the command signals of these switches are synchronized with Sfly . The circuit presented above is a three-stage electronic ballast, which is a complex and expensive solution. On the other hand, it can be understood that switches Sbuck and Sfly can be replaced by a shared switch (SSH , DSH1 , and DSH2 ), as shown in Fig. 2. Besides, if one extra secondary winding is added to the flyback inductor, only two switches could be used to supply

0278-0046/$25.00 © 2008 IEEE

DALLA COSTA et al.: SINGLE-STAGE HPF ELECTRONIC BALLAST BASED ON INTEGRATED BUCK FLYBACK CONVERTER

Fig. 1.

HPF electronic ballast.

Fig. 2.

Integrated buck flyback topology.

the lamp with an LFSW current, which was recently presented in [23] and [24]. Comparing both topologies, the integrated circuit shown in Fig. 2 presents only three controlled switches and two extra diodes. The rest of the components are the same in both topologies. There exists a clear reduction in cost, not only from avoiding the use of three additional controlled switches, but also because the use of the buck converter without integration requires an isolated driver for the power switch. Buck and flyback converters are studied in Sections V and VI, separately. III. B ALLAST O PERATION M ODES In this section, the possible operating modes of the proposed circuit are analyzed to define the conditions for the complete ballast design and to demonstrate why the circuit does not show overvoltage or current in the main switch. Furthermore, to analyze the integrated topology, the two secondary windings (LS1 and LS2 ), which commutate complementarily by the switches SLF1 and SLF2 , can be represented by only one winding (LS ) without commutation. Also, the MHL can be represented by an equivalent resistance (RL ). Fig. 3 shows all possible equivalent circuits that can appear according to the operation modes shown in Table I, which are described below. Time instants t1 and t2 represent the instants when the inductor buck and flyback currents reach zero, respectively. The initial condition for the buck capacitor (CB ) voltage value is V0 . The instantaneous line voltage is represented by vg (t). 1) Mode A: vg (t) ≤ V0 ; Interval Sequence—I–II–III: This is the only operation mode for vg (t) ≤ V0 . The operation starts

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when SSH is turned on, and the bus voltage charges the flyback primary winding (Interval I). In this interval, only the switch and diode DSH2 are conducting. When SSH turns off, the energy stored in the flyback core is discharged by the secondary winding (LS ). In this interval (II), only diode Dfly is conducting, and it ends when the current in LS reaches zero (instant t2 ). Then, Interval III starts and the energy stored in the capacitor Cf supplies the lamp, until SSH turns on again. Therefore, if vg (t) ≤ V0 , Mode A starts again; however, if vg (t) > V0 , Mode B, C, D, or E would take place. 2) Mode B: vg (t) > V0 and V0 /LP > (vg (t) − V0 )/Lbuck and t1 > t2 ; Interval Sequence—IV–VI–VII–III: This operation mode occurs when vg (t) > V0 , and the flyback current is higher than the buck current (V0 /LP > (vg (t) − V0 )/Lbuck ), and the flyback inductor discharges before the buck inductor (t1 > t2 ). It starts by the Interval IV, where SSH and DSH2 are conducting. The flyback current (ifly ) is higher than the buck current (iL ), so the bus capacitor supplies the extra current to the flyback inductor. In this interval, the switch SSH handles only the flyback current. After SSH turns off (Interval VI) the buck current circulates through diode DB , charging the bus capacitor, and the energy stored in the flyback core discharges through the secondary winding (LS ). Therefore, if the LS current reaches zero before iL , the energy stored in the capacitor Cf supplies the lamp and iL keeps decreasing (Interval VII). When the buck current reaches zero, Interval III occurs again, until SSH turns on. 3) Mode C: vg (t) > V0 and V0 /LP > (vg (t) − V0 )/Lbuck and t1 < t2 ; Interval Sequence—IV–VI–II–III: This operation mode occurs when vg (t) > V0 , and the flyback current is higher than the buck current (V0 /LP > (vg (t) − V0 )/Lbuck ), and the

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Fig. 3. Operating intervals of the proposed ballast. (a) Interval I. (b) Interval II. (c) Interval III. (d) Interval IV. (e) Interval V. (f) Interval VI. (g) Interval VII.

flyback inductor discharges after the buck inductor (t1 < t2 ). The main difference, compared to Mode B, is that after Interval VI, Interval II starts. In other words, the current in the buck inductor reaches zero before the current in the secondary flyback inductor. 4) Mode D: vg (t) > V0 and V0 /LP < (vg (t) − V0 )/Lbuck and t1 > t2 ; Interval Sequence—V–VI–VII–III: The main difference of this mode compared to Mode B is that the buck current is higher than the flyback current. Therefore, it starts by Interval V, where the difference between iL and ifly flows through CB and DSH1 . In this case, switch SSH handles only the buck current. After SSH turns off, the circuit operation is similar to Mode B. 5) Mode E: vg (t) > V0 and V0 /LP < (vg (t) − V0 )/Lbuck and t1 < t2 ; Interval Sequence—V–VI–II–III: The main difference, compared to Mode D, is that after Interval VI, Interval II

starts. In other words, the current in the buck inductor reaches zero before the current in the secondary flyback inductor. Another operation mode could appear if t1 = t2 . However, it is not a common situation, so it will not be analyzed here. Table I presents the operation modes, with respective conditions, intervals, and currents handled by switch SSH (ISSH ). In summary, during Modes A, B, and C, the switch SSH handles only the flyback current (ifly ), whereas during Modes D and E, it only carries the buck current (iL ). IV. B ALLAST O PERATION M ODES To clarify the different operation modes previously explained, a simulation example is presented in this section. The simulation has been performed based on the prototype that will be introduced in Section VII.


TABLE I BALLAST OPERATION MODES RESUME

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When SSH is off, the energy stored in inductor Lbuck flows through capacitor CB , according to the following expression: iL (t) = iL (dTS ) −

V0 (t − dTS ), Lbuck

dTS < t < t1 (2)

where t1 is the instant when the current iL (t) reaches zero. The filtered envelopment at line frequency of the input current is shown in Fig. 6(b). The buck input current is equal to the inductor current during the interval [0, dTS ]. Then, the mean input current (ig_mean ) can be calculated as follows: ig_mean =

d2 2Lbuck f

(vg − V0 )

(3)

f being the switching frequency. Equation (3) can also be expressed as follows: Fig. 4 shows the simulation results of switch SSH voltage and current, together with buck and flyback currents, iLbuck and iLP , respectively. In this case, for one line period, the ballast operation modes where A, C, and D, for vg = 50, 150, and 300 V, respectively (V0 = 100 V). As can be seen in Fig. 4(b), for vg = 50 V, the buck current is equal to zero because the line input voltage is lower than the buck output voltage. Therefore, the main switch SSH handles only the flyback current. For vg = 150 V [Fig. 4(c)], the buck current has started to flow, but it is still lower than the flyback current. Thus, the main switch SSH again handles only the flyback current. Finally, for vg = 300 V [Fig. 4(d)], the buck current has overcome the flyback current, therefore the main switch SSH handles only the buck current. These results prove that the switch SSH handles the flyback current in Modes A and C, and the buck current in Mode D. Regarding the switching conditions, since both buck and flyback operate in DCM in all operating modes, the current through the main switch is a triangular waveform starting from zero, and therefore there are no switching losses during the turn-on process. The losses in the turn-off process are minimized by the intrinsic capacitor of the MOSFET used as the main switch. V. B UCK A NALYSIS Fig. 5 shows the buck equivalent circuits for vg (t) > V0 . As can be seen, the flyback converter operating in DCM is represented by an equivalent resistance in steady-state (Rfly ). Therefore, the PFC characteristic of the buck converter can be studied as in [22]. Fig. 6(a) represents the theoretical waveforms at highfrequency for the aforementioned stages. When SSH is on, the current in the inductor buck [iL (t)] increases linearly according to following expression: iL (t) =

vg (t) − V0 Lbuck

t,

0 < t < dTS

where TS is the switching period and d is the duty cycle.

(1)

ig_mean =

vg − V 0 . RS

(4)

Therefore, the buck converter working in DCM behaves like a resistance when the instantaneous line voltage [vg (t)] is higher than the buck output voltage (V0 ). Also, the value of this resistance (RS ) is: RS =

2Lbuck f . d2

(5)

As can be seen, the input current is proportional to the input voltage, but only within the time the rectified line voltage is higher than V0 . The conduction time interval can be measured by means of the conduction angle θ. The higher the conduction angle, the closest the input current to a perfect sine waveform, and the lower the harmonic content. The complete study of the harmonic content of this waveform was already performed in [25]; therefore, only the resulting characteristics are presented in this paper. Fig. 7 shows the power factor (PF) and total harmonic distortion (THD) for an input current waveform as that shown in Fig. 6(b). To satisfy the IEC-61000-3-2 class C requirements, a minimum conduction angle of 130◦ is necessary. At this operation point, a PF of 0.96 and THD of 29% are obtained. According to [22], the following expression must be solved to define the buck equivalent resistance (RS ) for a given output voltage (V0 ): Vg2 2RS V0

V0 2 1 − sin−1 π Vg

−

V0 1 2 Vg − V02 − =0 πRS Rfly (6)

where Vg is the peak line voltage. VI. F LYBACK A NALYSIS Using the same principle, the flyback converter can now be analyzed and designed considering the buck stage as a dc voltage source (V0 ). The flyback works as a current source, and a single half-bridge inverter is responsible for swapping, at low frequency (250 Hz), the secondary windings of the converter. A

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Fig. 4. Simulation results (V0 = 100 V): (a) buck current at low frequency; SSH voltage and current, buck and flyback currents for (b) vg = 50 V (Mode A); (c) vg = 150 V (Mode C); and (d) vg = 300 V (Mode D).

1) Mode 1—SSH On: When SSH is on, the current flowing through the inductance LP (iP ) is defined in (7), its peak value is calculated in (8), and its mean value during one complete period (TS ) is shown in (9) iP (t) =

V0 t LP

(7)

iP_p =

V0 dTS LP

(8)

iP_m =

V 0 d2 T S . 2LP

(9)

Fig. 5. Buck equivalent circuits for vg (t) > V0 . (a) SSH (on). (b) SSH (on).

small capacitor is used to filter the current ripple that is imposed by the DCM operation of the flyback converter. Therefore, this circuit can be analyzed as a conventional flyback converter. A design example of this circuit can be seen in [26], which has been continued in this paper. Fig. 8 shows the two equivalent circuits of the ballast: (a) when SSH is on (Mode 1), and (b) when SSH is off (Mode 2). Fig. 8(c) presents the theoretical waveforms of the flyback winding currents. For the analysis, some parameters have to be defined, such as: switching frequency (f ), commutation period (TS = 1/f ), primary winding inductance (LP ), secondary winding inductance (LS ), turns ratio (n2 = LS /LP ), duty cycle (d), buck output voltage (V0 ), and lamp nominal voltage (VL ).

Assuming constant duty cycle and switching frequency, the input current is proportional to the source voltage. Thus, at low frequency, the converter behaves as a resistive load for the source, and its value (Rfly ) is the ratio between the input voltage and mean current Rfly =

V0 iP_m

=

2LP . d2 T S

(10)

2) Mode 2—SSH Off: In this operation mode, the energy stored in the flyback inductance is released by the secondary winding inductance (LS ). The secondary peak current (iS_p ), which is the initial condition for this stage, depends on the


Fig. 6.

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Proposed ballast input waveforms. (a) High-frequency. (b) Filtered low-frequency.

Fig. 7. PF and THD characteristics of the proposed ballast. (a) PF versus conduction angle. (b) THD versus conduction angle.

turn ratio (n) and is defined in (11). When the switch is off, all energy stored in the core has to be transferred to the load (t2 interval). Assuming a constant lamp voltage, time t2 can be calculated in (12) iP_p iS_p = n LS iS_p ndTS V0 t2 = = . VL VL

(11) (12)

Fig. 8. Flyback operation modes: equivalent circuits and theoretical waveforms. (a) SSH (on)—Mode 1. (b) SSH (off)—Mode 2. (c) Theoretical waveforms.

Secondary mean current, which is the lamp current, is calculated in iS_m =

t2 1 V 2 d2 T S iS_p = 0 . 2 TS 2VL LP

(13)

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Fig. 9. Proposed ballast complete circuit.

VII. B ALLAST C OMPLETE D ESIGN A design example is presented to clarify the ballast analysis. The complete circuit is shown in Fig. 9. To define the component values, some parameters have to be defined: 1) Lamp: Osram HCI-T 35W/WDL, which has VL = 80 V, irms = iS_m = 0.44 A, and RL = 180 Ω. 2) Line supply: 220 Vrms ± 20%/50 Hz. 3) Commutation frequencies: high = 50 kHz, and low = 250 Hz. At first, buck output voltage (V0 ) must be defined to provide a line current waveform that meets IEC61000-3-2 class C requirements. In [22], it was verified that for V0 = 137 V and θ = 130◦ , the PF requirements are reached. To provide a safety margin, V0 = 100 V has been defined for the proposed ballast. Now, considering V0 = 100 V, flyback components can be defined. Flyback equivalent resistance (Rfly ) must be calculated in order to define the primary winding inductance (LP ) by (10). Therefore, considering that the flyback has an efficiency of 90% V02 (100)2 = 257 Ω. → Rfly = Rfly (35/0.9)

Fig. 10.

Buck output voltage (V0 ) characteristics.

mum input voltage (220 V − 20% = 176 V, so V g = 250 V). Also, the calculated operation point is illustrated in Fig. 10. For V0 = 100 V and Rfly = 257 Ω, it gives RS = 400 Ω. Then, from (5):

(14)

RS =

Thus, from (10), LP = 520 µH. Also, considering that the maximum duty cycle (dmax ) allowed is 0.45, n can be calculated to guarantee DCM operation of the flyback converter. In other words, time t2 must be smaller than (1 − dmax )TS = 11 µs. So, from (12):

=

Pfly =

t2 =

ndTS V0 ≤ 11 µs → n VL ≤

11 · 10−6 · 80 → n ≈ 1. 0.45 · 20 · 10−6 · 100

(15)

Therefore, LS = LS1 = LS2 = 520 µH. Now, to define the buck inductor value (Lbuck ), the buck equivalent resistance (RS ) must be first defined by (6). As can be seen, an explicit expression cannot be attained for RS , and (6) must be solved by means of numerical methods, which can be easily done by any mathematical software (like MathCad). As a result, Fig. 10 illustrates the buck output voltage (V0 ) as a function of the flyback equivalent resistance (Rfly ) for different values of buck resistance RS . The graph was obtained considering the mini-

2Lbuck f → Lbuck d2 400 · 0.452 RS d2max = = 810 µH. 2f 50 · 103 · 2

(16)

Buck capacitor (CB ) is designed according to [22], in order to have a ripple lower than 5%, and its calculated value is 220 µF. The ballast diagram, shown in Fig. 9, also includes the ignition circuit composed of Rign , Cign , spark-gap SG (Epcos A81-A230X, 230 V breakdown voltage), L1 and L2 . During the starting period, SLF2 is closed and SLF1 is open; when the lamp ignites, these switches start to commute. When the lamp is turned off, capacitor Cign (4.7 µF) is charged by Rign (47 kΩ) until the breakdown voltage of SG. Thus, SG conducts and applies Cign voltage in the primary winding (L1 ) of the transformer (nign = 15, 7 : 105 turns on core EE25), which makes L2 voltage (near to 3 kV) start the MHL. After the lamp ignition, the flyback secondary current starts flowing through the lamp and Cign is charged to a voltage lower than the SG breakdown voltage. Therefore, the ignition circuit remains disabled as long as the lamp is on.


Fig. 11. Experimental results of: (a) lamp voltage and current (CH1-50 V/div; CH2-0.5 A/div; 1 ms/div), and (b) line voltage and current (CH1-100 V/div; CH2-0.2 A/div; 5 ms/div).

VIII. E XPERIMENTAL R ESULTS Based on the ballast design presented above, a prototype was carried out (Fig. 9), where: SSH = IXTH13N80 (VDSS = 800 V, RDSon = 0.80 Ω); SLF1 = BUK456 (800 V); SLF2 = IRF830 (500 V); D1 − D4 = 1N4007; DB , DSH1 , DSH2 , and Dfly = MUR160; Cf = 100 nF. Fig. 11 shows the experimental waveforms of: (a) lamp voltage and current, which shows how the ballast supplies the lamp with a LFSW current, avoiding ARs; and (b) shows line voltage and current, denoting the ballast HPF. Lamp voltage and current show a peak during the low-frequency commutation; this is due to the inductive effect of the series igniter. However, as confirmed experimentally, this peak does not represent a problem and can be minimized by the adequate selection of the inductor (L2 ) and filter capacitor (Cf ). Fig. 12(a) shows the buck inductor current at low frequency, where in the line voltage peak, the ballast works in the boundary of the DCM–CCM conduction mode, as detailed in Fig. 12(b). This guarantees that the CCM operation mode is never reached.

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Fig. 12. Buck inductor current: (a) envelopment (0.5 A/div; 1 ms/div) and (b) peak detail (0.5 A/div; 10 µs/div).

Experimental results of SSH switch voltage and current are shown in Fig. 13(a) and (b), together with the flyback and buck current, respectively. These results prove that switch SSH handles only the flyback or the buck current, depending on the operation mode. SLF switch voltage in steady state and buck output voltage (V0 ) are shown in Fig. 13(c) and (d), respectively. The maximum voltage in SLF1 during the lamp starting reaches 600 V, when this switch is open and SLF2 is closed. Therefore, a highvoltage MOSFET was used (BUK456—800 V). Table II presents the numerical experimental results of the proposed ballast, where Vin is the input line voltage, Iin is the input line current, Pin the input power, PF the ballast power factor, THD the total harmonic distortion, VL the rms lamp voltage, IL the rms lamp current, PL the lamp power, and η the ballast efficiency. The line current harmonic content is shown in Table III, which confirms that the proposed ballast complies with the IEC 61000-3-2 class C standard. Standard limits and experimental results in Amperes and in percent values are shown.

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Fig. 13. Experimental results: (a) CH1—SSH switch voltage, CH2—SSH switch current, and CH3—flyback current (CH1-100 V/div; CH2-0.5 A/div; 10 µs/div) for vg = 50 V; (b) CH1—SSH switch voltage, CH2—SSH switch current, and CH3—buck current (CH1-200 V/div; CH2-0.5 A/div; 10 µs/div) for vg = 300 V; (c) SLF switch voltage; and (d) dc bus voltage (V0 ) (50 V/div; 1 ms/div). (d) (25 V/div; 5 ms/div). TABLE II EXPERIMENTAL RESULTS

TABLE III INPUT CURRENT HARMONIC CONTENT

IX. C ONCLUSION A new SS HPF electronic ballast for supplying MHLs has been presented in this paper. The ballast is obtained from the integration of a dc–dc buck converter and a flyback converter with two secondary windings that commutate complementarily at low frequency. Both buck and flyback converters are operated in DCM and at a constant frequency, providing an input PF and line current harmonic content adequate to satisfy present standard requirements. The buck converter has a natural protection

against no-load operation, which makes it a very interesting solution to implement low-cost HPF electronic ballasts. The circuit analysis and experimental results show that the main switch does not suffer with overvoltage or current, which results in a good ballast efficiency. The lamp is supplied by an LFSW current to avoid ARs. A ballast prototype has been implemented at the laboratory to evaluate its possibilities, which provides good results of input PF (complying with IEC 61000-3-2 class C requirements) and ballast efficiency (90%).


In summary, the proposed topology includes only three controlled switches, whereas a typical three-stage commercial ballast uses six controlled switches. The control circuit is therefore greatly simplified, also because the main switch is ground referenced. In addition, the proposed ballast operates in an SS fashion, thus providing a high efficiency (90% compared to 80%), which is the typical efficiency of a three-stage converter. When compared to other possible integrated solutions (e.g., buckboost flyback, boost flyback, flyback flyback), the proposed ballast has the advantage of a lower current through the main switch due to the fact that it only handles the higher of the buck or flyback currents. This also provides higher efficiency when compared with other integrated converters. Another important advantage of the proposed converter is that the dc bus voltage is low. In the presented prototype, operating from a 220 V mains, a rated value of 100 V is used, with a maximum value of 130 V. This allows minimizing the volume of the filter capacitor, and also increasing its life. A typical three-stage ballast with a boost PFC stage would use a bus voltage of about 400 V. In conclusion, the proposed topology appears as a good solution to implement a low-cost HPF electronic ballast to supply MHLs.

R EFERENCES [1] W. Yan, S. Y. R. Hui, and Y. K. E. Ho, “Stability study and control methods for small-wattage high-intensity-discharge (HID) lamps,” IEEE Trans. Ind. Appl., vol. 37, no. 5, pp. 1522–1530, Sep./Oct. 2001. [2] M. W. Fellows, “Comparison of operating characteristics of ceramic metal halide lamps on electronic, magnetic and reference ballasts,” J. Illum. Eng. Soc., vol. 29, no. 2, pp. 106–118, Summer 2000. [3] M. A. Dalla Costa, J. M. Alonso, J. Ribas, J. Cardesín, and J. García, “Acoustic-resonance characterization of low-wattage metal-halide lamps,” IEEE Trans. Plasma Sci., vol. 35, no. 1, pp. 43–58, Feb. 2007. [4] M. A. Dalla Costa, J. M. Alonso, J. García, J. Cardesín, and M. Rico-Secades, “Acoustic resonance characterization of low-wattage metal-halide lamps under low-frequency square-waveform operation,” IEEE Trans. Power Electron., vol. 22, no. 3, pp. 735–743, May 2007. [5] M. Shen, Z. Qian, and F. Z. Peng, “Design of a two-stage low-frequency square-wave electronic ballast for HID lamps,” IEEE Trans. Ind. Appl., vol. 39, no. 2, pp. 424–430, Mar./Apr. 2003. [6] H. Ohguchi, T. Shimizu, H. Takagi, M. H. Ohsato, Q. Mao, and G. Kimura, “Megahertz operation of voltage-fed inverter for HID lamps using distributed constant line,” IEEE Trans. Ind. Appl., vol. 34, no. 4, pp. 747–751, Jul./Aug. 1998. [7] Y. Koshimura, N. Aoike, H. Kobayashi, and O. Nomura, “Several ways for stabilizing HID lamps operation on high frequency power,” J. Illum. Eng. Inst. Jpn., vol. 67, no. 2, pp. 55–61, 1983. [8] M. Ponce, A. Lopez, J. Correa, J. Arau, and J. M. Alonso, “Electronic ballast for HID lamps with high frequency square waveform to avoid acoustic resonance,” in Proc. IEEE APEC, Mar. 4–8, 2001, vol. 2, pp. 658–663. [9] L. Laskai, P. N. Enjeti, and I. J. Pitel, “White-noise modulation of highfrequency high-intensity discharge lamp ballasts,” IEEE Trans. Ind. Appl., vol. 34, no. 3, pp. 597–605, May/Jun. 1998. [10] J. M. Alonso, J. Ribas, M. Rico-Secades, J. G. García, J. Cardesin, and M. A. Dalla Costa, “Evaluation of high-frequency sinusoidal waveform superposed with third harmonic for stable operation of metal halide lamps,” IEEE Trans. Ind. Appl., vol. 41, no. 3, pp. 721–727, May/Jun. 2005. [11] H. Li, M. Shen, and Z. Qian, “A novel low frequency electronic ballast for HID lamps,” in Conf. Rec. IAS Annu. Meeting, Oct. 3–7, 2004, vol. 1, p. 673. [12] M. A. Có, M. Brumatti, D. S. L. Simonetti, and J. L. F. Vieira, “Single stage electronic ballast for HID Lamps,” in Conf. Rec. IAS Annu. Meeting, Oct. 12–16, 2003, vol. 1, pp. 339–344. [13] Y. Yang, Z. Qian, and X. Wu, “A novel single-stage low-frequency squarewave electronic ballast for low-wattage HID lamps,” in Proc. IEEE APEC, 2005, vol. 1, pp. 1048–1052.

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[14] A. F. Zobaa, “Maintaining a good power factor and saving money for industrial loads,” IEEE Trans. Ind. Electron., vol. 53, no. 2, pp. 710–711, Apr. 2006. [15] F. J. Azcondo, C. Branas, R. Casanueva, and S. Bracho, “Power-modecontrolled power-factor corrector for electronic ballast,” IEEE Trans. Ind. Electron., vol. 52, no. 1, pp. 56–65, Feb. 2005. [16] G. K. Andersen and F. Blaabjerg, “Current programmed control of a single-phase two-switch buck-boost power factor correction circuit,” IEEE Trans. Ind. Electron., vol. 53, no. 1, pp. 263–271, Feb. 2006. [17] C. M. Wang, “A new single-phase ZCS-PWM boost rectifier with high power factor and low conduction losses,” IEEE Trans. Ind. Electron., vol. 53, no. 2, pp. 500–510, Apr. 2006. [18] A. Lázaro, A. Barrado, M. Sanz, V. Salas, and E. Olias, “New power factor correction AC-DC converter with reduced storage capacitor voltage,” IEEE Trans. Ind. Electron., vol. 54, no. 1, pp. 384–397, Feb. 2007. [19] J.-Y. Lee, “Single-stage AC/DC converter with input-current dead-zone control for wide input voltage ranges,” IEEE Trans. Ind. Electron., vol. 54, no. 2, pp. 724–732, Apr. 2007. [20] M. G. Egan, D. L. O’Sullivan, J. G. Hayes, M. J. Willers, and C. P. Henze, “Power-factor-corrected single-stage inductive charger for electric vehicle batteries,” IEEE Trans. Ind. Electron., vol. 54, no. 2, pp. 1217–1226, Apr. 2007. [21] J. A. Villarejo, J. Sebastian, F. Soto, and E. Jodar, “Optimizing the design of single-stage power-factor correctors,” IEEE Trans. Ind. Electron., vol. 54, no. 3, pp. 1472–1482, Jun. 2007. [22] J. M. Alonso, A. J. Calleja, J. Ribas, E. L. Corominas, and M. Rico-Secades, “Analysis and design of a novel single-stage highpower-factor electronic ballast based on integrated buck half-bridge resonant inverter,” IEEE Trans. Power Electron., vol. 19, no. 2, pp. 550–559, Mar. 2004. [23] M. A. Dalla Costa, J. M. Alonso, J. Cardesin, and J. García, “Lowcost electronic ballast to supply MH lamps based on flyback converter,” Electron. Lett., vol. 41, no. 10, pp. 615–616, May 2005. [24] S. Ben-Yaakov, “Low frequency inverter fed by a high frequency AC current source,” U.S. Patent 20 050 110 431, May 26, 2005. [25] J. M. Alonso, A. J. Calleja, J. Ribas, E. López, M. Rico, and J. Sebastián, “Using input current shaper in the implementation of high-power-factor electronic ballasts,” in Proc. IEEE APEC, Dallas, TX, 1999, pp. 746–752. [26] J. M. Alonso, P. J. Villegas, J. Díaz, C. Blanco, and M. Rico, “A microcontroller-based emergency ballast for fluorescent lamps,” IEEE Trans. Ind. Electron., vol. 44, no. 2, pp. 207–216, Apr. 1997. [27] M. A. Dalla Costa and R. N. do Prado, “Lamp improved arrangement in the half-bridge topology,” IEEE Trans. Ind. Electron., vol. 53, no. 5, pp. 1754–1756, Oct. 2006.

Marco A. Dalla Costa (S’03) was born in Santa Maria, Brazil, in 1978. He received the B.S. and M.Sc. degrees in electrical engineering from the Federal University of Santa Maria, Santa Maria, Brazil, in 2002 and 2004, respectively. Since 2004, he is currently working toward the Ph.D. degree in the University of Oviedo, Gijón, Spain. He is currently a Researcher working on the development of electronic systems for lighting and high-intensity-discharge (HID) lamp modeling. His research interests include dc/dc converters, powerfactor-correction stages, dimming systems, high-frequency electronic ballasts, discharge lamp modeling, and electronic starters for HID lamps.

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J. Marcos Alonso (S’94–M’98–SM’03) received the M.Sc. and Ph.D. degrees in electrical engineering from the University of Oviedo, Gijón, Spain, in 1990 and 1994 respectively. From 1990 to 1999, he was an Assistant Professor at the Electrical and Electronic Department of the University of Oviedo, where he has been an Associate Professor since 1999. He is the primary author for more than 60 journal and international conference papers in power and industrial electronics, and has coauthored more than 100. His research interests include high-frequency electronic ballasts, discharge lamp modeling, power converters for ozone generation, power converters for electrostatic applications, power factor correction topologies and high frequency switching converters. He was the advisor of four Ph.D. theses in the field of power electronics. He is the holder of four Spanish patents with two under review. Dr. Alonso was awarded with the Early Career Award of the IEEE Industrial Electronics Society in 2006. He received the second prize paper award of the 2005 IEEE Industry Applications Society Meeting, Production and Application of Light Committee. He was also awarded with the IEEE Industrial Electronics Society Meritorious Paper Award for 1996. He collaborates as transactions paper reviewer and conference session chairman, among other positions, for the IEEE. Since October 2002, he has served as an Associate Editor of the IEEE TRANSACTIONS ON POWER ELECTRONICS in the field of Lighting Applications. He has served as a Guest Editor for the Special Issue on Lighting Applications, published in IEEE TRANSACTIONS ON POWER ELECTRONICS in May 2007. He is also a member of the International Ozone Association.

Jorge García (S’01–M’05) was born in Madrid, Spain, in 1975. He received the M.Sc. and Ph.D. degrees in electrical engineering from the University of Oviedo, Gijón, Spain, in 2000 and 2003, respectively. In December 1999, he joined the Department of Electrical and Electronic Engineering, University of Oviedo. He is currently a Researcher, working on the development of electronic systems for lighting and electronic switching power supplies. Since 2002, he also is an Assistant Professor in several matters related to electronics. He is currently Associate Professor in the same University. His research interests include dc/dc converters and power-factor-correction stages, switching power supplies, HF inverters for discharge lamps, electronic starters for high-intensity-discharge lamps, and electronic drivers for LEDs.

Jesús Cardesín Miranda (S’01–A’03–M’04) was born in Oviedo, Spain, in 1970. He received the M.Sc. and Ph.D. degrees from the University of Oviedo, Gijón, Spain, in 1995. In 1999, he joined the Electrical and Electronic Department, University of Oviedo, where he is currently an Associate Professor. His research interests include dc/dc converters, electronic light systems, switching power supplies, inverters and high-powerfactor rectifiers.

Diego G. Lamar (S’05) was born in Zaragoza, Spain, in 1974. He received the M.Sc. degree in electrical engineering from the University of Oviedo, Gijón, Spain, in 2003. In 2003, he became a Research Engineer at the University of Oviedo and since September 2005, he has been an Assistant Professor. His research interests are switching-mode power supplies, converter modeling, and power-factor-correction converters.