A Single-Stage Power Factor Correction AC/DC ... - IEEE Xplore

IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 21, NO. 1, JANUARY 2006

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A Single-Stage Power Factor Correction AC/DC Converter Based on Zero Voltage Switching Full Bridge Topology With Two Series-Connected Transformers Tae-Sung Kim, Gwan-Bon Koo, Member, IEEE, Gun-Woo Moon, Associate Member, IEEE, and Myung-Joong Youn, Senior Member, IEEE

Abstract—A single-stage power factor correction ac/dc converter based on zero voltage switching (ZVS) full bridge topology with two series-connected transformers is proposed in this paper. The proposed converter offers a very wide ZVS range due to the configuration of two series-connected transformers. It features a high efficiency over wide load ranges. Furthermore, it shows the low voltage stress on a dc link capacitor. The proposed converter also gives the high power factor and low input current harmonics complied with IEC 61000-3-2 Class D requirements by integrating a boost stage operated in a discontinuous current mode. The ZVS conditions, large signal modeling, and design procedure are discussed in detail. Experimental results are presented to show the validity of the proposed converter. Index Terms—Full bridge (FB), power factor correction (PFC), single-stage, two series-connected transformers, zero voltage switching (ZVS).

I. INTRODUCTION

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OWADAYS, a switch mode power supply (SMPS) is required to realize high power factor and low input current harmonics complied with harmonic standards such as IEC 61 000-3-2 together with a small size. Increasing the switching frequency can make the size of SMPS smaller. However, it produces higher switching losses, which result in a low efficiency. Therefore, it is necessary to use the soft switching technique in order to overcome this disadvantage. A zero voltage switching (ZVS) technique can be used to reduce switching losses. The approaches to obtain the low input current harmonics and high power factor are largely classified into the two-stage and single-stage approaches. In the two-stage approach, a nonisolated boost type converter is used for the power factor correction (PFC), which is followed by an isolated dc/dc converter. Therefore, this approach gives a good performance of low input current harmonics, high power factor, and fast output voltage regulation. However, since two separated converters are controlled independently in this approach, it is not suitable for low power

Manuscript received August 5, 2004; revised April 22, 2005. Recommended by Associate Editor K. Smedley. The authors are with the Department of Electrical Engineering and Computer Science, Korea Advanced Institute of Science and Technology, Daejeon 305701, Korea (e-mail: [email protected]; [email protected]; [email protected]; [email protected]). Digital Object Identifier 10.1109/TPEL.2005.861200

levels due to the cost of additional switches and control circuitry. To overcome this disadvantage, the single-stage approach suitable for low power levels has been introduced. In order to reduce the cost of overall systems, switches used in the dc/dc converter are also used for the PFC so that only one controller is used in this approach. Although this approach has the disadvantages that the dc link voltage is not regulated due to the lack of controller for the PFC, the current stress on switches is higher than that in the two-stage approach, and it gives a lower efficiency compared with the two-stage approach, it is a good cost-effective solution for low power levels. Since this approach usually employs a boost converter operated in a discontinuous current mode (DCM) to achieve the PFC, it gives a good performance of low input current harmonic distortion and high power factor [1]–[4]. A conventional single-stage PFC full bridge (FB) converter features the low input current harmonics, high power factor, and ZVS operation without auxiliary circuits, i.e., only by controlling the duty ratio of switches complementarily [5]. However, this converter has a serious disadvantage of very narrow ZVS range of lower switches. Since the output inductor is reflected into the primary current path until the ZVS operation of upper switches ends completely, this ZVS operation is done by the energy stored in both the boost input inductor and the output inductor. Therefore, it is easy to achieve the ZVS of upper switches. However, the dc link voltage is only placed across the leakage inductor during the ZVS operation of lower switches. Thus, only the energy stored in this inductor affects the ZVS of lower switches. If the energy stored in this inductor is less than the energy needed for the ZVS of lower switches, it is difficult to achieve the ZVS of lower switches. Since the energy stored in the leakage inductor is a function of the load current, the ZVS is lost at a light load. If the leakage inductor is increased to extend the ZVS range, the effective duty ratio is reduced. As a result, the conduction loss and the current stress on main switches increase. Therefore, a lot of researches have been proposed to extend the ZVS range down to a light load without an effective duty loss. The nondissipative snubber composed of the resonant inductor, resonant capacitors, diodes, and auxiliary switches is proposed in [6], zero voltage transition circuits composed of resonant inductors, saturable inductors, diodes, and auxiliary switches are added in [7], and a resonant cell composed of resonant capacitors and inductors, diodes, and auxiliary switches is used in [8]. However, there are some disadvantages in these methods.

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Fig. 1.


Proposed converter.

Although the ZVS range of lower switches is extended, the switching and conduction losses generated in the auxiliary circuits for the ZVS operation can decrease the total efficiency. Moreover, not only auxiliary circuits increase the size and cost of overall system, but also the current stress on main switches is increased due to the resonant current for the ZVS operation generated in auxiliary circuits. In this paper, a single-stage PFC ac/dc converter based on the ZVS FB topology with two series-connected transformers is proposed to extend a ZVS range of main switches without any auxiliary circuits. Since two series-connected transformers act as not only a main transformer but also an output inductor, there is no need to use an output inductor [9], [10]. It offers a dramatically wide ZVS range for all switches without reducing an effective duty ratio due to two series-connected transformers. Moreover, there are no excessive power loss and increased current stress on main switches caused by auxiliary circuits for ZVS operation. Thus, it features high efficiency. Also, the proposed converter has the low input current harmonics and high power factor by integrating a boost stage operated in a DCM to achieve the PFC. The operational principles by the mode analysis, ZVS condition of lower switches, large signal modeling, design procedure, and experimental results are presented to show the validity of the proposed converter. II. OPERATION OF THE PROPOSED CONVERTER The basic structure of the proposed converter is shown in is a filtered and rectified line Fig. 1. The input voltage voltage. The proposed converter seems to be almost the same as a conventional single-stage PFC FB converter in [5] except for having two series-connected transformers with no output inductor. The boost PFC part of the proposed converter is operated in DCM for the low input current harmonics and high power factor. The dc/dc conversion part based on the FB topology with two series-connected transformers is operated in the continuous current mode (CCM) at full load and operated in the DCM at light load in order to restrict the dc link voltage. In order to simplify the mode analysis, several assumptions are made as follows: , 1) two transformers are identical ( ); 2) all diodes are ideal; 3) switches are ideal except for output capacitances and internal diodes, and identical ; are and the output voltage 4) the dc link voltage constant.

Fig. 2.

Key waveforms of the proposed converter.

Fig. 2 shows the key waveforms of the proposed converter in steady state, where a shadowed area is the input current is a turn-on time of lower switches, flowing to switches, is a time when there is no energy transfer from the and dc link capacitor to the load due to two leakage inductors. The modes of the proposed converter for one switching period are divided into ten as shown in Fig. 3. A. Mode 1 When the currents flowing through secondary diodes and are commutated perfectly at , is turned off. Therefore, the energy is transferred from the dc link capacitor to the load through the transformer as a forward transas an inductor stores the former, and the transformer . The energy stored in during this mode energy from in all modes except for is discharged to the load through stores the energy from the recmode 1. The input inductor so that the input current flowing tified input voltage increases linearly. The input current through diode and primary current are represented as follows:

(1) B. Mode 2 When switch is turned off at , the output capacitor of begins to be charged and the output capacitor

KIM et al.: SINGLE-STAGE POWER FACTOR CORRECTION AC/DC CONVERTER

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Fig. 3. Equivalent circuits for each mode: (a) Mode 1, (b) mode 2, (c) mode 3, (d) mode 4, (e) mode 5, (f) mode 6, (g) mode 7, (h) mode 8, (i) mode 9, and (j) mode 10.

of begins to be discharged. Since still acts as an inductor and charging are finished comuntil discharging pletely, the charge and discharge of these capacitors are done and . Therefore, the ZVS by the energy stored in both is represented as follows: condition of

(2)

, , and is In this equation, the energy stored in and discharging larger than the energy charging [11]. Therefore, it is easy to achieve the ZVS of upper switch at a very light load. and discharging , the energy stored After charging is transferred to the dc link capacitor through and in . Also, the primary current begins to freewheel through upper switches and , and the energy stored in and is discharged to the load through and , respec-

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tively. The input current represented as follows:


and primary current

are

(3)

C. Mode 3 When the input current becomes zero at , both and are turned off and charging the dc link capacitor ends. The and primary current still freewheels through upper switches , and the energy stored in and is still discharged to and , respectively. The input current the load through and primary current are represented as follows:

(4)

D. Mode 4 When switch is turned off at , the input current still maintains zero, the primary current flows back to the dc link caand is still discharged pacitor, and the energy stored in and , respectively. The output cato the load through of begins to be charged and the output capacpacitor of begins to be discharged by the primary current itor flowing back to the dc link capacitor. In a conventional singlestage PFC FB converter controlling the duty ratio of switches complementarily, since the leakage inductor only contributes to and discharging , it is difficult to achieve charging at a light load. However, the prothe ZVS of lower switch posed converter has a dramatically wide ZVS range of lower since the ZVS conditions are varied according to switch load conditions (heavy, light, and very light load) due to two seand priries-connected transformers. The input current are represented as follows: mary current

(5)

E. Mode 5 When switch is turned on at , the input inductor stores the energy from the rectified input voltage so that flowing through diode increases the input current and are linearly. Since the currents flowing through not commutated perfectly in this mode, they are still turned on. and there Therefore, the dc link voltage is placed across two to the load. The primary current is no energy transfer from changes its polarity to the opposite direction in this mode. The and primary current are represented input current as follows:

(6)

Fig. 4. Magnetizing and primary currents under load variations: (a) heavy load condition, (b) boundary load condition, (c) light load condition, and (d) very light load condition (DCM operation).

F. Modes 6 10 The operations from mode 6 to mode 10 are the same as previous modes except for the direction of the primary current. At the end of mode 10, one period is completed and the operation is repeated.

III. ZVS CONDITION OF LOWER SWITCHES In a conventional single-stage PFC FB converter controlling the duty ratio of switches complementarily, it is difficult to achieve the ZVS of lower switches at a light load since the leakage inductor only affects the ZVS condition [5]. However, the proposed converter has a dramatically wide ZVS range and without auxiliary circuits. It is for lower switches achieved by just controlling the duty ratio of switches complementarily, since the ZVS conditions are varied according to load conditions (heavy, light, and very light load) due to two series-connected transformers. The magnetizing currents and of two transformers and the primary are shown in Fig. 4. The magnetizing currents current and swing around a positive current offset of and negative current offset of , respectively. Fig. 4(a)–(d) show the primary and magnetizing currents in a heavy, boundary, light, and very light load conditions, respectively.


A. Heavy Load Condition and do not change their directions at Both a heavy load as shown in Fig. 4(a). During the ZVS operation and are turned on so that of lower switches, both is placed only across two leakage the dc link voltage inductors. It is similar to a conventional single-stage PFC FB converter. That is, the ZVS condition for lower switches of the proposed converter is dependent on the leakage inductance in a heavy load. However, the leakage inductance of the proposed converter is naturally doubled because of two series-connected transformers compared with a conventional single-stage PFC FB converter. Therefore, the ZVS condition of lower switches is represented in a heavy load as follows: (7) At a heavy load, it is easier to achieve the ZVS condition in the proposed converter than in a conventional single-stage PFC . Therefore, the ZVS range of the FB converter due to proposed converter is extended at a heavy load. B. Light Load Condition As the load decreases, the current offsets of and are close to zero. Fig. 4(b) shows a boundary situation affects the ZVS condition of lower switches. If the where output current is higher than the boundary output current , the ZVS condition of lower switches is the same as the is lower than , and (7). However, if change their directions in some interval including the ZVS duration of lower switches as shown in Fig. 4(c). Therefore, is equal to or , the ZVS of lower until switches is achieved by . However, after is equal to or , either or acts as an inductor so that or contributes to the ZVS the magnetizing inductance condition of lower switches, which is represented as follows: (8)

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an inductor. Therefore, the ZVS condition of lower switches is represented as follows: (9) In this proposed converter, not only the doubled leakage inductance due to two series-connected transformers makes it easy to achieve the ZVS condition of lower switches at a heavy load, but also the magnetizing inductance makes it easy to do at a light load. Therefore, the proposed converter has a dramatically wide ZVS range for lower switches without auxiliary circuits compared with a conventional single-stage PFC FB converter. IV. LARGE SIGNAL MODELING AND DESIGN PROCEDURE When the dc/dc conversion part is operated in a CCM and the load decreases, the dc link voltage increases due to the power unbalance between input and output. The dc link voltage becomes highest in a CCM/DCM boundary. When the dc/dc conversion part is operated in a DCM, the dc link voltage is maintained at a constant value without regard to load variations due to the power balance between input and output. If the dc/dc conversion part is designed to operate in a DCM at a full load, main switches with a high current rating are required, which reduces an efficiency compared with operating in a CCM at a full load. Therefore, in order to reduce a switch current rating and restrict the dc link voltage, the dc/dc conversion part is designed to operate in a CCM at a full load and in a DCM at a light load. The large signal modeling approach for the proposed con, verter is based on [12] and [13]. The dc link voltage output voltage , and output current are chosen as state variables. In order to simplify the large signal modeling, several assumptions are made as follows: 1) switches and diodes are ideal; 2) dead-times are neglected; 3) two transformers are identical and ideal ( , 0). When the dc/dc conversion part of the proposed converter is operated in a CCM, the large signal modeling equations are obtained from Fig. 5(a) as follows:

Therefore, at a light load, the ZVS condition of lower switches in the proposed converter is achieved more easily compared with a conventional single-stage PFC FB converter. C. Very Light Load Condition (DCM Operation) In Fig. 4(a)–(c), the dc/dc conversion part of the proposed converter operates in a CCM. However, if the load becomes very light, the dc/dc conversion part operates in a DCM and the primary and magnetizing currents flow as shown in Fig. 4(d). In the DCM operation, there is some interval when and become equivalent before the upper switch or is turned off. If and become equivalent, both and are turned off, and also both and act as inductors. Then, when either or is turned off, the output capacitor of the upper switch begins to be charged so that one transformer acts as a forward transformer and the other acts as

(10) . where The steady state equations of the dc link voltage and output voltage in a CCM operation of the dc/dc conversion part are obtained by averaging the large signal modeling (10) for one switching period as follows:

(11)

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When the dc/dc conversion part of the proposed converter is operated in a DCM at a light load, the large signal modeling equations are obtained from Fig. 5(b) as follows:

(12) where

, , . The steady state equations of the dc link voltage and output voltage in a DCM operation of the dc/dc conversion part are obtained by averaging the large signal modeling (12) for one switching period as follows:

(13) where 1 . In order to illustrate the converter operation, the components of the proposed converter based on steady state equations and ZVS condition are selected with the following specifications. • Input voltage 110 V(rms), 60 Hz. • Output voltage 25 V. • Output power 25 to 125 W. • Switching frequency 100 kHz. • DC link voltage 450 V. • Maximum duty ratio 0.26. A. Selection of the Turns Ratio of the Transformer Input Inductance

and the

The condition to guarantee a DCM operation of the input inductor becomes from Fig. 5(a) as follows: (14) where . The boundary of the dc link voltage for a DCM operation of the input inductor can be obtained from the (14) for a full load condition as follows: (15) The turns ratio of the transformer can be obtained from the (11) as (16) The

can also be selected from the (11) as (17)

Fig. 5. Key waveforms for large signal modeling: (a) CCM operation of dc/dc conversion part and (b) DCM operation of dc/dc conversion part.

The minimum dc link voltage for a DCM operation of the input inductor is obtained as 324.1 V from the (15). If the dc link voltage at a full load is higher than 324.1 V, a DCM operation of the input inductor is guaranteed. The higher the dc link voltage is, the higher the turns ratio of the transformer is. Therefore, the dc link voltage at a full load is selected as 390 V in this design so that and are obtained as 4 and 90 H from the (16) and (17), respectively.


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Fig. 7.

Fig. 6.

Input voltage and current waveforms at a full load.

Calculated dc link voltage under load variations.

B. Selection of the Magnetizing Inductance The dc link voltage is highest in a CCM/DCM boundary of the dc/dc conversion part. Since the maximum dc link voltage is restricted below 450 V, the dc/dc conversion part is designed to operate with a CCM/DCM boundary at a 70% of full load as shown in Fig. 6. If it is assumed that the leakage inductance is neglected, then the output current ripple is represented as follows: (18) The magnetizing inductance as

can be selected from the (18)

(19) In a DCM/CCM boundary, the dc link voltage is 448 V, duty ratio is 0.223, and output current ripple is 7 A. Therefore, based on these values, is obtained as 316 H from the (19). C. Selection of the Leakage Inductance When the output current is higher than the boundary output current , shown in Fig. 4(b), the ZVS condition of lower switches is only dependent on . However, if is lower than , contributes to the ZVS condition of lower switches. Therefore, should be selected from the (7) at to achieve the ZVS condition of lower switches over whole load variations. The boundary output current is obtained from the fact that the average current of is equal to as follows: (20) can be calculated as 9.4 A The boundary output current from the (20) based on the predetermined values of 390 V, 316 H, 5 A, and 4 at a full load condition. Since the output current at a full load, 5 A,

Fig. 8. Input current harmonics at a full load.

is lower than the boundary output current, 9.4 A, contributes to the ZVS condition of lower switches at a full load. Therefore, even if the leakage inductance is zero, the ZVS condition of lower switches in the proposed converter is guaranteed over whole load variations without auxiliary circuits. Thus, the leakage inductance had better be as small as possible in manufacturing the main transformer. V. EXPERIMENTAL RESULTS In order to verify the behavior and analysis of the proposed converter, a prototype converter has been designed as in Section IV. Fig. 7 shows the filtered input current and input voltage at a full load. These waveforms show that the input current is nearly sinusoidal and in phase with the input voltage. The input current harmonics at a full load and the measured power factor under load variations are shown in Figs. 8 and 9, respectively. The measured power factor is above 0.915 over whole load variations and all input current harmonics meet the IEC 61 000-3-2 Class D requirements. Fig. 10 shows an input current total harmonic distortion (THD) of the proposed converter. Over whole load variations, the input current THD is below 13.05%. Fig. 11 shows the measured dc link voltage under load variations. The maximum dc link voltage is about 446 V in a DCM/CCM boundary of the dc/dc conversion part. The difference between the calculated dc link voltage shown in Fig. 6 and the measured dc link voltage shown in Fig. 11 is caused by the losses of real elements. Fig. 12 shows the ZVS under load variations. Since conditions of the lower switch contributes to the ZVS condition of lower switches, the is extended to about 10% ZVS range of the lower switch

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Fig. 9.


Power factor under load variations.

Fig. 12. ZVS conditions of lower switch under load variations: (a) full load condition, (b) 60% load condition, (c) 10% load condition, and (d) 5% load condition.

Fig. 10.

Input current THD under load variations.

Fig. 13.

Efficiency under load variations.

VI. CONCLUSION

Fig. 11.

Measured dc link voltage under load variations.

load. Finally, the maximum efficiency is about 85% as shown in Fig. 13.

In this paper, a single-stage power factor correction ac/dc converter based on zero voltage switching FB topology with two series-connected transformers has been proposed. The proposed converter has a dramatically wide ZVS range for lower switches without auxiliary circuits by just complementarily controlling the duty ratio of switches due to two series-connected transformers. It has also high efficiency due to a wide ZVS


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range. The proposed converter also gives the high power factor and low input current harmonics complied with IEC 61 000-3-2 Class D requirements by integrating the boost stage operated in the DCM in order to achieve the PFC. The operational principles have been presented by the mode analysis, and the steady state equations have been derived according to the large signal modeling. From these steady state equations, the design equations have been found and a prototype converter with 25 V, 5-A output has been designed to prove the validity of the proposed converter. The experimental results show that the power factor is above 0.915, the input current THD is below 13.05% over whole load variations, and the proposed converter meets IEC 61 000-3-2 Class D requirements. The ZVS range of lower switches is extended dramatically to very light load. The maximum dc link voltage is about 446 V and the maximum efficiency is about 85%.

Tae-Sung Kim was born in Jeonbuk, Korea, in 1975. He received the B.S. degree from Chonbuk National University, Jeonbuk, in 2001, and the M.S. degree in electrical engineering from the Korea Advanced Institute of Science and Technology (KAIST), Daejeon, in 2003, where he is currently pursuing the Ph.D. degree in electrical engineering. His research interests are in the areas of power electronics and control, including analysis, modeling, and design of power converters, soft-switching power converters, resonant converters, distributed power systems, power-factor correction, and digital display driver systems. Mr. Kim is a member of the Korean Institute of Power Electronics (KIPE).

REFERENCES [1] F. Canales, D. Abud, J. Arau, and G. Jimenez, “Design of a two stage, 1 kW battery charger with power factor correction,” in Proc. IEE Power Electronics Variable-Speed Drives Conf., 1994, pp. 626–631. [2] E. X. Yang, Y. Jiang, G. Hua, and F. C. Lee, “Isolated boost circuit for power factor correction,” in Proc. IEEE APEC, 1993, pp. 196–203. [3] J. Zhang, M. M. Jovanovic´ , and F. C. Lee, “Comparison between CCM single-stage and two-stage boost PFC converters,” in Proc. IEEE APEC, 1999, pp. 335–341. [4] C. Qiao and K. M. Smedley, “A topology survey of single-stage power factor corrector with a boost type input-current-shaper,” IEEE Trans. Power Electron., vol. 16, no. 3, pp. 360–368, May 2001. [5] M. Qiu, G. Moschopoulos, H. Pinheiro, and P. Jain, “A PWM full-bridge converter with natural input power factor correction,” in Proc. IEEE PESC, 1998, pp. 1605–1612. [6] K. L. Fontoura, J. A. C. Pinto, V. J. Farias, L. C. de Freitas, and J. B. Vieira Jr., “Application of the nondissipative snubber in the ac/dc full-bridge converter and high power factor operation,” in Proc. IEEE INTELEC, 2000, pp. 665–670. [7] A. K. S. Bhat and R. Venkatraman, “A soft-switched full-bridge singlestage AC-to-DC converter with low input current harmonic distortion,” in Proc. IEEE PESC, 2000, pp. 799–804. [8] C. A. Gallo, J. A. C. Pinto, L. C. de Freitas, V. J. Farias, E. A. A. Coelho, and J. B. Vieira Jr, “An unity high power factor power supply rectifier using a PWM ac/dc full bridge soft-switching,” in Proc. IEEE APEC, 2002, pp. 1190–1194. [9] G.-B. Koo, G.-W. Moon, and M.-J. Youn, “Analysis and design of phase shift full bridge converter with two series-connected transformers,” IEEE Trans. Power Electron., vol. 19, no. 2, pp. 411–419, Mar. 2004. [10] G.-B. Koo, T.-S. Kim, G.-W. Moon, and M.-J. Youn. Analysis and design of a new phase shift full bridge converter with series-connected two transformers. presented at 10th EPE. [CD-ROM] [11] J. A. Sabate, V. Vlatkovic, R. B. Ridel, F. C. Lee, and B. H. Cho, “Design considerations for high-voltage high-power full-bridge zero-voltage-switched PWM converter,” in Proc. IEEE APEC, 1990, pp. 275–284. [12] S. Singer, “The application of loss-free resistors in power processing circuits,” IEEE Trans. Power Electron., vol. 16, no. 4, pp. 595–600, Oct. 1991. [13] M. Madigan, R. Erickson, and E. Ismail, “Integrated high quality rectifier-regulators,” IEEE Trans. Ind. Electron., vol. 46, no. 4, pp. 749–758, Aug. 1999.

Gwan-Bon Koo (S’04–M’05) was born in Seoul, Korea, in 1975. He received the B.S. and M.S. degrees in electrical engineering and the Ph.D. degree in electrical engineering and computer science from the Korea Advanced Institute of Science and Technology (KAIST), Daejeon, in 1997, 1999, and 2004, respectively. He is currently a Senior Engineer with Fairchild Korea Semiconductor Ltd., Bucheon-City, Korea. His research interests are in the areas of power electronics and control, including analysis, modeling, and design of high-performance power converters, soft-switching power converters, distributed power systems, power-factor correction, and resonant converters. Dr. Koo is a Member of the Korean Institute of Power Electronics (KIPE).

Gun-Woo Moon (S’92–A’96) was born in Korea in 1966. He received the B.S. degree from Han-Yang University, Seoul, Korea, in 1990 and the M.S. and Ph.D. degrees in electrical engineering from the Korea Advanced Institute of Science and Technology (KAIST), Daejeon, in 1992 and 1996, respectively. He is currently an Associate Professor in the Department of Electrical Engineering and Computer Science, KAIST. His research interests include modeling, design and control of power converters, soft-switching power converters, resonant inverters, distributed power systems, power-factor correction, electric drive systems, driver circuits of plasma display panels, and flexible ac transmission systems. Dr. Moon is a member of the Korean Institute of Power Electronics (KIPE), the Korean Institute of Electrical Engineers (KIEE), the Korea Institute of Telematics and Electronics (KITE), and the Korea Institute of Illumination Electronics and Industrial Equipment (KIIEIE).

Myung-Joong Youn (S’74–M’78–SM’98) was born in Seoul, Korea, in 1946. He received the B.S. degree from Seoul National University, Seoul, in 1970 and the M.S. and Ph.D. degrees in electrical engineering from the University of Missouri, Columbia, in 1974 and 1978, respectively. In 1978, he joined the Air-Craft Equipment Division, General Electric Company, Erie, PA, where he was an Individual Contributor on Aerospace Electrical System Engineering. Since 1983, he has been a Professor at the Korea Advanced Institute of Science and Technology (KAIST), Daejeon. His research activities are in the areas of power electronics and control, which include the drive systems, rotating electrical machine design, and high-performance switching regulators. Dr. Youn is a member of the Institution of Electrical Engineers, U.K., the Korean Institute of Power Electronics (KIPE), the Korean Institute of Electrical Engineers (KIEE), and the Korea Institute of Telematics and Electronics (KITE).