A Single-Stage Power Factor Correction Switched

A Single-Stage Power Factor Correction Switched Mode Power Supply

POSTIGLIONE Cícero

A Single-Stage Power Factor Correction Switched Mode Power Supply Cícero S. Postiglione, Arnaldo J. Perin INSTITUTE OF POWER ELECTRONICS INEP FEDERAL UNIVERSITY OF SANTA CATARINA - UFSC P.O. Box 5119 - 88040-970 Florianópolis, Brazil Email: [email protected] URL: http://www.inep.ufsc.br

Claudinor B. Nascimento TECHNOLOGICAL FEDERAL UNIVERSITY OF PARANÁ Ponta Grossa Campus Av. Monteiro Lobato s/n – km 04 84016-210 Ponta Grossa, Brazil Email: [email protected]

Acknowledgements The authors would like to thank Cnpq, FINEP and CEBRA for the financial support.

Keywords «Switched-mode power supply», «Power factor correction», «ZVS converters».

Abstract This paper presents a single-stage power factor corrected ac-dc converter based on a half-bridge topology. The proposed converter make use of the charge-pump and interleaving techniques resulting in near unity power factor and ripple free input current, meeting the IEC 61000-3-2 regulations for wide-load ranges. It is also a cost effective and competitive solution for 100 - 600 W applications where a two stage approach is costly and passive filters are not recommended. It works with zero voltage switching (ZVS) for a reasonable load variation range, achieving higher efficiency at higher load conditions. To overcome the excessive elevation of the Dc-link voltage in lower load situations, a common problem of single-stage PFC solutions, frequency variation and PWM control are used simultaneously.

Introduction Today, there are over 10 Billion electronic power supplies in use worldwide. These power supplies are used to convert high voltage AC to the low voltage AC or DC needed to power various consumer and office electronic products. During the conversion process, some of the energy is converted to waste heat. The typical efficiency of these power supplies lies within the range of 30% to 60% [1]. Over the past years, the United States (Environmental Protection Agency (EPA) ENERGY STAR® program and the State of California), China, Europe, Canada, and Australia have been working together to explore ways to encourage the improved energy efficiency of external power supplies and thereby reduce the power consumed by those finished products that are sold with an external power supply. The environmental advocacy group Natural Resources Defense Council (NRDC) estimates that movement toward more efficient external power supplies has the potential to save more than 25 billion kWh annually on a worldwide basis [2]. Thus, it would seem prudent to consider high efficiency one of the design rules in any new power supply design. While full-load efficiency is important, new requirements are demanding a flatter efficiency curve, with requirements at light loads as well. While the requirements for external power supplies specify efficiency, averaging data at four different load values (25%, 50%, 75% and 100% of rated load), the internal computer power supply requires a minimum efficiency given for each of four different loads. In either case, maintaining high efficiency at a load of 20% of rated power represents a significant design task. And the problem is further exacerbated when the system under power can

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achieve a very low standby or off state, so that “no load” operation also applies to the power supply [1]. Besides the efficiency, another important characteristic to be considered is the power factor, since it affects how much energy can be drained from the utility line. Therefore, high power factor with low total harmonic distortion (THD) is also a requirement to a modern power supply design. However, today, to meet these requirements, such as the IEC 61000-3-2, the PFC is only required (or measured) at the rated power. Recent studies have shown that a commercial desktop computer, for example, is in “idle mode” most of the time [1]. Thus it would be natural to have PFC at low power levels too. Accordingly, future requirements will probably follow this proclivity, in order to improve the efficiency of the utility lines. In this paper a single-stage PFC converter suitable for 100 - 600 W switch-mode power supplies is presented. The main advantages of the proposed converter are close to unity power factor and high efficiency, both for wide-load range, with low cost and high density power. The converter topology was proposed in [4] and it is based on the charge-pump voltage-source technique, which is usually used for electronic ballasts. It was first presented with variable frequency control, which resulted in high efficiency (above 80%) and 0.99 PF for a load variation from 100% to 50% and with no elevation of the dc bus voltage. However, it has problems with very low load (lower than 20%), because the switching frequency becomes too high and the ZVS is lost. Therefore, reducing efficiency and making it difficult to design optimized magnetic elements and filters. In this paper, it is shown that it is possible to control the converter with PWM and narrower frequency variation for wide-load variation, with good efficiency, but with the cost of Power Factor (PF) reduction and higher dc-link voltage in light load conditions. But, it will also be shown that the reduction in PF is minimal. There are different ways to implement the PWM control. In this approach, the active switches are driven symmetrically. In other words, if one of the switches has duty cycle D, the other switch duty cycle is (1-D). Since the converter is symmetric, the duty cycle must vary from 0 to 0.5 or 0.5 to 1, with 0.5 being the operation point for the maximum power transfer.

Proposed Converter The proposed converter, shown in Fig. 1, is a composition of two charge-pump converters, which work in a complementary fashion, and a half-bridge converter with pulse width modulation and zero voltage switching (HB-PWM-ZVS). Both, the PFC and the dc-dc converters share the same power switches, which is a characteristic of single-stage topologies.

Fig. 1: Proposed converter. An advantage of this PFC technique over most single-stage solutions based on DCM operation is that the current through the input filter inductor, Lf, is in continuous conduction mode (CCM) with a current ripple of twice the switching frequency, which allows a significant reduction of size and weight of the filtering element. This is possible through the complementary operation of the chargepump circuits, which is analogous to the interleaved boost converter [5], [6]. In addition, inductors Lin1 and Lin2 can be coupled, eliminating the necessity of inductor Lf and reducing two magnetic cores from the circuit. Further, if inductance Lr is considered the transformer leakage inductance and this

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transformer is properly design so that no external inductance is necessary, this converter can be build with low component count. This configuration with coupled inductors is not studied in this paper. The use of charge-pump topologies in PFC applications has shown good results in lighting applications, presenting high efficiency and theoretically unity power factor [7] and [8]. However, in the abovementioned applications, with exception for the turn on transient, the load is usually constant, while switch mode power supplies must deal with wide-load ranges, making de design task much more challenging. In [4] a duty cycle of 0.5 was preferred to ensure symmetry of the inductors (Lin) currents and capacitors (Cf) voltages. Therefore, it was necessary to vary the switching frequency to regulate the output voltage. But, it is also possible to control the converter by varying the duty cycle (PWM). However, the voltage across capacitors Cf and Ce will depend on the duty cycle and must tolerate voltage levels higher than Vi/2. Further, the unbalanced current through inductors Lin would distort the input current, reducing the power factor. And, like other fixed frequency single-stage solutions, when the output power is reduced, the dc-link voltage increases. In this paper a combination of both techniques: PWM and frequency variation is proposed. A fast response control loop can be used to keep the output voltage constant with PWM, while a “slower” control loop keeps the dc-link voltage VB under acceptable limits by varying the switching frequency. This allows overcoming the voltage stress in light load condition, which could exceed 500V when the converter is supplied by a 220 V utility line. However, this topology output characteristic makes necessary to increase the switching frequency with the reduction of load. Thus, when the ZVS is lost, the efficiency starts to decrease fast as a consequence of higher switching losses. But the ZVS range can be extended in order to achieve a flatter efficiency curve. The price is higher reactive power circulating, increasing conduction losses and so, reducing overall efficiency. So there is a trade-off between the ZVS range and overall efficiency which has to be taken into account when designing the converter.

Analysis and Design Equations In order to simplify the analysis, the PFC stage and the dc-dc converter are studied separately. This is made possible by the presence of the dc-link capacitor, which decouples both stages. The only common elements to both stages are the power switches which handle the sum of the currents of both stages. The presented analysis is performed for a duty cycle of D = 0.5, which closely represents the circuit operation at the maximum power.

The PFC Stage The PFC stage is shown in Fig. 2 (a). To perform its analysis input filter inductor Lf is disregarded. This is feasible because PFC is performed by the charge-pump converter and the filter inductor is only responsible for the input current ripple reduction, which has twice the switching frequency. Therefore, it does not influence the low frequency harmonics and does not significantly affect the PF when only the first 40 harmonics are considered.

(a) PFC circuit

(b) Dc-dc circuit

Fig. 2: Converter division into two stages for analysis.

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Operation Modes In the present analysis, the input voltage is considered to be in its positive half-cycle and the circuit is considered to be in steady-state operation with a constant switching frequency, fs. The switching frequency is high enough that input voltage Vi(t) can be considered constant during one switching period and the Capacitors Cf1 e Cf2 have the same capacitance values and are large enough that their voltages can be considered constant and equal to Vi(t)/2 during one switching period. Inductors Lin1 e Lin2 and capacitors CS1 e CS2 have the same values of inductance and capacitance, respectively. The dc-link voltage ripple is negligible because the dc-link capacitor, CB, has a large value. All components are assumed to be ideal. Mode 1 – (t0, t1): At the instant before t0, lower switch S2 is conducting the increasing current through Lin2. At t0, S2 is turned off. Cs1 then starts to discharge and Cs2 charges. Thus, the voltage across S1 decreases and across S2 increases. At t1, voltage VS1 is zero and VS2 is equal to the dc-link voltage VB. Mode 2 – (t1, t2): At t1, when voltage VS1 reaches zero, S1’s anti-parallel diode is turned on. The current through Lin2 decreases, charging the dc-link capacitor with CB. The current through Lin1 starts to increase due to the voltage imposed by Cf1. Mode 3 – (t2, t3): At t2, S1 is turned on, taking on all of the currents. At t3, the current through inductor Lin2 reaches zero. Mode 4 – (t3, t4): The input current flows through capacitor Cf2 and the current through inductor Lin1 continues to increase linearly. Mode 5 – (t4, t5): At t4, S1 is turned off under zero voltage. Due to the current imposed by inductor Lin1, Cs2 starts to discharge and Cs1 to charge and the opposite of mode one occurs. Mode 6 – (t5, t6): This mode is similar to mode 2, but now the body diode of S2 is turned on. Mode 7 – (t6, t7): At t6, S2 is turned on, taking on all of the currents. At t7, the current through inductor Lin1 reaches zero. Mode 8 – (t7, t8): At t7, when the current trough Lin1 reaches zero, D1 turns off. The input current flows through capacitor Cf1 and the current through inductor Lin2 continues to increase linearly. This mode ends when S2 is turned off. Fig. 3 (a) represents the PFC circuit main waveforms.

Design Equations To derive the design equations, the line input voltage is considered to be at its peak and the dead time is neglected. The methodology is based on the works presented in [4], [7] and [9]. The values of the charge-pump inductors and capacitors are obtained with (1) and (2), respectively. Lin =

Cf =

Vipk 2

(1)

16 ⋅ f s ⋅ Pin 4 ⋅ Pin π ⋅ f s ⋅ α 2 ⋅Vipk 2

(2)

2

Where 0 < α < 1 and represents the rate of the charge-pump natural frequency over the switching frequency:

α=

ω0 1 = ωs 2π ⋅ f s ⋅ Lin ⋅ C f

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The α parameter has direct influence over the dc-link voltage VB. The higher α is, higher is the dc-link voltage. However, an equation to express VB was not obtained, since the relation is nonlinear. Reference [10] shows that for the boost converter working in DCM, the ratio VB/Vi, has influence over the PF. The same happens to the studied topology. And since the dc-link voltage depends on α, the PF also depends on this parameter. Simulation results has shown that, for this topology, an α close to 1/3 results in close to unit power factor with none excessive dc-link voltage.

(a) - Theoretical waveforms of the PFC stage.

(b) - Theoretical waveforms of the DC-DC stage.

Fig. 3: Theoretical waveforms near the peak of line input voltage and for D = 0.5.

DC-DC Stage The dc-dc stage is shown in Fig. 2 (b). Since the HB-PWM-ZVS is a well known converter [11], the operation modes are not presented in this paper.

Design Equations The HB-ZVS-PWM output characteristic is presented in (4). q=

V '0 ⎡ 4 ⋅ I '0 ⋅ Lr ⋅ f s ⎤ = ⎢ 2 ⋅ D ⋅ (1 − D ) − ⎥ VB ⎣ VB ⎦

(4) Due to the presence of the resonant inductor there is a duty cycle loss, which is proportional to the output current, as shown in (5). I '0 =

4 ⋅ I '0 ⋅ Lr ⋅ f s VB

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Substituting (5) in (4) leads to (6). q = ⎡⎣ 2 ⋅ D ⋅ (1 − D ) − I '0 ⎤⎦

(6) The turns ratio can be written as shown in (7), where V'0 represents the output voltage referred to the primary side of the transformer [12]. nT =

V '0 VB = ⋅ ⎡ 2 ⋅ D ⋅ (1 − D ) − I '0 ⎤⎦ V0 V0 ⎣

(7)

The dc-link voltage VB is obtained by simulation.

Simulation and Experimental Results In order to validate the presented study simulation and experimental results for the converter shown in Fig. 1 operating with PWM control and variable switching frequency are presented. The specifications are presented in Table I. The converter component values obtained for the given specifications are shown in Table II. The chosen value for the α parameter was 0.35, in order to guarantee that the converter can deliver the rated power with reduced line input voltage, as low as 190 V. Simulation results has shown that for the chosen α, the dc-link voltage is approximately 360 V at the rated power for 220 V line input voltage and 390V at 240 V. However, if a reduction of the switching frequency is allowed in low input voltage situations, the α parameter can be reduced, therefore, reducing the dc-link voltage as well. Table I: Prototype Specifications. Parameter Line Input Voltage - Vi Output Voltage - V0 Output Rated Power – P0 Nominal Switching frequency – fs Standard

Value 220 Vef ± 10% / 60 Hz 24 Vdc ± 5 % 200 W 110 kHz IEC 61000-3-2 Class A

Table II: Component Values Parameter Component Value Lin1, Lin2 200 μH Cf1, Cf2 100 nF Lf 500 μH Lr 25 μH CB 100 μF Ce1, Ce2 220 nF L0 20 μH C0 4,700 μF The converter control was designed to keep the output voltage constant with PWM. Another control loop was designed to reduce the dc-link voltage by increasing the switching frequency when it reaches 460 V. The maximum switching frequency for this prototype is 180 kHz. Simulation results for the line input voltage and current at full load are presented in Fig. 4. As can be seen, power factor correction is achieved, since the input current presents a sinusoidal shape in phase with the input voltage. In Fig. 5 the harmonic content of the input current and the limits imposed by

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IEC 61000-3-2 Class A and D standard are depicted. The input current THD is about 13.3 % and the power factor obtained is 0.99.

Fig. 4: Input voltage and current at full load. As shown in Fig. 5, with the exception of the third harmonic, all other current harmonic components are so small they do not appear in the bar graph. Thus, the proposed converter easily complies with the IEC regulations. 2,5 2 1,5

Class A Class D Converter

1 0,5 0 2

3

4

5

6

7

8

9 10 11 12 13 14 15 16 17 18 19 20 21

Fig. 5 – Harmonic content of the input current in amperes. Fig. 6 presents experimental results for the line input voltage and current at 100 % and 25 % of the rated power, respectively. As can be seen, power factor correction is achieved in both situations. At 25 % of full load the input current is more distorted with a THD of 22 %, but the power factor is still high, 0.977. Fig. 7, shows the line input power quality analysis at both situations.

(b) – 51.3 W

(a) – 212.2 W

Fig. 6: Line input voltage and current at (a) - rated power and (b) – 25 % of rated power.

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(a) – 212.2 W

(b) – 51.3 W

Fig. 7: Input voltage and current at (a) - rated power and (b) – 25 % of rated power. The power factor and efficiency trend curves as functions of the output power are depicted in Fig. 8 (a). High power factor is achieved for the tested range, always above 97 %. The efficiency is high for the converter operating between 50 % and 100 % of the rated power, which is the power range where ZVS is achieved. When the output power goes under 50 %, the converter stars to work with hard switching during the zero cross of line input voltage. As the output power is reduced, the time interval in which the converter works with hard switching, increases, reducing the efficiency. Fig. 9 shows switch S1 current at approximately 75 W. It can be seen that soft switching is still achieved at the line peak and the ZVS is lost close to the zero crossing of the line input voltage. Fig. 8 (b) shows the dc-link voltage as a function of the output power for three different line input voltages. As mentioned earlier, the voltage increases with the reduction of load. This voltage becomes an issue when the output power is reduced under 25 % . With a maximum switching frequency of 180 kHz, it was not possible to keep the dc-link voltage under 500 V in light load condition when the line input voltage is around 240 V. Increasing the switching frequency above 180 kHz is not a solution, since the switching losses will be higher. One solution is to reduce the α parameter. But it does not entirely solve the problem, which will remain in lighter load. 1,00

500

0,95

460 VB (V)

0,90 0,85 0,80

Efficiency

0,75

Power Factor

420 220 V 240 V

380

198 V

0,70

340 50

100

150

200

Output Power (W)

50

100

150

200

Output Power (W)

(a) – Power factor and efficiency vs output power

(b) – Dc-link voltage vs output power

Fig. 8: Power factor, efficiency and dc-link voltage trend curves vs output power.

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Fig. 9: Detail of switch S1 current at the line input peak voltage and zero crossing @ 75 W (acquisition with peak detection mode).

CONCLUSION A single-stage SMPS with PFC was presented. As in [4], the presented converter is suitable for low power applications, under 600 W. Experimental results for a 200 W - 110 kHz prototype presented close to unity power factor, high efficiency, high power density and a small number of components, comparing to two stage approach. The obtained efficiency trend curve has shown that the presented converter is more suitable for applications with load variations from 50 % to 100 % of the rated power when powered by a 220 V utility line. Therefore it is more likely to use it in equipment with a dedicated load. Wide load range applications are possible, but efficiency is reduced at light load conditions and extra care is necessary to properly design the converter in order to avoid dc-link voltage stress, optimize the ZVS range.

REFERENCES [1] B. Mammano.: Improving Power Supply Efficiency – The Global Perspective, SEM1700 2006-2007 Power Supply Design Seminar, Texas Instruments inc., 2006-2007, pp. 1-1 through 1-9. [2] PSMA.: External Power Supply International Efficiency Marking Protocol Version 1.1, Revised July 2005 – www.psma.com. [3] PSMA.: Re: Position on voluntary and mandatory standards that will regulate the minimum acceptable efficiency of power supplies. Letter PSMA-BOD-2005-01 Rev. – www.psma.com. [4] C. S. Postiglione, A. J. Perin, C. B. Nascimento.: Single-Stage Power Factor Correction Switched Power Supply, IEEE IECON’06 32nd Annual Conference of the IEEE Industrial Electronics Society, pp. 24022407, November 2006. [5] A. Nabae, H. Nakano, S. Arai.: Novel Sinusoidal Converters with High Power Factor, IEEE Industry Applications Society Annual Meeting, Vol. 2, pp 775-780, 1994. [6] T.-F. Wu, J.-C. Hung, S.-Y. Tseng, Y.-M. Chen.: A Single-Stage Fast Regulator with PFC based on an Asymmetrical Half-Bridge Topology, IEEE Transactions on Industrial Electronics, Vol. 52, No.1, pp. 139150, February 2005. [7] J. F. Dums, C. B. Nascimento, A. J. Perin.: Single stage charge pump voltage-source electronic ballast for a 70W HPS lamp, SOBRAEP – Brazilian Power Electronics Society Journal, Vol. 12 no 1, pp 43 a 51, March 2007. [8] C. B. Nascimento.: Structures of Electronic Ballasts with High Power Factor (in portuguese), Ph.D. Thesis Federal University of Santa Catarina - UFSC, Institute of Power Electronics - INEP, 2005. [9] H.-L. Do, B.-H. Kwon.: Single-Stage Line-Coupled Half-Bridge Ballast with Unity Power Factor and Ripple-Free Input Current Using a Coupled Inductor, IEEE Transactions on Industrial Electronics, Vol. 50, NO. 6, pp 1259-1266, 2003. [10] K.-H. Liu, Y.-L. Lin.: Current Waveform Distortion in Power Factor Correction Circuits Employing Discontinuous-Mode Boost Converters, IEEE Power Electronics Specialists Conference, PESC’89, Vol. 2, pp. 825-829, 1989. [11] I. Barbi, F. P. Souza.: High Frequency soft-switched Isolated dc/dc Converters (in portuguese), Authors Ed. INEP – UFSC, 1999. [12] A. Alves.: Study, Project and Implementation of Rectifying Units for Telecommunications 48V/10A Using Microcontrolled Supervision Circuits (in Portuguese), Master Thesis, Federal University of Santa Catarina UFSC, Institute of Power Electronics - INEP, 2002.

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