A Test Generation Method Using a Compacted Test Table and a Test Generation Method Using a Compacted Test Plan Table for RTL Data Path Circuits Toshinori Hosokawa, Hiroshi Date, and Michiaki Muraoka Design Technology Development Department, Semiconductor Technology Academic Research Center (STARC) 5F Yusen Shin Yokohama Bldg, 3-17-2,Shin Yokohama, Kohoku-ku, Yokohama, 222-0033, Japan {hosokawa, date, muraoka}@starc.or.jp Abstract This paper proposes a test generation method using a compacted test table and a test generation method using a compacted test plan table for RTL data path circuits with DFT where hierarchical test generations are applicable. Moreover, a heuristic algorithm for a compacted test plan table generation is proposed. The proposed methods could shorten test lengths for some RTL data path circuits compared with the conventional hierarchical test generation method.

1. Introduction Design for testability (DFT) method is important for a reliable VLSI. Scan design methods [1,2] are one of the most popular DFT methods, so far. However, scan design methods have the following disadvantages. (1)Test circuits cause the degradation of performance and/or area due to DFT application at gate level after logic synthesis. (2)The test length is very long [3]. (3)To apply at-speed testing is difficult. In order to solve the above-mentioned disadvantages, DFT methods [4,5,6,7,8] for RTL design circuits before logic synthesis were proposed. RTL design circuits consist of a data path part and a controller part. The former is represented by hardware elements (e.g. registers, multiplexers, and operation modules) and wires, and the latter is represented by a finite state machine. A controller and a data path are connected with internal signals: control signals and status signals. Control signals are those that come from a controller, and status signals are those that come from a data path. The focus of this paper is on RTL data path circuits. In reference [6], a design for strong testability method for RTL data path circuits has been proposed. The method makes the inputs of a hardware element M in a data path controllable and makes the outputs of M in a data path observable using normal data path flow. Thus, a test pattern for M can be propagated to the inputs of M from primary inputs, and a

Proceedings of the 20 th IEEE VLSI Test Symposium (VTS’02) 1093-0167/02 $17.00 © 2002 IEEE

response from M can be propagated to primary outputs using normal data path flow by a design for strong testability method. It is said that a data path circuit is strongly testable [6] iff there exists a test plan for each hardware element M that makes it possible to apply any test pattern to M and to observe any response of M. In reference [6], as a hierarchical test generation is only applied to operation modules and multiplexers in a data path circuit, referred to as combinational modules, M is a combinational module. 100% fault efficiency is achieved for RTL data path circuits with strong testability as each M is a small combinational circuit and M is completely controllable and observable. In reference [6], testing is sequentially performed for a single combinational module in data path circuits with strong testability. The test length for data path circuits with strong testability is, then, given by n

L=

å (L ´ N ) , j

j

(1)

j =1

where L is the test length for data path circuits with strong testability, n is the number of combinational modules, Lj is the length of a test plan for a combinational module j (j=1,2,...,n), and Nj is the number of test patterns for a combinational module j. Equation (1) shows that the test length for data path circuits with strong testability becomes drastically longer as the number of combinational modules and the number of gates in a combinational module increase. In this paper, a test generation method using a compacted test table (CTT) and a test generation method using a compacted test plan table (CTPT) for data path circuits with strong testability are proposed to shorten the test length. This paper is organized as follows. In section 2, a test generation method using a CTT is proposed. In section 3, a test generation method using a CTPT is proposed. In section 4, experimental results by applying the proposed test generation methods to some RTL data path circuits are shown. Finally, section 5 concludes this paper.

2. Test Generation Method Using a CTT In this paper, control signals and status signals of RTL data path circuits are treated as primary inputs and outputs, respectively. When a primary input needs to be distinguished, control signals are referred to as control primary inputs and other primary inputs are referred to as data primary inputs.

2.1 Preliminaries (Definition 1: Test plan) A test plan for a combinational module M is the test sequence at primary input that propagates a test pattern to M from primary inputs and propagates the response to primary outputs. The value of a data primary input is b Î {0,1} or X (don’t care) and the value of a control primary input is b, X, 0, or 1. b is the value of a primary input which constitutes a test pattern to detect a fault in M[9]. Example 1: Table 1 shows a test plan T1 for a combinational module 1 (Table 1 (a)) and a test plan T2 for a combinational module 2 (Table 1 (b)) in a data path circuit with a data primary input P0 and control primary inputs P1, P2, P3, and P4.

P0 X b X

(a) T1 P1 P2 b 0 0 1 X X

P3 1 X X

P4 X 1 X

Time 0 1 2

P0 X b X

(b) T2 P1 P2 0 X X X X X

P3 X b 0

P4 X 0 X

Table 2 Operation ∩f ∩f b X 0 1 T1 Time P0 P1 P2 P3 P4 0 X b 0 1 X 1 b 0 1 X 1 2

X X X X X

b φ b φ φ

X b X 0 1

0 φ 0 0 φ

1 φ 1 φ 1

Skew 1 T2 ∩f

Time P0 P1 P2 P3 P4 0 X 0 X X X 1 2

b X X X X X

b 0

0 X

(C1) k ≥ l1 (C2) T1(t,i)∩f T2(t-k,i) ≠ φ for any t, i, such that k ≤ t < min(l1, k+l2), and 0≤ i < w. The compaction operation ∩f is defined as shown in Table 2. Let T be the resultant test plan when T2 is compacted for T1 with skew k. T can be represented by the following equations using the compaction operation ∩f for any i such that 0 ≤ i < w. T(t,i)=T1(t,i) T(t,i)=T1(t,i)∩fT2(t-k,i) T(t,i)=X T(t,i)=T2(t-k,i)

for 0≤t

1. Introduction Design for testability (DFT) method is important for a reliable VLSI. Scan design methods [1,2] are one of the most popular DFT methods, so far. However, scan design methods have the following disadvantages. (1)Test circuits cause the degradation of performance and/or area due to DFT application at gate level after logic synthesis. (2)The test length is very long [3]. (3)To apply at-speed testing is difficult. In order to solve the above-mentioned disadvantages, DFT methods [4,5,6,7,8] for RTL design circuits before logic synthesis were proposed. RTL design circuits consist of a data path part and a controller part. The former is represented by hardware elements (e.g. registers, multiplexers, and operation modules) and wires, and the latter is represented by a finite state machine. A controller and a data path are connected with internal signals: control signals and status signals. Control signals are those that come from a controller, and status signals are those that come from a data path. The focus of this paper is on RTL data path circuits. In reference [6], a design for strong testability method for RTL data path circuits has been proposed. The method makes the inputs of a hardware element M in a data path controllable and makes the outputs of M in a data path observable using normal data path flow. Thus, a test pattern for M can be propagated to the inputs of M from primary inputs, and a

Proceedings of the 20 th IEEE VLSI Test Symposium (VTS’02) 1093-0167/02 $17.00 © 2002 IEEE

response from M can be propagated to primary outputs using normal data path flow by a design for strong testability method. It is said that a data path circuit is strongly testable [6] iff there exists a test plan for each hardware element M that makes it possible to apply any test pattern to M and to observe any response of M. In reference [6], as a hierarchical test generation is only applied to operation modules and multiplexers in a data path circuit, referred to as combinational modules, M is a combinational module. 100% fault efficiency is achieved for RTL data path circuits with strong testability as each M is a small combinational circuit and M is completely controllable and observable. In reference [6], testing is sequentially performed for a single combinational module in data path circuits with strong testability. The test length for data path circuits with strong testability is, then, given by n

L=

å (L ´ N ) , j

j

(1)

j =1

where L is the test length for data path circuits with strong testability, n is the number of combinational modules, Lj is the length of a test plan for a combinational module j (j=1,2,...,n), and Nj is the number of test patterns for a combinational module j. Equation (1) shows that the test length for data path circuits with strong testability becomes drastically longer as the number of combinational modules and the number of gates in a combinational module increase. In this paper, a test generation method using a compacted test table (CTT) and a test generation method using a compacted test plan table (CTPT) for data path circuits with strong testability are proposed to shorten the test length. This paper is organized as follows. In section 2, a test generation method using a CTT is proposed. In section 3, a test generation method using a CTPT is proposed. In section 4, experimental results by applying the proposed test generation methods to some RTL data path circuits are shown. Finally, section 5 concludes this paper.

2. Test Generation Method Using a CTT In this paper, control signals and status signals of RTL data path circuits are treated as primary inputs and outputs, respectively. When a primary input needs to be distinguished, control signals are referred to as control primary inputs and other primary inputs are referred to as data primary inputs.

2.1 Preliminaries (Definition 1: Test plan) A test plan for a combinational module M is the test sequence at primary input that propagates a test pattern to M from primary inputs and propagates the response to primary outputs. The value of a data primary input is b Î {0,1} or X (don’t care) and the value of a control primary input is b, X, 0, or 1. b is the value of a primary input which constitutes a test pattern to detect a fault in M[9]. Example 1: Table 1 shows a test plan T1 for a combinational module 1 (Table 1 (a)) and a test plan T2 for a combinational module 2 (Table 1 (b)) in a data path circuit with a data primary input P0 and control primary inputs P1, P2, P3, and P4.

P0 X b X

(a) T1 P1 P2 b 0 0 1 X X

P3 1 X X

P4 X 1 X

Time 0 1 2

P0 X b X

(b) T2 P1 P2 0 X X X X X

P3 X b 0

P4 X 0 X

Table 2 Operation ∩f ∩f b X 0 1 T1 Time P0 P1 P2 P3 P4 0 X b 0 1 X 1 b 0 1 X 1 2

X X X X X

b φ b φ φ

X b X 0 1

0 φ 0 0 φ

1 φ 1 φ 1

Skew 1 T2 ∩f

Time P0 P1 P2 P3 P4 0 X 0 X X X 1 2

b X X X X X

b 0

0 X

(C1) k ≥ l1 (C2) T1(t,i)∩f T2(t-k,i) ≠ φ for any t, i, such that k ≤ t < min(l1, k+l2), and 0≤ i < w. The compaction operation ∩f is defined as shown in Table 2. Let T be the resultant test plan when T2 is compacted for T1 with skew k. T can be represented by the following equations using the compaction operation ∩f for any i such that 0 ≤ i < w. T(t,i)=T1(t,i) T(t,i)=T1(t,i)∩fT2(t-k,i) T(t,i)=X T(t,i)=T2(t-k,i)

for 0≤t