A three-phase line-interactive UPS system ... - IEEE Xplore

IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS, VOL. 38, NO. 6, NOVEMBER/DECEMBER 2002

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A Three-Phase Line-Interactive UPS System Implementation With Series-Parallel Active Power-Line Conditioning Capabilities Sérgio Augusto Oliveira da Silva, Pedro Francisco Donoso-Garcia, Porfirio Cabaleiro Cortizo, and Paulo Fernando Seixas

Abstract—This paper presents a three-phase line-interactive uninterruptible power supply (UPS) system with series-parallel active power-line conditioning capabilities, using a synchronous-reference-frame (SRF)-based controller, which allows an effective power-factor correction, load harmonic current suppression, and output voltage regulation. The three-phase UPS system is composed of two active power filter topologies. The first one is a series active power filter, which works as a sinusoidal current source in phase with the input voltage. The other is a parallel active power filter, which works as a sinusoidal voltage source in phase with the input voltage, providing to the load a regulated and sinusoidal voltage with low total harmonic distortion. Operation of a three-phase phase-locked loop structure, used in the proposed line-interactive UPS implementation, is presented and experimentally verified under distorted utility conditions. The control algorithm using the SRF method and the active power flow through the UPS system are described and analytically studied. Design procedures, digital simulations, and experimental results for a prototype are presented to verify the good performance of the proposed three-phase line-interactive UPS system. Index Terms—Active power-line conditioning, harmonic compensation, series-parallel active filter, synchronous reference frame (SRF).

I. INTRODUCTION

T

O IMPROVE the power source quality, uninterruptible power supply (UPS) systems have been employed, which provide clean and uninterruptible power to critical loads such as computers, medical equipment, etc., against power supply disturbances [1]–[7]. In [6] and [7], three-phase parallel processing UPSs have been presented with harmonic and reactive power compensation, but the output voltages and the input currents cannot be controlled simultaneously. Three-phase UPS systems with series-parallel active power-line conditioning have been proposed using different control strategies [1]–[3]. In [3], the Paper IPCSD 02–045, presented at the 2001 Industry Applications Society Annual Meeting, Chicago, IL, September 30–October 5, and approved for publication in the IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS by the Industrial Power Converter Committee of the IEEE Industry Applications Society. Manuscript submitted for review November 1, 2001 and released for publication July 20, 2002. S. A. O. da Silva is with the Department of Electrical Engineering, Federal Center of Technological Education, 86300-000 Cornélio Procópio, Brazil (e-mail: [email protected]). P. F. Donoso-Garcia, P. C. Cortizo, and P. F. Seixas are with the Electrical Engineering R&D Center, Federal University of Minas Gerais, 31270-901 Belo Horizonte, Brazil (e-mail: [email protected]; [email protected]; [email protected]). Digital Object Identifier 10.1109/TIA.2002.804760

three-phase UPS system was employed for three-wire systems, and in [1] and [2] it was employed for three-wire and four-wire systems. In these papers, two different approaches to control three-phase UPS systems using synchronous-reference-frame (SRF)-based controllers were proposed, but only simulations results were presented. This paper presents experimental results for a three-phase line-interactive UPS system with series-parallel active power-line conditioning using an SRF-based controller, for three-phase, three-wire, and four-wire systems. The series active power filter acts as a sinusoidal current source and the parallel active power filter acts as a sinusoidal voltage source [2]. In this line-interactive UPS system, an effective power-factor correction is carried out. The output voltages are controlled to have constant rms values and low total harmonic distortion (THD) and the source currents are controlled to be balanced and sinusoidal quantities with low THD, also. Operation of a three-phase phase-locked loop (PLL) structure, used in the line-interactive UPS implementation, is presented and experimentally tested under distorted utility conditions. A PLL model is shown and design procedures to achieve the proportional–integral (PI) controller gains are presented. The control algorithm using the SRF method and the active power flow through the UPS system are described and analytically studied. Design procedures, digital simulations, and experimental results for a prototype are presented in order to verify the good performance of the proposed three-phase line-interactive UPS system. II. OPERATION OF THE LINE-INTERACTIVE UPS TOPOLOGY The topology of the line-interactive UPS system is shown in Fig. 1. Two pulsewidth modulation (PWM) converters, coupled to a common dc bus, are used to perform the series active filter and the parallel active filter functions. Battery bank and dc capacitors are placed in the dc bus and a static switch “sw” is used to provide the disconnection between the UPS system and the power supply when an occasional interruption of the incoming power occurs. A control algorithm using SRF-based controllers is used to control the series active filter making the line currents ( , , and ) sinusoidal and balanced. The parallel active filter acts as a sinusoidal voltage source, such that balanced and sinusoidal voltages are provided to load. The output UPS voltages ( , , and ) are controlled to be in phase with respect to the

0093-9994/02$17.00 © 2002 IEEE

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Fig. 1. Line-interactive UPS system topology.

Fig. 2. Block diagram of the current SRF-based controller.

input voltages ( , , and ), respectively. Both the parallel and the series filter use three independent controllers acting on half-bridge inverters. III. SRF AND STATE FEEDBACK CONTROLLERS A. Current SRF Controller (Standby Mode) The block diagram of the control scheme for current compensation is shown in Fig. 2. The control algorithm should be developed to provide, by software, the compensating reference currents ( , , and ) for the series active filter. The three-phase , and ) are measured and uncompensated currents ( , transformed into two-phase stationary reference frame quantities ( , ). Then, such quantities are transformed from into a two-phase the two-phase stationary reference frame , based on the transsynchronous rotating reference frame is the angular position of the formation (1), where reference frame. The inverse transformation matrix from twophase SRF to two-phase stationary reference frame is given by

(2). The components of the unit vector and are obtained from a PLL system that will be discussed in Section IV. are now dc The currents at the fundamental frequency values and all the harmonics are transformed into non-dc quantities and can be filtered using a low-pass filter (LPF) shown in and represent the fundamental active and Fig. 2. Now, reactive components of the load currents, respectively. In this line-interactive UPS implementation the reactive power must is made equal to zero in the be compensated, too, and then, SRF controller of Fig. 2. The series filter reference currents in the stationary reference frame are then given by (3) (1) (2) (3)

DA SILVA et al.: THREE-PHASE LINE-INTERACTIVE UPS SYSTEM IMPLEMENTATION

Fig. 3.

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Single-phase current controller of the series active filter.

Thereby, the dc components of the SRF are transformed into and yield all fundamental the stationary reference frame components of the input uncompensated ac currents. The matrices that provide the linear transformation from three-phase system to two-phase stationary reference frame system and from two-phase system to three-phase stationary reference frame system are given by (4) and (5), respectively. An additional dc-bus controller is responsible for regulating the current and the voltage . Apart from the conventional active power filter applications, in which only the dc-bus voltage is controlled, the UPS dc-bus controller must be able to control the dc-bus current, too. The dc-bus controller is responsible for the control of the power flow through the UPS system. Its and, thus, output is added to the active current in the axis the amplitude of the input currents is controlled as shown in Fig. 2

Fig. 4. Frequency response of the series active filter i (s)=i (s). (a) Amplitude response. (b) Phase response.

(4)

(5)

B. State Feedback Current Controller (Standby Mode) The single-phase block diagram of the current controller is , ) are meashown in Fig. 3. The load currents ( , sured and from the current SRF controller the sinusoidal current references ( , , and ) are obtained. From Fig. 3, the is found as (6) and the closed-loop transfer function output dynamic stiffness is given by (7), which shows the efand input fect of the difference between the output voltage . The differvoltage on the compensated input current ence between the input and output voltages is considered as a disturbance (6) (7) The frequency response of (6) is shown in Fig. 4(a) and (b). rad/s , the gain of the At the power system frequency system transfer function is about 0 dB and the phase shift is approximately 0 . The bandwidth of the system is about 1600 Hz. Fig. 5 shows the dynamic stiffness of the system. It is noticed that the series active filter has high impedance obtained from (7)

j

Fig. 5. Dynamic stiffness of the current controller (v (s) amplitude response.

0 v (s))=i (s)j:

in a large range of the frequency spectrum, which is enough to isolate the line from the load with respect to current harmonics. C. State Feedback Voltage Controller (Standby and Backup Mode) The parallel active filter is responsible for the control of the output voltages. Thus, the output voltages must have constant rms values with low THD and will be controlled to be in phase with the input voltages. Similar to the control algorithm for input , and ) current compensation, the reference voltages ( , are generated by software using a PLL system. The single-phase block diagram of the voltage controller is shown in Fig. 6, in which a classical PI controller with inner current loop and outer voltage loop is used. is From Fig. 6, the closed-loop transfer function found as (8) and the output dynamic stiffness is given by (9), which shows the effect of the difference between the load curand the compensated input current on the regulated rent output voltage . The difference between the load current

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Fig. 6. Single-phase voltage controller of the parallel active filter.

Fig. 7. Frequency response of the parallel active filter v (s)=v (s). (a) Amplitude response. (b) Phase response.

and the compensated input current bance

j

Fig. 8. Dynamic stiffness of the voltage controller (i (s) amplitude response.

0 i (s))=v

j

(s) :

is considered as a distur-

(8) (9)

Fig. 9.

Three-phase PLL control diagram.

IV. THREE-PHASE PLL SYSTEM

(10) The frequency response of (8) is shown in Fig. 7(a) and (b). rad/s , the gain of At the power system frequency the system transfer function is about 0 dB and the phase shift is approximately 0 . The bandwidth of the system is about 6000 Hz. Fig. 8 shows the dynamic stiffness of the system. A high admittance from (9) is noticed in a large range of the frequency spectrum, which is enough to absorb the harmonic currents of the load.

The three-phase PLL structure implemented in this paper is shown in Fig. 9. It is entirely implemented in software. The input signals of the PLL system are the sampled voltages , , and . The principle of operation of the presented of the instantaPLL structure is to annul the dc component neous power (Fig. 9). The dynamic of the PLL system will set the output of the PI controller to the angular frequency reference , where is the utility frequency. The angle is obtained by an integration of the frequency that will be identical to the utility frequency . reference is used to calculate the feedback signals Thus, the angle and that will be orthogonal to the sampled voltages and


Fig. 10.

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Control model of the three-phase PLL. TABLE I PARAMETERS AND CONTROLLER GAINS

Fig. 12. PLL frequency ! .

Fig. 13. Input sampled voltage v

Fig. 11.

and PLL voltage v

.

PLL instantaneous power p .

, respectively, in such a way that the dc component of annulled.

is

A. Control Model of the Three-Phase PLL System The instantaneous input power of the power system is found as

(a)

(11) Assuming that the sum of the input currents is equal to zero, (11) can be found as

,

, and (12)

where (b)

(13)

Fig. 14.

Power flow of the UPS system. (a) V

>V

. (b) V

>V

.

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(a)

(a)

(b) Fig. 15. Normalized powers. (a) Parallel converter converter jS =S j.

j

S =S

(b) j

. (b) Series

Moreover, from Fig. 9, the PLL instantaneous power is , , , and are given by (14), where the quantities given by (15) (14)

(15) To annul the dc component of , the PLL system will set the output of the integrating element as

=

Fig. 16. Normalized powers for k 0 and k = 0:1(cos Parallel converter jS =S j. (b) Series converter jS =S j.

= 1). (a)

In addition, the PLL control diagram shown in Fig. 9 can be replaced by the simplified PLL model shown in Fig. 10. For , the term behaves linearly [8], that small values of . is, is found as (19), The open-loop transfer function which accounts for the sampling time that introduces a lag in the forward path of the PLL model. Since it contains a double integration, a standard design procedure called “symmetrical optimum” method is used to determine the PI controller gains [9]. This method consists of choosing the crossover frequency at . the geometric mean of the two corner frequencies of should be symThe magnitude and the phase plot of metrical with respect to the crossover frequency

(16) The error between the utility angle and the PLL angle is given by (17). Then, substituting the (15)–(17) in (14), the power can be found as (18). As constant varies either when input voltages or input currents change, it is assumed in the PLL model to be equal to one (17) (18)

(19) Thus, using the symmetrical optimum method discussed above and from (19), (20) and (21) are found, where is a normalizing factor. Thus, from (19)–(21), the proportional gain can be selected by (22) (20)


Fig. 17.

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Complete scheme of the line-interactive series-parallel UPS system.

(21)

PLL instantaneous power and PLL frequency , respecand the clean tively. In Fig. 13, the distorted input voltage are shown. PLL voltage

(22) V. ACTIVE POWER FLOW OF THE THREE-PHASE UPS SYSTEM The closed-loop transfer function its poles are found by (24)

is given by (23) and

(23)

(24) Hence, the relationship between damping ratio factor is

and the

(25) Thereby, with an adequate choice of the damping ratio and from (20), (22), and (25), it is possible to select the appropriate PI controller gains. Table I shows the parameters and the controller gains used in the PLL simulation and experimentation. In Figs. 11 and 12, the experimental results and the model simulation results of the three-phase PLL system are shown. Figs. 11 and 12 show the

The active power flow of the UPS system is shown in Fig. 14. The direction of the power flow can ever change because the amplitude of the input voltages is variable. and , handled by the series Both the apparent powers and by the parallel converters, respectively, depend of the , the ratio between the output and input rms voltages and the THD of the load current displacement factor . In steady state, assuming a balanced sinusoidal system, the normalized powers handled by the parallel conand by the series converter are given verter , , and by (26) and (27), respectively. The quantities , are the apparent, active, reactive, and harmonic powers of the load, respectively. In Fig. 15(a) and (b), the normalized powers handled by the and by the series converter parallel converter are plotted for two different displacement factors. These curves can be used to determine the power rate of the PWM converters

(26)

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(a)

(b)

(c)

(d)

Fig. 18. Experimental results. (a) Output voltages v current i .

. (b) Input currents i

(27) If the charging of the batteries is taking into account, additional active power , given by (28), must be included in the analysis. Thus, (29) and (30) replace (26) and (27), respectively, where the charging factor (28)

(29)

(30)

of

The plots of the normalized powers for two different values are shown in Fig. 16(a) and (b). Depending on the value

. (c) Input voltage v

and input current i . (d) Output voltage v

and input

and the input voltage deviation from the desired output voltage, the batteries charging can be realized either from the series or parallel PWM converters, or from both. VI. EXPERIMENTAL RESULTS The complete scheme of the three-phase line-interactive UPS system is shown in Fig. 17. To verify the performance of the UPS system, a prototype was developed and tested. A 2.5-kVA used to test the UPS system is a nonlinear load three-phase diode rectifier. The parameters used in the prototype H, mH, F, are: (dc load), F, nominal rms line-to-neutral output V, and dc bus voltage— V. voltages The part of the scheme shown in the shaded area uses a 400-MHz PC computer, a 12-b-resolution data acquisition system, and a 12-b-resolution D/A converter board. Both current SRF controller (Fig. 6) and PLL scheme (Fig. 2) are implemented in software and are responsible for generating the current and voltage references for the current and voltage analog controls. Both data acquisition systems and digital controllers run at 5-kHz frequency. and source currents are The output voltages shown in Fig. 18(a) and (b), respectively. The source currents are almost sinusoidal and balanced and the currents THDs


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(e)

(f)

(g)

(h)

(i) Fig. 18. (Continued.) Experimental results. (e) Boost action—input and output voltages. (f) Buck action—input and output voltages. (g) Currents i , i . (h) Standby–backup transition mode. (i) Backup–standby transition mode.

, and

i

are approximately 4%. The output voltages are almost sinusoidal with constant rms values and the voltages THDs are approximately 3%. and the input Fig. 18(c) shows the phase “ ” input current . The measured power factor (PF) is equal to 0.99. voltage and Fig. 18(d) shows the phase “ ” compensated current , respectively. The quantities and the output voltage are controlled to be in phase with respect to . The

UPS stabilization capability of the output voltages is shown in Fig. 18(e) and (f). In Fig. 18(g) are shown phase “ ” uncompensated current , parallel compensation current , and compensated source current . The presence of a small fundamental current refers to the charging of the battery bank. component in , , and Fig. 18(h) and (i) shows the quantities (reference input current), for the transition from standby to

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backup mode (0.02 s) and from backup to standby mode (0.31 s). VII. CONCLUSIONS A three-phase line-interactive UPS system topology with active series-parallel power-line conditioning capabilities has been implemented and tested. Sinusoidal and regulated output voltages, sinusoidal input currents, and high input power factor were obtained. A model of a PLL system was presented and both PLL system and the algorithm of the SRF-based controller were implemented in software without the use of any hardware filters. The main advantage of the presented line-interactive UPS topology, as compared to the online topology, which uses two cascaded PWM power converters working at full power rating, is the smaller power rating handled by both series and parallel converters during the standby mode, increasing the efficiency of the UPS. Depending on the VA load rating, the presented line interactive UPS system can be an attractive and practical solution. It has been demonstrated that the experimentally obtained results have a good approximation with the theoretically predicted results. REFERENCES [1] S. A. O. da Silva, P. F. Donoso-Garcia, and P. C. Cortizo, “A three-phase series-parallel compensated line-interactive UPS system with sinusoidal input current and sinusoidal output voltage,” in Conf. Rec. IEEE-IAS Annu. Meeting, vol. 2, 1999, pp. 826–832. [2] S. A. O. da Silva, P. F. Donoso-Garcia, P. C. Cortizo, and P. F. Seixas, “A comparative analysis of control algorithms for three-phase line-interactive UPS systems with series-parallel active power-line conditioning using SRF method,” in Proc. IEEE PESC, 2000, CD-ROM. [3] F. Kamran and T. Habetler, “A novel on-line UPS with universal filtering capabilities,” in Proc. IEEE PESC’95, 1995, pp. 500–506. [4] S. J. Jeon and G. H. Cho, “A series-parallel compensated uninterruptible power supply with sinusoidal input current and sinusoidal output voltage,” in Proc. IEEE PESC’97, 1997, pp. 297–303. [5] R. Cheung, L. Cheng, P. Yu, and R. Sotudeh, “New line-interactive UPS system with DSP-based active power-line conditioning,” in Proc. IEEE PESC’96, vol. 2, 1996, pp. 981–985. [6] G. Joos, Y. Lin, P. D. Ziogas, and J. F. Lindsay, “An on-line UPS with improved input-output characteristics,” in Proc. IEEE APEC’92, 1992, pp. 598–605. [7] Y. Lin, G. Joos, and J. F. Lindsay, “Performance analysis of parallel—Processing UPS systems,” in Proc. IEEE APEC’93, 1993, pp. 533–539. [8] V. Kaura and V. Blasko, “Operation of a phase locked loop system under distorted utility conditions,” IEEE Trans. Ind. Applicat., vol. 33, pp. 58–63, Jan./Feb. 1997. [9] W. Leonard, Control of Electrical Drives. Berlin, Germany: SpringerVerlag, 1985, pp. 67–76.

Sérgio Augusto Oliveira da Silva received the B.S. and M.S. degrees in electrical engineering from the Federal University of Santa Catarina, Florianópolis, Brazil, in 1987 and 1989, respectively, and the Ph.D. degree from the Federal University of Minas Gerais, Belo Horizonte, Brazil, in 2001. From 1990 to 1992, he was with Spectro—Engineering and Electronic Systems Inc., Brazil, working on projects development, including switching power converters and UPS inverters. Since 1993, he has been a member of the Federal Center of Technological Education (CEFET-PR), Cornélio Procópio, Brazil. where he currently is a Professor of Electrical Engineering. His present research involves power electronic inverters, UPS systems, active filters, and control systems.

Pedro Francisco Donoso-Garcia (S’88-M’92) received the B.S. degree in electronic engineering from the Federal University of Rio Grande do Sul, Porto Alegre, Brazil, in 1981, the M.S. degree in electrical and electronics engineering from the Federal University of Minas Gerais, Belo Horizonte, Brazil, in 1986, and the Ph.D. degree in electrical and electronics engineering from the Federal University of Santa Catarina, Florianópolis, Brazil, in 1991. He currently is an Associate Professor in the Department of Electronic Engineering, Federal University of Minas Gerais. His research interests include high-frequency and highefficiency switching power converters UPS systems, power active filters, and audio amplifiers.

Porfírio Cabaleiro Cortizo was born in Belo Horizonte, Brazil, in 1955. He received the B.S. degree in electrical engineering from the Federal University of Minas Gerais, Belo Horizonte, Brazil, in 1978, and the Dr.Ing. degree from the Institut Polytechnique de Toulouse, Toulouse, France, in 1984. Since 1978, he has been a member of the Electronic Engineering Department, Federal University of Minas Gerais, where he currently is a Professor of Electrical Engineering. His research interests include high-frequency and high-efficiency switching power converters UPS systems, active filters, and control systems.

Paulo Fernando Seixas was born in Belo Horizonte, Brazil, in 1957. He received the B.S. and M.S. degrees in electrical engineering from the Federal University of Minas Gerais, Belo Horizonte, Brazil, in 1980 and 1983, respectively, and the Ph.D. degree from the Institut Polytechnique de Toulouse, Toulouse, France, in 1988. He has been a member of the Electrical Engineering Department, Federal University of Minas Gerais, since 1980, where he currently is a Professor of Electrical Engineering. His research interests are in the fields of electrical machines and drives, power electronics, and digital signal processing.