Phone: +41-1-632-6973 Fax: +41- 1-632-1 212. Abstruct-This paper ... gating SI and S3 alternatively, while S2 is always ON and. S4 is always OFF in the main ...
A Transformer Assisted Zero Voltage Switching Scheme for the Neutral-Point-Clamped (NPC) Inverter Xiaoming Yuan
Ivo Barbi
Power Electronics and Electrometrology Laboratory Swiss Federal Institute of Technology Zurich ETH-Zentrum / ETL, CH-8092 Zurich Switzerland Phone: +41-1-632-6973 Fax: +41- 1-632-1212
Power Electronics Institute Federal University of Santa Catarina P. 0. Box: 51 19,88040-970, Florianopolis-SC Brazil Phone: +55-48-331-9204 Fax: +55-48-234-5422
when possible mismatch between the DC link storage capacitors are taken into account [12]. Protection of the auxiliary devices from voltage spikes during their reverse recoveries constitutes the other difficulty of the circuit. Moreover, the auxiliary devices in the circuit are subject to 1.5 times of the main devices blocking voltage, raising significantly the cost for the auxiliary circuit.
Abstruct-This paper proposes a transformer assisted PWM zero voltage switching Neutral-Point-Clamped (NPC) inverter. With the assistance of a transformer assisted small rating lossless auxiliary circuit, the main switches work with zero voltage switching without suffering from any voltage/current spikes, under simple explicit control. The technique allows for higher operating frequency and better device utilization of the NPC inverter. Operation, analysis, designing as well as testing results from a 7kW prototype are presented in details.
I. INTRODUCTION Neutral-Point-Clamped (NPC) inverter [ 13 has been playing an growing role in the recent decade in drive [2] [4] and power system applications [3], due to the expanded capacity with the existing devices without the problematic series association, as well as the reduced output harmonics. To limit the dv/dt and di/dt rates of change when GTO is used, different snubber schemes utilizing either RCD snubbers [4] or low-loss snubbers [5] [6] have been developed, where the switching frequency is limited to a few hundreds Hz due to the significant snubber loss. Regenerative snubbers avoid the loss at the expense of the considerable hardware complexity [7], which includes even baby snubbers €or the recovery choppers [SI. Moreover, snubbers either dissipative or regenerative, suffer from such other problems as voltagdcurrent spikes, series inductor loss, as well as the adverse effects from the snubbing diodes etc.. Several previous publications have resorted to soft switching techniques for snubbing of NPC inverter. Besides the early thyristor three-state inverter [9] which works actually with zero current switching, zero voltage switching realized with resonant DC link and AuxiliaryResonant-Commutated-Pole-Inverter (ARCPI) have also been investigated [ 101 [ 111. In particular, the ARCPI NPC inverter [ l l ] , as shown in Fig. 1, is deemed a more promising scheme for high power applications due to the small power auxiliary circuit and full PWM operation capability. However, the scheme requires complicated current monitoring and controlling to ensure zero voltage switching, especially
0-7803-5160-6/99/$10.00 0 1999 IEEE.
I , T Fig. 1. Configuration of the ARCPI NPC inverter proposed in [I I].
T
I
Fig. 2. Configuration of the proposed transfonner assisted PWM zero voltage switching pole NPC inverter.
1259
As shown in Fig. 2, this paper proposes an alternative zero voltage switching scheme for the NPC inverter. By setting the transformer ratio k (k=N2/N I ,=NdN 12) to less than 1/4 according to the potential resonant loop losses, the proposal requires no additional monitoring or controlling circuit for ensuring zero voltage operation. Moreover, as the auxiliary devices are now all clamped to the rails by the NPC configuration, overvoltage protecting circuit is no longer necessary. Besides, all the auxiliary devices now block the same voltage as the main devices, rendering the circuit more practically interesting. Operation, analysis, designing and testing of the circuit will be presented in this paper.
commutations of SL and S4 respectively in the second zero voltage switching pole. As operation of one pole is identical to the other, only the operation of the first pole will be described. Assume that for each snubbing capacitance, a zero voltage detecting circuit is installed across it for releasing the gating signal of its corresponding main device (CrI-Sl; Cr2-S2; Cr3-S3; Cr4-S4)[131. Assume further that the transformer ratio k is set less than 1/4 that ensures the pole voltage swinging to the rail level during the commutation resonance with the presence of commutation loop losses [13]. Referring to Fig. 4 for the commutation step diagrams and Fig. 5 for the predicted commutation waveformes, the commutations between SI(Dl) and S3 during a switching cycle under negative load current will proceed in the steps described as following.
11. CIRCUIT OPERATION Neglecting the affects from the second order circuit parasitics as stray inductances and capacitances etc., the whole circuit can be decoupled into two independent zero voltage switching poles, as shown in Fig. 3(a)(b). The DC link neutral potential is assumed stable and is not addressed further for the sole purpose of this paper. For the first pole, as shown in Fig. 3(a), the output can be switched between the plus rail and the zero rail by gating S I and S3 alternatively, while S2 is always ON and S4 is always OFF in the main circuit, Sa4 is always ON and Sd is always OFF in the auxiliary circuit. As a result, for the main circuit, DcIserves as the freewheeling path of the down-arm, and S3 in series with Dc2 serves as the forward path of the down-arm. In the meanwhile, Cr2sees always zero voltage whereas Cr3 serves as the snubbing capacitance for the down-arm. Moreover, for the auxiliary circuit, DaClserves as the freewheeling path of the downarm, and Sal in series with Dac2serves as the forward path of the down-arm, For second pole, as shown in Fig. 3(b), the output can be switched between the zero rail and the minus rail by gating S2 and S4 alternatively, while S3 is always ON and SI is always OFF in the main circuit, and Sal is always ON and Sa3 is always OFF in the auxiliary circuit. Similar to the first pole, in the main circuit, Dc2forms the freewheeling path of the up-arm and S2 in series with DcI forms the forward path of the up-arm. Cr3 sees always zero voltage whereas Cr2 serves as the snubbing capacitance for the up-arm. Also, in the auxiliary circuit, Dac2 forms the freewheeling path and Sa4 in series with Daclforms the forward path of the up-arm. Evidently, both of the decoupled circuits work as a transformer assisted PWM zero voltage switching pole inverter [13]. In Fig. 3(a), auxiliary switches Sal and Sa3 assist the commutations of S I and S3 respectively in the first zero voltage switching pole. On the other hand, in Fig. 3(b), auxiliary switches Sa2 and Sa4 assist the
(a) First zero voltage switching pole of the transformer assisted PWM zero voltage switching NPC inverter. SZis always ON, S4 is always OFF in the main circuit. Sad is always ON, Sa*is always OFF in the auxiliary circuit.
n
(c) Second zero voltage switching pole of the transformer assisted PWM zero voltage switching NPC inverter. S, is always ON and S I is always OFF in the main circuit. S,, is always ON and Sa3 is always OFF in the auxiliary circuit. Fig. 3. Decoupling of the transformer assisted PWM zero voltage switching pole NPC inverter into two independent poles.
1260
Step 1 (to-tl):Circuit steady state. Freewheeling diodes D2 and DI carry the load current. Circuit output is connected to the plus rail. Step 2 (tl-t2): Turn off S I and turn on Sa, simultaneously at tl, leading to conduction of the auxiliary diode DI2.A voltage source valued at kVd, is induced on N2. Currents in D1and D2 start decreasing. Step 3 (t2-t3): D1 and D2 becomes blocking at t2. CrI is
Step I : b-tl (step 9: ts-b)
Step 7: t&
then charged and Cr3is discharged. Step 4 (t3-t4):CrI voltage rises to v d & at t3. Currents transfer from C,, and Cr3to DCIinstantly. S3 gating signal is then released by the zero voltage detecting circuit installed across Cr3. Step 5 (t4-t5):Resonant inductor current iLr decreases to the load current level iloadat t4. D,I becomes blocking and S3starts conduction.
Step 2: tl-tz
Step 8: t7-k
Step 3: tz-t3
Step 9 &t
Fig. 4. Step diagrams for the commutations between S I and S 3 when the load current is negative. (kis the transformer ratio, k=N?lNl,=N2/N12!)
ISl",,
... ...
, , ,
il,
VS,
lw
I
.
.
4,
fl
12
... ... . .
..,
t4
15
13
8
,
k
t7
I
t
cu
Fig. 5. Predicted theoretical waveforms for the commutationsbetween St and Ss in the first zero voltage switching pole with negative load current during a switching cycle.
Step 6 (t&: Resonant inductor current iLr and the auxiliary diode current in DI2 decreases to zero at t5. Sal gating signal can be withdrawn. Circuit reaches another steady state. The output is connected to the zero rail. S3 and Dc2 carry the load current. Step 7 (t6-t7):Turn off S3 and turn on Sa3at k, leading to conduction of the auxiliary diode DI1. An induced voltage source of kVdcappears on N2. Cr3 is charged and CrIis discharged. Step 8 (t&: Crl voltage declines to zero at t,. Currents in C,, and CrS transfer to D1 instantly. SI gating signal is released by the zero voltage detecting circuit installed across it. Step 9 (tg-tg): Currents in the resonant inductor Lr and the auxiliary diode DI I extinct at t8. Sa3 gating signal can be withdrawn. Circuit returns to the original state. D2 and DI carry the load current. Circuit output is connected to the plus rail.
will see the discharging of Cr2 and will not exactly be zero voltage switching as a result. Analogously, inner device S2 will see the same problem in the second pole when load current is positive. This problem is essentially resulted from the topological drawback of the NPC inverter--the inner two devices of a NPC leg are actually not directly clamped as in the two level inverter. For example, it is S3 in series with D,z that is clamped to C1, rather than S3 itself. In the same sense, it is S2 in series with DcI that is clamped to C2, rather than SI itself. Therefore, when S3 and S4 are both OFF,S3 can block higher voltage than S4 and Dc2can see some voltage rather than zero. Or, alternatively, when SI and S2 are both OFF, S2 can block higher voltage than SI and DcIcan see some voltage rather than zero. Obviously this problem can not be removed without changing the main circuit topology. However, it can be mitigated by careful busbar designing.
Note that the inner device S3 may not work exactly at zero voltage switching in practice when the parasitic inductances and capacitances of the circuit are taken into account. Assume a parasitic inductance with the neutral rail and a negative load current flowing through S3 and Dc2 connecting the output to the neutral rail. Now, to transfer the load current from S3 and Dc2to D2 and D1, the neutral rail current will decrease leading to discharging of the resonant capacitor Cr4 via Dc2. Upon reaching the steady state (D2 and DI conducting), both Cn and Cr4will be charged by C2 via the parasitic inductance of the neutral rail. Consequently, voltage across CR will not be zero. Thus for the next commutation, the turn-on of S3
111. CIRCUIT ANALYSIS AND DESIGNING Since each pole works in the same way as the transformer assisted PWM zero voltage switching pole inverter, the characteristics of the transformer assisted PWM zero voltage switching pole inverter applies also in the current circuit. Under the following assumptions, the commutation duration, the resonant inductor peak current and the resonate inductor RMS current (averaged over the switching cycle) in relation to load current, transformer ratio and switching cycle are shown in Fig. 6, Fig. 7 and Fig. 8 respectively. Details of the mathematical process have been included in [ 131.
I262
w 5I
16.893
3.704
14.601
3.142
12.309
2.58
10.017
2.01 7
7.725
1.455
5.433
0.893
3.142
0
0.5
I
1.5
2
2.5
0.33
3
0.5
0
1
2
1.5
-
2.5
3
iload
iload
(b) Switch to diode commutation
(a) Diode to switch commutation
Fig. 6. Variations of commutation durations t5, and tg6 with load current and auto-transformer ratio. 0.65
3.65 3. I25
0.549
2.6
0.447
2.075
0.346
I .55
0.244
1.325
0.143
-
i b i
ns "._
0
0.5
I
1.5
2
2.5
0.041
3
0
0.5
1
2
1.5
2.5
(b ) Switch to diode commutation
(a ) Diode to switch commutation
Fig. 7. Variations of the resmant inductor peak currents with load current and auto-transformer ratio.
I.42
0 136
I.2
0.114
.D.
k=0.25, _T=90
'-*k=O.15. T=45
0 092
0.91
__ 'Lmrms
0.5:
. .
. . .. .
0.047
.
0.024
0.3
0.a
0.069
038
0.53
1.03
-
1.52
0.002 2.01
2.Sl
3
iload
0.0110.509
1.008
1.506
-
2.004
'load
(b) switch to diode commutation
(a) diode to switch commutation
Fig. 8. Variations of the resonant inductor RMS currents with load current, transformer ratio and switching cycle.
1263
2.502
operating frequency. Rating of the auxiliary device can be
Snubbing capacitance CrI=Cr2=Cr3=Cr4=Cr, resonant frequency resonant impedance z
cw=lIm,
and
switching cycle T. Unit current
-
made , according to the auxiliary device RMS current =r~
0
stress, and the peak current stress as well given in Fig. 7. Gating signal width for the auxiliary switch must cover the maximum commutation duration given in Fig. 6 and remains constant over the low frequency cycle. In the meantime, the minimum pulse width in the inverter PWM pattern should not be less than this duration. The next commutation should not start before the conclusion of the previous commutation. On the other hand, transformer designing can be based on the knowledge of commutation (magnetization) duration and the RMS resonant inductor current stress. With peak and RMS resonant inductor currents information, the resonant inductor can be designed.
j=q,/(& /2),
unit voltagev=v/&.//2),unit time t = tu,. Circuit parasitics, device switching delays, losses etc. are neglected in the analysis. From Fig. 6, for diode to switch commutation, the commutation duration increases with load current but decreases with transformer ratio. For switch to diode commutation, it decreases with both load current and transformer ratio. From Fig. 7, for diode to switch commutation, the peak resonant inductor current increases with load current but decreases with transformer ratio. For switch to diode commutation, it decreases with both load current and transformer ratio. Moreover, from Fig. 8, the resonant inductor Rh4S current resulted from diode to switch commutation increases with load current, but decreases with transformer ratio and switching cycle. The resonant inductor RMS current resulted from switch to diode commutation, however, decreases with load current, transformer ratio and switching cycle. The reverse proportional relation of the commutation duration, resonant inductor peak current and resonant inductor RMS current with load current for switch to diode commutation highly justifies the auxiliary switch gating strategy in this paper to trigger the corresponding auxiliary switch simultaneously with the main switch not only for diode CO switch commutation where such triggering is indispensable for achieving zero voltage switching, but also for switch to diode commutation where such triggering becomes dispensable above certain load current level. Such triggering strategy facilitates significant control simplification while the extra loss so accrued during switch to diode commutation is negligible. Note that the auxiliary switch RMS current equals the diode to switch commutation component for one load current direction. It equals the switch to diode commutation component for the other load current direction. The peak current and RMS current stresses of the auxiliary diode in the transformer primary are given accordingly from the transformer ratio. For designing of the auxiliary circuit, the transformer ratio should be set less than 114 dependent on the actual resonant loop resistance to ensure the pole voltage swinging to the rail level during the commutation resonance. This requirement is hard and allows no bargaining. In addition, the resonant capacitance can be designed as per the device turn-off loss and the thermal condition associated. Resonant inductance can then be decided according to the accepted resonant circuit RMS stress based on Fig. 8, taking into account the system
IV. EXPERIMENTATION RESULTS A 7kW IGBT half bridge NPC inverter prototype has been built. The specifications of which are given in Table 1. Circuit parameters of the prototype are: Lr=12uH, Crl=CiL=Cr3=Cr4=0. luF, k=0.2. Auxiliary switch gating signal width is set at 14.4uS. Maximum and Minimum PWM widths are set at 136.8uS and 16.8uS respectively. Main switches S1-S4 and auxiliary switches Sal-Sa4 used are semikron SKMSOGB123D (1200V/50A). Auxiliary diodes Dc,-DCzand DacI-Da,z,used are ultra-fast HFA30T60C (600V/30A). Inverter output is installed with a second order filter Lf=l.45mH and Cf=12uF. Four 350V/3300uF capacitors are used at the DC link. It is worth mentioning that the prototype is modulated with normal sub-harmonic PWM pattern under which the neutral potential has been proved to be self-balancing when the load is not pure-reactive [14]. No specific measures are taken for stabilizing the neutral potential. Four simple zero voltage detecting circuits [14] are employed to interface the four semikron SKHlO drivsrs to the main IGBT devices for releasing the gating signals once the detected voltage reaches zero. Fig. 9 shows the main device S3 voltage and current waveformes during S3 to DI and DI to S3 commutations. Obviously, the main device works with zero voltage turnon and capacitive turn-off. No voltage/current spikes are produced in the process. In the meanwhile, Fig. 10 shows the waveforms of the auxiliary device Sa3 voltage and current as well as the load current during D,, to SI commutation. With a predicted commutation duration of 7.2uS according to Fig. 6(a) and a predicted peak resonant current of 47.8A according to Fig. 7(a), at load current of 20A, the experimental values ace 6.7uS and 40.5A respectively. The analysis results in Section I11 are well validated. Errors are due to the losses in the commutations neglected in the analysis.
1264
REFERENCES DC input voltage output power
V&= 8OOV P,= 7kW
V,
Output voltage Load current
=164V I,,,, =42.5A
Modulation index Switching frequency
M= 0.62 f,= 6.5kHz
[ l ] A. Nabae, I. Takahashi, and A. Akagi, “A New
Neutral-Point Clamped PWM Inverter”, IEEE Trans. Ind. App., Vol. 19, No. 5, Sep./Oct. 1981, pp. 518523. H. Stemmler, “Power Electronics in Electric Traction Applications”, Record of IEEE IECON, 1993, pp. 707-713. B. A. Renz, A. J. F. Heri, A. S. Mehraban, J. P. Kessinger, C. D. Cchauder, L. Gyugyi, L. J. Kovalsky and A. A. Edris, “World’s First Unified Power Flow Controller on The AEP System”, CIGRE Paper 14107, 1998. [4] A. Steimel, “Electric Railway Traction in Europe”, IEEE Industry Applications Magazine, Nov./Dec. 1996, pp. 7-17. [5] T. Salzmann, G. Kratz, C. Daubler, “High Power Drive System with Advanced Power Circuitry and Improved Digital Control”, IEEE Trans. on Ind. App., Vol. 29, No. 1, Jan./Feb. 1993, pp. 168-174. [6] H. Schambock and K. Schiftner, “A New Snubber for GTO Applications with Energy Recovery by an ActivePassive Circuit”, Record of EPE Conference, 1989, pp. 707-711. [7] H. Okayama etc., “Large Capacity High Performance 3-Level GTO Inverter System for Steel Rolling Mill Drives”, Record of IEEE IAS, 1996, pp. 174-179. [8] J. A. Tarfiq and Y. Shakweh, “New Snubber Energy Recovery Scheme for High Power Traction Drive”, Record of IPEC-Yokohama, 1995, pp. 825-830. [9] J. Holtz and S. Stadtfeld, “An Economic Very High Power PWM Inverter for Induction Motor Drives”, Record of EPE Conference, 1985, pp. 3.375-3.380. [lo] W. Yi and G. H. Cho, “Novel Snubberless ThreeLevel GTO Inverter with Dual Quasi-Resonant DCLink”, Record of IEEE PESC, 1991, pp.880-884. Ill] J. G. Cho, J. W. Baek, D. W. Yo0 and C. Y. Won, “Three Level Auxiliary Resonant Commutated Pole Inverter for High Power Applications”, Record of IEEE PESC, 1996, pp.1019-1026. [12] Xiaoming Yuan and Ivo Barbi, “Control Simplification and Stress Reduction in A Modified PWM zero voltage switching Pole Inverter”, Record of IEEE APEC, 1999. [13] Xiaoming Yuan and Ivo Barbi, “Transformer Assisted PWM Zero Voltage Switching Pole Inverter”, Record of IEEE PESC, 1999. [ 141 Xiaoming Yuan, “Soft Switching Techniques for Multilevel Inverters”, Ph. D Thesis, INEP-UFSCBrazil, May 1998.
loOV/DIv.IOA/DIv, 4uSDiv
Fig. 9. Experimental waveforms of the main switch S3 voltage and current during S , to DI commutation and DI to S3 commutation..
,
.
.
.................................................................
:
: .,.... . . . .................. ....:........................................ I
Fig. 10. Experimental waveforms of the auxiliary switch Sa3 voltage and current as well as the load current during D,I to SIcommutation.
V. CONCLUSIONS The analysis and experimentation presented verify that the proposed small rating zero current switching auxiliary circuit guarantees the zero voltage switching of the NPC main switches, without requiring any extra monitoring or controlling and without incurring any voltagdcurrent spikes or modulation constraints. The auxiliary switches block the same voltage as the main switches. The scheme can be used to advantage for high frequency application of the GTO NPC inverter where conventional snubbers are not expected to offer adequate performance.
1265
