A Two-Switch Buck-Boost PFC Rectifier With ...

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Abstract—In this paper, a single-stage power-factor- correction (PFC) rectifier with active power decoupling function is proposed. The proposed rectifier has a ...

A Two-Switch Buck-Boost PFC Rectifier With Automatic AC Power Decoupling Capability Wenlong Qi1, Sinan Li1, Siew-Chong-Tan1 and S. Y. (Ron) Hui1,2 Email: [email protected], [email protected], [email protected], [email protected] 1

Department of Electrical and Electronic Engineering, The University of Hong Kong, Hong Kong, China 2

Department of Electrical and Electronic Engineering, Imperial College London, U.K.

Abstract—In this paper, a single-stage power-factorcorrection (PFC) rectifier with active power decoupling function is proposed. The proposed rectifier has a low component count as compared to existing solutions. Only two active switches, one inductor and one small power-buffering capacitor are needed. High power factor, wide output voltage range and active power decoupling can be simultaneously obtained. In addition, the rectifier has an inherent automatic power decoupling capability, and no dedicated active power decoupling control is required. Therefore, the control of the rectifier is simple and easy to implement. A 100 W prototype of the proposed rectifier with 110 Vrms/50 Hz input and a regulated DC output voltage ranging from 30 V to 100 V has been constructed and tested. The results show that with only a 15 ȝF power-buffering capacitor, a power factor of over 0.98, peak efficiency of 93.9% and output voltage ripple of less than 3% has been achieved. Keywords—Single-stage, automatic power decoupling.

Power-factor-correction

rectifier,

I. INTRODUCTION Single-phase power-factor-correction (PFC) rectifiers have the inherent problem of possessing a double-line-frequency ripple-power that pulsates between the AC input and the DC output [1]. Without buffering of this ripple-power, the DC voltage output of the rectifier will fluctuate significantly. Voltage fluctuation is undesirable for applications such as light-emitting-diode lighting (causing flickers) [2]–[6] and battery charging (overheating) [7]. Using bulky electrolytic capacitors (E-Caps) is a common solution to reduce the voltage ripple. However, an E-Cap can take up more than 80% of the system volume [8] and can substantially reduce the reliability, and hence the lifetime of the overall system. Active power decoupling technique is an effective method to reducing the capacitance requirement for buffering ripple power [7], [9], [10]. It enables non-E-Caps with long lifetime (e.g. film capacitors, stack ceramic capacitors) to be used in the design. With this technique, the double-line frequency power of the rectifier is diverted into an external capacitor (or an inductor). By allowing a large voltage fluctuation to appear across the capacitor, only a small capacitor is required to store a large amount of ripple power. A typical active power decoupling circuit, like an activepower filter, requires additional active switches, diodes and/or bulky inductors. These extra components lead to increased rectifiers’ volume and cost. Recently, several attempts have been made to simplify the circuit structure through component sharing between the rectifier and the power decoupling circuit

978-1-5090-0737-0/16/$31.00 ©2016 IEEE

[7], [9]–[15]. As a result, the total component count could be reduced. In these solutions, the minimum number of active switches reported is three. In [16], a new rectifier that has active power decoupling capability using two active switches has been proposed. The idea is to introduce a power-buffering cell into the topology, such that two extra operating modes are created, i.e., power charging phase and power discharging phase. With only two active switches, the solution is simple and cost-effective. One major limitation of this rectifier, however, is that the output voltage is limited to only half of the peak input voltage. In this paper, the idea of introducing a power buffer cell is further explored and a two-switch buck-boost type PFC rectifier is reported. Similar to [16], the converter is capable of realizing PFC, output regulation and power decoupling in a simple manner. Due to the buck-boost-like operation, the rectifier naturally provides a wide output voltage range in a single-stage conversion. To complement the design, an automatic power decoupling control without a complicated decoupling control loop is also proposed. The feasibility of the proposed rectifier and the automatic decoupling control technique are verified through both simulation and experiments on a 100 W prototype using a 15 ȝF non-electrolytic capacitor. II. PROPSED TWO-SWITCH BUCK-BOOST PFC RECTIFIER Large capacitor

SB

vg

DA

EMI Filter

Co

Ro

L

(a) CS

small capacitors SA

SB

vg

DA

EMI Filter

Co

Ro

L

(b) Fig. 1. Circuit topologies of (a) a conventional buck-boost PFC rectifier and (b) the proposed two-switch PFC rectifier.

switching patterns and the associated charging/discharging states for CS and L are summarized in Table I.

Fig. 1(a) shows a conventional single-phase PFC rectifier based on a buck-boost converter topology. It has a simple structure and low bill-of-material. Only one active switch SB is needed. PFC and wide-range output voltage regulation can be easily attained simultaneously by controlling SB. One major drawback of the buck-boost PFC rectifier is that the output capacitor Co must be sufficiently large in order to buffer the double-line-frequency ripple-power (i.e. the instantaneous difference between the pulsating AC input power and the constant DC output power) to assure a small output voltage ripple. Usually, an electrolytic capacitor with relative short lifetime is used for Co.

According to Fig. 3 and Table I, it is clear that State 1 and State 2 are identical to the operating states in a conventional buck-boost converter. During these two states, CS is in idle mode and is not involved in the circuit operation. In State 3 and State 4, CS is connected in series to the inductor L. CS can thus be charged or discharged by the inductor current iL. The amount of energy to be absorbed/released by CS can be precisely controlled by varying the duration of State 3 and State 4, respectively. Due to the capability of bidirectional power flow from the power-buffering capacitor CS to the rest of the converter, active power decoupling using CS is viable.

Fig. 1(b) shows the proposed buck-boost type PFC rectifier. Compared to Fig. 1(a), the new rectifier incorporates one extra active switch SA and one power-buffering capacitor CS. As will be shown in Section III, the addition of the two components creates two extra operation modes which enable active charging and discharging of the capacitor CS. Consequently, the new rectifier has an additional power decoupling capability, while retaining the functions of PFC and output voltage regulation. Through proper control, CS is able to fully compensate the double-line-frequency pulsating ripple-power. The capacitance requirement for Co can be substantially reduced since Co is required only for filtering the highfrequency ripple. On the other hand, the capacitance of CS can also be small, if a large voltage variation across CS is allowed. These new features are more advantageous than those of conventional buck-boost PFC rectifier. Since the capacitance requirement is low, the new rectifier can be constructed without using an electrolytic capacitor.

With reference to Fig. 3, one operating constraint of the system is

ig

Vc

Fig. 2. Simplified equivalent circuit of Fig. 1(b). Table I. Summary of Switching Paterns. Operating State

SA

SB

CS

L

State 1

1

0

Idle

Charge

State 2

0

1

Idle

Discharge

State 3

0

0

Charge

Discharge

State 4

1

1

Discharge

Charge

Vc

vg

Co

Ro Vo

L (SA = 1, SB = 0) State 2

(SA = 0, SB = 1) State 1 Vc

SA

vg

(SA = 0, SB = 0) State 3

SA

CS DA

SB Co

L

Vc

Dr

CS DA

Fig. 3. Operation mode for State 1 to State 4.

SA

CS DA

L

SB

Ro Vo

L

Dr

Ro Vo

io Co

SB Co

ic

iL

SA

vg

SA

Vc

DA

DA

Dr

CS

vg

CS

SB

Dr SB

III. PRINCIPLE OF OPERATION To facilitate circuit analysis, the effect of the EMI filter in Fig. 1(b) is neglected and the front-end diode bridge rectifier is represented by a diode Dr. The equivalent circuit of Fig. 1(b) can be simplified as shown in Fig. 2. Assuming continuous conduction mode of operation, the rectifier has four possible operating modes (depicted as State 1–State 4 in Fig. 3). The Dr

(1)

vc ! vg  vo .

Ro Vo vg

Co L (SA = 1, SB = 1) State 4

Ro Vo

vg

vg

vc*

vc

ig *

Gv1(s)

iL * io

vc

*

iL

SA

vc*

vc

vo *

dB

Gv2(s)

SB

Carrier_b

vo

sin(Ȧt)

f=

Gv1(s)

Ig*

ig *

iL * io

vc

Carrier_a

1 Ro

LPF

dA

Gi1(s)

PLL

*

Gi1(s) iL

SA

Carrier_a

Notch vo *

Gv2(s) vo

(a)

dA

dB

SB

Carrier_b

(b)

Fig. 4. Control schematics for the proposed two-switch rectifier with automatic power decoupling. (a) a low-cost implemention when the load resistance is known. (b) an implementation for a general load

where vg is the rectified input voltage, vc is the voltage of the power-buffering capacitor CS and vo is the output voltage. In this way, Dr in State 2 and State 4 are reverse-biased and can be securely turned OFF during these two states. It can also be concluded from Fig. 3 that the inductor current iL is related to the rectified input current ig and output current io as

iL

(2)

ig  io .

y when sa = 1, dvo/dt = (iL – vo/Ro)/Co = (iL – io)/Co = ig/Co t 0, and vo increases; y when sa = 0, dvo/dt=(– vo/Ro) /Co < 0, and vo decreases. The above analysis suggests that vo has a monotonic relationship with sa. Thus, vo is controllable through SA. On the other hand, with reference to (3) and considering the constraint of (1), the dynamics of the inductor current iL can be expressed as y when sa = 1, sb = 1, diL / dt = (vc – vo) / L > 0, and iL increases;

where iL, ig and io are the time-averaged over one switching

y when sa = 0, sb = 1, diL / dt = vg / L > 0, and iL increases;

period.

y when sa = 1, sb = 0, diL / dt = – vo / L< 0, and iL decreases; y when sa = 0, sb =0, diL / dt = (vg – vc) / L< 0, and iL decreases.

IV. CONTROL STRATEGY WITH AUTOMATIC POWER DECOUPLING A. Control Analysis With reference to Fig. 3, the state-space averaged equations describing the dynamics of the inductor current iL, the output voltage vo and the voltage vc of the power-buffering capacitor CS, can be expressed as

L

diL dt

v

g



Co CS





 vc  d A vg  vo  vc  d B vc ,

dvo dt

dvc dt

d AiL 

vo , Ro

1  d A  d B iL ,

(3) (4) (5)

where dA and dB are the duty cycles for the switches SA and SB, respectively and are also the control input, iL, vo and vc are state variables and are also the control outputs, and vg is the system’s input. Here, the switching functions for SA and SB are respectively defined as sa and sb, where si  {0, 1} and i  {a, b}. si = 1 indicates that the associated switch is ON, and si = 0 indicates that the associated switch is OFF. According to (4), different situations of the switching action can be expressed as

The above analysis shows that iL has a monotonic relationship with sb, despite the state of SA. Therefore, iL is controllable through SB. Once the switching actions of SA and SB are determined such that iL and vo are regulated at their desired values, the instantaneous input and output power are also determined. As a result, their power difference (the double-line ripple power) will be automatically transferred to the energy-buffering capacitor CS. There is no need to design a dedicated power decoupling control for regulating the instantaneous voltage of vc. In other words, power decoupling is achieved automatically. This is in contrast to conventional rectifiers with active power decoupling function in which a complicated power decoupling control is unavoidable. The elimination of a sophisticated power decoupling control loop greatly simplifies the controller design and a low-cost control unit can be employed for implementing the control. Based on the above analysis, Fig. 4 illustrates two possible control schematics for the proposed two-switch buck-boost rectifier. Fig. 4(a) is for a low-cost implementation and is suitable for applications where the output load resistance Ro is known. Fig. 4(b) is an advanced version of Fig. 4(a) and is more suitable for general load applications. In both cases, iL and vo are respectively controlled by SA and SB via a current compensator Gi1(s) and a voltage compensator Gv2(s). Proportional-integral-plus-resonant compensators (PIR) are

Carrier_a

Carrier_a dA dA Sawtooth carrier

Carrier_b

Sawtooth carrier

Carrier_b dB

dB SA

1

0

0

1

0

SA

1

0

1

1

0

SB

0

1

0

0

1

SB

0

1

1

0

1

iL

iL

charging

vc

discharging

vc State

2

1

3

2

1

State

2

1

4

2

1

(a)

(b)

Fig. 5. Gate signal generation for SA and SB using two out-of-phase sawtooth carriers with associated inductor current and capacitor voltage waveforms when (a) capacitor CS is charging (b) capacitor CS is discharging.

selected for Gi1(s) and Gv2(s) to ensure a zero steady-state error and to avoid possible disturbances at the double-line frequency and high-order line frequencies. The reference signal iL* is obtained based on (2) by summing the rectified input current reference ig * and the output current reference io*. At the same

ensures a smooth transition between charging and discharging mode with three active states.

time, ig * is obtained from an outer voltage loop regulating the

Table II. Key Simulation and Experiment Parameters. Parameters Values Parameters Values Rated power Po 100 W Line frequency 50 Hz EMI filter cutPeak AC voltage 155 V 1.2 kHz off frequency Switching DC output voltage Vo 25 kHz 30ˉ100 V frequency Output capacitor Co 10 ȝF/ 150 V Inductor L 3.5 mH Power-buffering 15 ȝF/ 450 V (450V film capacitor) capacitor CS UF5404-E3/54 VRRM : 400 V, IF : 3 A Diode bridge VF : 1.0 V, Trr = 50 ns (Vishay Semiconductor) SCS206AGC VRRM : 650 V, IF : 6 A Diode DA (Rohm Semiconductor) VF : 1.35 V, Trr = 0 ns VDS : 600 V, RDS (ON) : AOT20S60L (Alpha & Omega ȍ SA and SB Semiconductor Inc.) Tr : 32 ns, Tf : 30 ns

*

average value of vc, i.e., vc , at vc . Considering that a small Cs will lead to significant second and high-order line frequency ripple in vc, a low-pass filter or a notch filter with stopping bands at these frequencies can be employed to obtain vc . To achieve the regulation of vc , a low-bandwidth proportionalintegral compensator (PI) can be chosen for Gv1(s). B. Gate Signal Generation To generate the proper gate signals for SA and SB, the output of Gi1(s) and Gv2(s), i.e., dA and dB, are modulated by two outof-phase sawtooth carriers, Carrier_a and Carrier_b, respectively, as shown in Fig. 4.

V. SIMULATION AND EXPERIMENT RESULTS A. Simulation Results

The advantage of the modulation method is that minimum state-transition times can be achieved. In particular, only three operating states will be active per switching period instead of four. The use of fewer operating states might help to improve the energy efficiency since power is processed fewer times.

Fig. 6 shows the simulation results of the two-switch buckboost PFC rectifier based on the control method described in Fig. 4(b). To filter out the switching ripples in the input current, a ʌ-shape C-L-C filter with a cut-off frequency of 1.2 kHz is selected as the front-end EMI filter. The key simulation parameters are listed in Table II.

Fig. 5(a) and (b) illustrate the timing diagram of the gate signals of SA and SB against their associated carriers, during CS charging phase and discharging phase, respectively. The instantaneous waveforms of iL and vC are also shown. As shown, during the CS charging phase, the effective operating states are State 1, State 2 and State 3, while during the CS discharging phase, the effective operating states are State 1, State 2 and State 4. Such a modulation method inherently

It can be seen from the simulation results that the input current ig is sinusoidal and is in phase with the input voltage vg. The output voltage is well regulated at 100 V with negligible double-line frequency ripple. Meanwhile, the voltage of the energy-buffering capacitor vc is regulated at around 300 V and is fluctuating with significant magnitude. The low-frequency pulsating waveform of vc indicates that CS is performing the

power decoupling function. Due to the large voltage fluctuation, a small capacitor of 15 ȝF is sufficient for handling the full ripple power of the 100 W rectifier. It is important to notice that vc is always larger than the sum of vg and vo. As a result, normal circuit operation is ensured. 150

vg ig

00

50

-150 vc 300 100

vo

0 0

0.01 Time (s)

0.02

Fig. 6. Simulated operation waveforms of the input voltage, input current, the output voltage and the voltage of the power-buffering capacitor (with Po=100 W, Vg =155 V, CS =15 ȝF, L =3.5 mH, fsw= 25 kHz).

B. Experiment Results

A 100 W prototype for AC input of 110 Vrms/50 Hz (generated by a voltage source, Model: GW Instek APS-9501) with the component specifications given in Table II has been constructed and tested. One single high and low side gate driver IR2102 is used to drive SA and SB simultaneously. To reduce the switching loss and conduction loss, MOSFETs with low drain–source on-resistance (RDC(ON)) and junction charges are selected for SA and SB. In addition, Silicon-Carbide (SiC) diode with zero reverse recovery charge is chosen for DA. A small power-buffering capacitor CS of 15 ȝF film capacitor is selected. Fig. 7(a) shows the steady-state waveforms of the input voltage vg, line current ig, output voltage Vo and the voltage of the power-buffering capacitor vc. A sinusoidal line current that is in phase with the line voltage has been obtained. In addition, vo is precisely regulated at 100 V with a peak–peak ripple of merely 3 V (i.e., 3% of the average output voltage). The result is in contrast to the rectifier proposed in [16], of which the output voltage is limited to half the peak input voltage. At the same time, the measured vc is varying between 250 V and 300 V. The low-frequency varying waveform of vc indicates that CS is actively performing AC ripple power decoupling. Fig. 7(b) shows the corresponding current waveforms of the rectifier. As predicted in (2), which shows that the average inductor current iL is equal to the averaged sum of the rectified line current and the output current, the measured iL in Fig. 7(b) is always larger than the output current and is low-frequency pulsating. vg : [200 V/div]

vc : [50 V/div]

vc : [100 V/div] vSB : [100 V/div]

vo : [50 V/div]

vo = 3 V

vg : [200 V/div]

vDA : [100 V/div]

ig : [2 A/div]

Time : [10 ms/div]

Time : [10 ms/div]

(a)

(a) vg : [200 V/div]

vg : [200 V/div]

vc : [200 V/div]

iL : [1 A/div]

vSA : [200 V/div]

vDr1 : [200 V/div]

io : [1 A/div] ig : [2 A/div]

Time : [10 ms/div]

Time : [10 ms/div]

(b) Fig. 7. Measured steady-state (a) voltage and (b) current waveforms of the twoswitch buck-boost PFC rectifier.

(b) Fig. 8. Measured steady-state (a) voltage and (b) current waveforms of the twoswitch buck-boost PFC rectifier.

Fig. 8 depicts the voltage waveforms of the switching devices. The voltage vc is always applied to the switch SB and the diode DA (Fig. 8(a)) when they are “turned OFF”, whereas a differential voltage of vc  vo  vg is imposed on SA and the diode bridge (only one out of the four diode is measured here) (Fig. 8(b)). Due to the low voltage applied, SA and the diode bridge should have relatively smaller switching losses (including the diode reverse recovery losses) than those of SB and DA. Fig. 9 shows the measured efficiency, power factor and total harmonic distortion of the proposed rectifier within the range of 40% to 100% of the rated power. In the measurement, t the change of the output power is achieved by changing the reference command of the output voltage vo* while the load resistance is kept constant Fig. 9(a) shows that the peak efficiency of the rectifier is around 93.9% and the efficiency curve is fairly flat within the entire power range that is examined. Fig. 9(b) shows that the power factor of the rectifier is above 0.98 and the THD is less than 8.5%.

order to further reduce the switching losses and improve system efficiency, soft switching and/or special gate signal modulation techniques might be employed [17], [18]. This will be open for future work.

LEMI L Dr DA SA SB 0

0.5

1

1.5

2

2.5

Power losses (W)

Fig. 10. Simulated power loss audit of the two-switch buck-boost PFC rectifier (Po=100 W, Vg =155 V, CS =15 ȝF, L =3.5 mH, fsw= 25 kHz and Tline= 20 ms).

Efficiency

94.0% 93.9% 93.8% 93.7% 93.6% 93.5% 40

60 80 Output power (W)

100

0.994

8.5

0.992

8.0

0.990

7.5

0.988

7.0 Power factor THD

0.986 0.984 40

60 80 Output power (W)

6.5

THD (%)

Power factor

(a)

6.0 100

CONCLUSIONS In this paper, a two-active-switched PFC rectifier based on the conventional buck-boost topology is reported. The converter can achieve a high power factor, wide output voltage range and active power decoupling operation (using only two active switches, one inductor, one small high-frequencyfiltering capacitor, and one small power-buffering capacitor). To complement the system design, an automatic power decoupling control scheme is proposed so that the need for a complicated power decoupling loop as conventionally required is eliminated. The experimental results show that a peak efficiency of 93.9% can be achieved, with a power factor higher than 0.98 and THD less than 8.5%. Also, the voltage ripple present is merely 3% for a 100 W prototype using only a small non-electrolytic capacitor of 15 ȝF. ACKNOWLEDGMENT This work was supported by the Hong Kong Research Grant Council with the Theme-based Research Project: T23701/14-R/N.

(b) Fig. 9. (a) Measured efficiency and (b) power factor and THD curves of the two-switch buck-boost PFC rectifier against the output power.

Finally, Fig. 10 shows the power loss distribution of the converter. The results are obtained through simulation. Parasitic parameters, such as the drain–source on-resistance of the MOSFETs, the equivalent series resistance (ESR) of the inductors, etc., have been taken into consideration. The power losses are then averaged over one line period of Tline. As shown, the conduction loss of the diodes contributes most to the power losses. This can be explained by comparing the length of the conduction intervals of Dr and DA to that of SA and SB based on Fig. 3. In addition, SB has a higher switching loss as compared to SA. The result is consistent with the previous analysis. In

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