e-mail : tomisima@,lsi.melco.co.jp chip. Abstract. A System In a Package (SIP) is another candidate of future embedded system chips against the System On a.
A Variable Drivability (VD) Output Buffer for the System In a Package (SIP)
and High Frequency Wafer Test Shigeki Tomi~hirna’,~, Hiroaki Tanizaki’, Mitsutaka Niirol, Masanao Maruta’, Hideto Hidaka’, T. Tada3and Kenji Gamo4
,
1 - ULSI Development Center, Mitsubishi Electric Corporation 3 - System LSI Development Center, Mitsubishi Electric Corporation 4-1, Mizuhara, Itami, Hyogo 664-8641, Japan 2 - Electronic Devices Design Center, Mitsubishi Electric Engineering Co., Ltd., 4-61-5, Higashino, Itami, Hyogo 664-0004, Japan 4 - Division of Advanced Electronics and Optical Science, Graduate School of Engineering Science, Osaka University, 1-3 Machikaneyama-cho, Toyonaka, Osaka 560-853 1, Japan e-mail : tomisima@,lsi.melco.co.jp Abstract A System In a Package (SIP) is another candidate of future embedded system chips against the System On a Chip (SOC). The SIP has intra connections, which have small IO load. On the other hand, the high /+equency wafer test has large IO load caused by probe, Hi-Fir and coaxial cable. This paper makes these incompatible load problems clear and proposes a new output buffer to overcome them. A new variable drivability (VD) output buffer can provide the optimum driving abiliiy for both the SIP intra-connection and the high frequency (over I OOMHZ) wafer test. This proposed output buffer realizes new SIP test Jlow containing high frequency wafer test and reduction of the total test cost of embedded DRAM chip by 35% compared with the SOC test cost.
includes many functional parts, CPU, DSP, ALU and DRAM. This embedding in a chip can brings high performance, cost effective, and low power. As one of popular candidate of such a system chip, shown in Fig. I , we have studied the System On a Chip (SOC) ,which has many IP cores in the same die. As the embedded DRAM in the SOC can bring low power consumption and high bandwidth, many SOCs with embedded DRAM have been developed and reported [l-51.
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1. Introduction
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Rapid progress of an advanced information-oriented society demands the embedded system chip, which
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SOC(System On a Chip)
SIP(Systern In a Package)
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Paper 7.2 170
Fig. 2. Chip internal image (a) SOC and (b) SIP.
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Fig. 3 . Test flow (a) SOC test flow,
However, embedding DRAM itself caused some problems. For instance, the cost-up from the additional DRAM capacitor process steps, the transistor performance degradation from DRAM capacitor's thermal budget and testing complexity exists. The test complexity comes from the fact that all signals among each functional core are only internal connections fabricated by metal signal lines. Therefore, no external signal path exists to test each functional core directly, as shown in Fig. 2(a). Actually various Design For Test (DFT) containing the Built-In Self-Test (BIST) has been studied [6-91 in order to remove the complexity of testing core, but those have not reached complete resolution yet. Recently, the System In a Package (SIP) technology has attracted us as another candidate of the system chip form [IO]. In the SIP, plural chips, CPU, DSP and memory are housed in one package and they operate as a system chip. Usually, the base chips are fabricated by different process technologies and tested each before packaging. So this feature can eliminate the performance degradation problems as the SOC. And at the memory capacity up-grade, SIP has no necessary to redesign chip and can realize quicker turn-around-time compared with SOC. This paper describes the study of the SIP intra-connection and proposes new wafer test flow and new output buffer for the SIP embedded DRAM.
(b) SIP test flow
However, there are two limitations for such wafer test, which are the IO number and the clock frequency. Even though DRAM core itself has large 1 0 ports, the external ports are usually degenerated to smaller numbers through the TEST unit [11], as shown in Fig. 2(a). Next, the large IO load of the wafer probe card has limited the testing clock frequency, for instance, under 6OMHz. These two limitations impose the pseudo test condition thorough the test unit and the high frequency final test after packaging. In the SIP, however, large numbers of IO pads have been already prepared on the die for the intra-connection, as shown in Fig. 2(b). Thus, we proposed new test flow for the SIP shown in Fig. 3(b). The high frequency and multi IO test on the wafer condition can eliminate the final test by the memory tester after packaging. Its cost reduction effect due to new SIP test flow will be explained in detail at chapter 5.
3. Optimization of the Output Buffer Size In order to realize new SIP test flow proposed in chapter 2, we studied the optimum buffer size for two different 10 load conditions, which are the SIP intra-connection and the high frequency wafer test.
2. Test Flow for SIP Fie. 3(a) shows a eeneral test flow of the SOC. After the embedded DRAM process steps, two different testers perform tests on each core in the SOC separately on the wafer condition. Esueciallv. because the DRAM core has redundant circuit for improving the yield, the wafer test and the redundant replacement are necessary. ~I
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Fig. 4. The SIP connection (a) wire connection, (b) bump connection
Paper 7.2 171
Electromagnetic Field Simulator composed of the finite element method. Fig.5 shows the input figure pattern of the wire connection. As simulation parameters, material, wire diameter and hump diameter is assumed Au, 30um and IOOum respectively. The electrical LCR model of the SIP intra-connection is shown in Fig. 6, and the simulated values are listed in Table I. Fig. 7 shows the results of the electrical circuit simulation with 0.13um process transistor parameter for LCR model shown in Fig. 6. As a worst case, the supply voltage is set lower limit of 1.35V, and the signal I2 is anti-phase at others. It is confirmed that the rising time delay of the hump connection becomes smaller than the wire connection due to small LCR values. And we obtained enough output buffer size of 16urn for PMOS and Xum for NMOS transistor. It is also noticed that the signal time delays in parallel-phase are almost half of ones in anti-phase. @27C,Vdd=l .JIV,anti-phase 2
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Fig. 5. The SIP input figure pattern of wire connection
3.1. Estimation for the SIP Intra-connection There are two different intra-connections in the SIP, as shown in Fig. 4(a) and (h). One is the wiring and another is the bump connection. The IO load of these different SIP intra-connection is calculated by the 3D
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3.2. Estimation for the Wafer Test
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Next, in order to optimize the buffer size for the wafer test with high clock frequency, the circuit simulation with the LCR load model on the wafer test
Fig. 6 . The SIP intra-connection LCR model
Table 1. Simulated SIP LCR values.
(b) Probe model
(C)
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172
Load Condition
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condition, as shown in Fig. 8 (a), is performed. This model is composed of four parts, the probe, the probe card, the HI-Fix and the tester part. In the probe part, three probes are located closely with mutual interferences each other. Therefore, the mutual inductance and capacitance exist in the LCR model, as shown in Fig. 8 (b). At other parts, however, because the ground line shields the transmission line, these LCR models are independent, as shown in Fig. 8 (c). We used these LCR values proffered from ATE makers. Recently, the LCR values of the probe part for over 100MHz. frequency are realized by latest probing technology. We performed the circuit simulation with mentioned wafer test LCR model under the test condition listed in Table 11. As shown in Fig. 9, large driver can bring small rising time delay. In the wafer test of lOOMHz and beyond, it is assumed that the output delay time should be suppressed to near 1 ns.
Fig. 10. SIP wire CaMnection wave forms with large drivability.
Therefore, it is estimated that the buffer size for high frequency wafer test should be over lOOum for PMOS and 50um for NMOS transistor. And next, we confirmed whether the excess driving ability of large buffer for the wafer test causes had influence to the SIP intra-connection or not. As shown in Fig. 10, excess drivahility caused large ringing for the small IO load in the SIP intra-connection. And it would give birth to the reliability problem at the in-put buffer at another internal chip. This simulation result shows that it is impossible that large output buffer for the wafer test can not drive small SIP intra-connection without reliability problem.
4. Variable Drivability (VD) Output Buffer 4.1. Hybrid type We propose the hybrid output buffer circuit, as shown in Fig. 1 1 . Two different sized buffers are provided in a parallel way for each bonding pad, small buffer for the SIP intra-connection and large one for the wafer test. As explained in chapter 3.1, small buffer size is enough 16um for PMOS and 8um for NMOS transistor. On the contrary, large size reaches 150um for PMOS and 75um for NMOS transistor. And the mode select signal (MODE) is asserted to both output buffers in order to change the huffer according to operation mode, the normal SIP operation mode or the wafer test
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Fig. 12. Buffer circuit for the wafer test.
Paper 7.2 173
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Voltage (V) capacitance. of the wafer test buffer reaches about 0.2 pF. In the case of SIP hump connection, this additional capacitance causes these problems, larger transition delay and much power consumption. Because the hump connection does not have so large parasitic capacitance as shown in Table I. Thus, the reverse body bias (RBB) supply, Vpp level of 2.5V and Vbb level of -I.SV, can decrease the junction capacitance of 25% in the estimation from Fig. 13. Futhermore, we confirmed about 15% improvement of transient delay in the hump connection by the circuit simulation, as show in Fig. 14.
Fig. 13. Measuredjuni:tion
mode. As shown in Fig. 12, at the wafer test mode, the signal MODE of "H' makes large buffer enable and small buffer disenable. The disenable state of the buffer means tri-state not to disturb another buffer's output. Next, in the SIP intra-connection mode, the junction capacitance of large buffer becomes an obstacle to high speed transition and low power consumption by small buffer. Thus, the MODE signal also changes the well bias of the wafer test buffer in order to reduce the junction capacitance attached to the output node. In the wafer test mode, the normal body bias (NBB) condition is adapted to buffer transistors in order to get fast transient time with high drivability, Vdd for PMOS and ground for NMOS. On the other hand, in the SIP intra-connection mode, the body bias is fixed to higher voltage Vpp for PMOS and negative voltage Vhb for NMOS transistor. The Fig. 13 shows the measured junction capacitance characteristic of real device fabricated by the 0.13um CMOS process technology, which area is 600 x 900 urn2. The junction capacitance
4.2. Single type withforward body bias We also propose the single output buffer with forward body bias (FBB) to reduce the element number and layout area, as shown in Fig. IS. This single output buffer can supply two different drivability by changing the body bias of output transistor, normal body bias (NBB) or forward body bias (FBB) condition. For the small IO load of the SIP intra-connection, the NBB is adapted to the output transistor and generate small drivability. On the other hand, for large IO load of the high frequency wafer test, the FBB is supplied and brings large drivability. The reason why the single
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Paper 7.2 174
Fig. 15. Single type output buffer.
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