A Very Low Spurious X-Band Frequency

IEICE TRANS. ELECTRON., VOL.E91–C, NO.11 NOVEMBER 2008

1744

PAPER

Special Section on Microwave and Millimeter-wave Technologies

A Very Low Spurious X-Band Frequency Quadrupler with Very High Integration Using 3D-MMIC Technology Yo YAMAGUCHI†a) , Takana KAHO† , and Kazuhiro UEHARA† , Members

SUMMARY A highly integrated frequency quadrupler MMIC that uses three-dimensional MMIC (3D-MMIC) technology is presented. It consists of four driver amplifiers, two doublers, and a 2-band elimination filter. These seven circuits are integrated in only a 2.36 mm2 area. The filter sufficiently suppresses spurious output components. The third and fifth harmonic components, which are the spurious components nearest to the desired component, are well suppressed. The desired/undesired ratio is about 40 dB. The driver amplifiers make the quadrupler output a constant power of the desired multiplied signal under low input power. The MMIC supplies +5 dBm of the fourth harmonic component in the input power range from −10 dBm to +5 dBm. The power dissipation of the MMIC is only 160 mW. key words: quadrupler, doubler, 3D-MMIC, 2-band elimination filter, low spurious

1.

Introduction

The broadband environment has recently been developing very rapidly. Fixed wireless access (FWA) systems have the advantage of providing fast Internet services to areas and user homes where it is difficult to provide broadband optical access. However, FWA equipment is still very expensive because the main market for these systems is business users and these systems must assure high link quality over long distances. Moreover, the equipment is large and heavy, so it is difficult to provide such service to homes. To provide a low cost FWA system for home and SOHO users, NTT Corporation developed the Wireless IP Access System (WIPAS), which is a point-to-multipoint (P-MP) FWA system in the 26-GHz frequency band [1]. To reduce equipment size and costs, MMICs, which integrate the RF block, have been developed. The signal in the quasi-millimeter band can be directly generated either by a quasi-millimeter frequency oscillator or by a low-frequency oscillator and a frequency multiplier. When a quasi-millimeter frequency oscillator is used, frequency dividers must be used because low cost PLL-ICs operate at up to 6 GHz. Quasi-millimeter frequency dividers consume a lot of power [2], and quasi-millimeter frequency oscillators are expensive. In contrast, low-frequency oscillators for wireless LANs are inexpensive and provided by a variety of makers. Therefore, it would be advantageous to generate signals with a low-frequency oscillator and a frequency multiplier if an inexpensive, low-power-dissipation Manuscript received February 15, 2008. Manuscript revised June 18, 2008. † The authors are with NTT Corporation, Yokosuka-shi, 2390847 Japan. a) E-mail: [email protected] DOI: 10.1093/ietele/e91–c.11.1744

frequency multiplier could be developed. To use a harmonic mixer [3] and an oscillator at a low frequency, such as 3 GHz, a quadrupler that changes 3-GHz signals to 12-GHz signals is needed. Frequency multipliers usually output spurious frequency components. To suppress these components, balanced structures [4], [5] or filters are often used. A balanced doubler consumes twice as much power as a single-end doubler because it needs two active devices. An external filter increases the size and cost, so a monolithic filter is desirable. Some monolithic band pass filters have been proposed [6]–[8]. Unfortunately, despite efforts to miniaturize them, they are still too large. A frequency doubler MMIC with an open stub filter has also been proposed [9]. An open stub is constructed with a λ/4 line, which is too big for use in an MMIC. Methods of shortening λ/4 lines have been proposed [10]. The resulting lines are small and can eliminate the fundamental frequency component and pass the second harmonic component, which is the desired output frequency component for a frequency doubler. However, they cannot eliminate the third harmonic component, which is one of the nearest spurious components to the desired component. To suppress these components, the authors have proposed a very small 2-band elimination filter [11]. Frequency multipliers usually require driver amplifiers. Because increasing the number of chips increases assembly cost, a higher degree of integration is needed. Yield is also an important factor in reducing cost. Multipliers should generate constant output power even when input power undergoes changes. This requires a margin at the level diagram, which usually requires more circuit blocks. NTT also developed three-dimensional MMIC (3D-MMIC) technology [12]. Figure 1 shows the basic structure of the 3D-MMIC. Devices are formed on a substrate using a standard fabrication process. The upper polyimide layers are used for

Fig. 1

Basic structure of 3D-MMIC.

c 2008 The Institute of Electronics, Information and Communication Engineers Copyright

YAMAGUCHI et al.: A VERY LOW SPURIOUS X-BAND FREQUENCY QUADRUPLER

1745

passive circuitry. This technology significantly miniaturizes MMICs. Thin-film microstrip (TFMS) lines are formed on the structures that have both ground planes and signal lines on the substrate. In general, the lines are sufficiently isolated when the line spacing is three times wider than the spacing between the lines and ground planes. Because the spacing between the lines and ground planes of the TFMS lines is around 10 μm, which is about one-tenth of the spacing between the ordinary microstrip lines and ground planes, TFMS lines can be arranged in one-tenth of the spacing of ordinary microstrip lines. Multi-layer lines on multi-layer dielectric films can make up a very compact multi-layer inductor [13], which contributes greatly to integration because inductors often occupy the majority of the circuit area at microwave frequencies. The authors proposed a highly integrated frequency quadrupler 3D-MMIC [14], which has a high degree of integration, provides constant output power under low input power, and sufficiently suppresses spurious frequency components. This technology can help reduce the cost of quasimillimeter band wireless terminals. In this paper, we discuss the quadrupler 3D-MMIC in detail. 2.

3-GHz spacings. It is difficult to suppress spurious components that are 3-GHz away at a quasi-millimeter wave band. However, it is easier to suppress spurious components that are 3-GHz away at a lower microwave band. Therefore, the 2-band elimination filter is allocated after the first doubler. The interstage driver amplifiers drive the second frequency doubler, which changes 6-GHz signals to 12-GHz signals. The output driver amplifier outputs 5-dBm signals. Each circuit is designed below. 2.2 Frequency Doublers If a doubler is operated at a low input power, fewer driver amplifiers are required. We used active doublers because passive ones require a lot of input power. Figure 3 is a schematic configuration of the doubler, which consists of a GaAs pHEMT. Its bias point is around the threshold voltage, which offers low power consumption and strong nonlinearity. The doubler needs an input power of only 0 dBm. To reduce the chip size, the port that supplies the gate bias was isolated from the RF signal by resistors. Also to reduce its size, the inductors were constructed with multilayer lines.

MMIC Design 2.3 2-Band Elimination Filter

2.1 Block Diagram of the MMIC The quadruple multiplied signal can be generated either by a frequency quadrupler or by two frequency doublers. The conversion loss of a frequency quadrupler is generally greater than that of a frequency doubler. A frequency quadrupler usually requires more additional amplifiers than two doublers, and the power consumption of an amplifier is usually larger than that of a doubler. Moreover, a quadrupler requires a higher performance filter than a doubler because passing 4 fin and eliminating 3 fin and 5 fin is more difficult than passing 2 fin and eliminating fin and 3 fin . As a high performance filter is generally larger than a low performance filter. Therefore, the two-doubler configuration was selected. A block diagram of the MMIC is shown in Fig. 2. It consists of 7 circuits: an input driver amplifier, a frequency doubler that changes 3-GHz signals to 6-GHz signals, a 2band elimination filter, two interstage driver amplifiers, a frequency doubler that changes 6-GHz signals to 12-GHz signals, and an output driver amplifier. The output power of an ordinary oscillator is not large enough to drive a frequency doubler. The input driver amplifies input signals so that the signals can drive the first frequency doubler. The doubler changes 3-GHz signals to 6-GHz signals. Its output signals have spurious components that are arranged in

Fig. 2

Block diagram of proposed MMIC.

A doubler generates spurious frequency components. The nearest ones are generated at a 3-GHz offset from the desired component when the frequency of the oscillator is 3 GHz. Those spurious components must be suppressed because the 3-GHz offset undesired signal is too near the desired signal in the quasi-millimeter band. We developed a miniaturized 2-band elimination filter suitable for use as a frequency doubler MMIC. The filter eliminates the spurious components nearest to the desired component, fundamental frequency, and third harmonic components but passes the second harmonic component, which is the desired output component. Figure 4 shows the basic configuration of the proposed 2-band elimination filter. It consists of lumped capacitors and stubs whose parameters can be easily set using equations. The filter is designed as follows when the fundamental, second harmonic, and third harmonic frequencies are fin , 2 fin , and 3 fin , the line impedances of S 1 and S 2 are Z1 and Z2 , and the electrical lengths of S 1 and S 2 at fin are θ1 (0 < θ1 < π/2) and θ2 (0 < θ2 < π/2), respectively. C1 = 1/2π fin Z1 tan θ1 , C2 = 1/2π fin Z2 tan θ2 ,

Fig. 3

Configuration of doubler.


1746

Fig. 5

Side view of an MIM capacitor isolated from a signal line.

1 j2π2 finCt Zfil (3 fin ) = 1 ZA1 (3 fin ) + j2π2 finCt 1 + jZ2 tan 3θ2 C2C22 j2π3 fin C2 + C22 = Z2 · 1 Z2 + tan 3θ2 C2C22 2π3 fin C2 + C22 1 j2π3 finCt = 0. · 1 ZA1 ( fin ) + j2π3 finCt ZA1 (3 fin ) ·

Fig. 4

Basic configuration of 2-band elimination filter.

C21 = C1 (3 − 6 tan2 θ1 − tan4 θ1 )/24, C22 = C2 tan θ2 /(3 tan 3θ2 − tan θ2 ), Ct = j/(4π fin Zt ), where Zt is the total impedance of S 1 , S 2 , C1 , C2 , C21 at 2 fin . At fin , ZB1 ( fin ), which is the total impedance of S 1 and C1 at point B, is given by 1 + jZ1 tan θ1 j2π finC1 = 0. ZB1 ( fin ) = Z1 · 1 Z1 + tan θ1 2π finC1 Therefore, when the total impedance of S 1 , S 2 , C1 , C2 , C21 at point A is ZA1 ( fin ), the total impedance of the filter, Z f il ( fin ), is 1 j2π2 finCt Zfil ( fin ) = 1 ZA1 ( fin ) + j2π2 finCt 1 + jZ2 tan θ2 j2π finC2 = Z2 · 1 Z2 + tan θ2 2π finC2 1 j2π2 finCt = 0. · 1 ZA1 ( fin ) + j2π2 finCt ZA1 ( fin ) ·

Hence, the filter eliminates the fin component. At 3 fin , ZB2 (3 fin ), which is the total impedance of the S 1 , C1 and C21 at point B, is given by 1 j2π3 finC21 ZB2 (3 fin ) = 1 ZB1 (3 fin ) + j2π3 finC21 1 ZB2 (3 fin ) · j2π3 finC21 = ∞. = 0 Therefore, the total impedance of the filter, Z f il (3 fin ), is ZB1 (3 fin ) ·

Hence, the filter also eliminates the 3 fin component. At 2 fin , the total impedance of the filter, Z f il (2 fin ), is 1 1 Zt · j2π2 finCt j2π2 finCt = ∞. Zfil (2 fin ) = = 1 0 Zt + j2π2 finCt Zt ·

Hence, the filter passes the 2 fin component. The stubs were constructed using thin film microstrip (TFMS) lines. C1 and C2 were set to 3.9 pF, which occupies a lot of space. To reduce the chip size, these large capacitors, were fabricated under the ground plane and isolated from the stubs, S 1 and S 2 , using 3D-MMIC technology, as shown in Fig. 5. 2.4 Amplifiers A schematic configuration of the input driver amplifier at 3 GHz is shown in Fig. 6(a). To reduce the chip size, it uses a common gate HEMT as its input matching circuit and a resistor as its load. As interstage amplifiers, we used two negative feedback amplifiers. A schematic configuration of the negative feedback amplifier is shown in Fig. 6(b). The second interstage driver amplifier is operated around the saturation point and can adsorb fluctuations in the intensity of the signal. A schematic configuration of the output driver amplifier is shown in Fig. 6(c). It uses spiral inductors as its load, which helps maximize output power and reduce chip size.


1747

Fig. 7

Measured characteristics of input driver amplifier.

Fig. 8

Measured output components of first doubler.

Fig. 6 Configurations of driver amplifiers. (a) Input driver amplifier. (b) Interstage driver amplifier. (c) Output driver amplifter.

3.

Results

Figure 7 shows the measured characteristics of the input driver amplifier. Its gain is 11 dB ± 0.5 dB, and its input return loss is −10 dB ± 1 dB at 2.1 to 3.8 GHz. Its drain current is 25 mA. The first doubler converts the input signal of the 3-GHz band to the output signal of the 6-GHz band. Figure 8 shows its measured output components when a 2.95-GHz signal is input. Its conversion loss of the second harmonic component, f2 , is 6 dB at an input power of 5 dBm. The fundamental component, f1 , and the third harmonic component, f3 , are 9 dB and 27 dB less than f2 , respectively. The doubler’s drain current is only 3 mA at an input power of 0 dBm. Figure 9 shows the measured characteristics of the 2band elimination filter. It passes the desired signal at 6 GHz and suppresses the nearest undesired signals at 3 GHz and 9 GHz. Its insertion loss is 3 dB at 6 GHz. Meanwhile, its insertion losses are 13 dB at 3 GHz and 9 GHz. The filter had adequate performance but it was not excellent. The cause of the degradation was residual impedance mismatch. Figure 10 shows the measured characteristics of the interstage driver amplifier. It has a gain of 6 dB in the 6-GHz band and no gain in the 3-GHz band and 9-GHz band. Its

Fig. 9

Measured characteristics of 2-band elimination filter.

saturation power is 4 dBm. Because the 2-stage amplifier consists of this amplifier, the second stage amplifier is operated around the saturation point. It causes a constant 4-dBm input power to be provided to the second doubler. Its drain current is 7 mA. The second doubler converts the input signal of the 6GHz band to the output signal of the 12-GHz band. The input signal from the interstage driver amplifiers is around 4 dBm in the MMIC and its gate voltage is set a little lower than the pinch off voltage. Its drain current is only 3 mA at an input power of 4 dBm. Its drain current is only 3 mA at an input power of 4 dBm. Figure 11 shows its measured output components when a 5.8-GHz signal is input. Its conversion loss of the second harmonic component, f2 , is 8 dB at an input power of 4 dBm. The fundamental component, f1 , and the third harmonic component, f3 , are 3 dB and 24 dB less


1748

Fig. 12

Measured characteristics of output driver amplifier.

Fig. 10 Measured characteristics of interstage driver amplifier. (a) S-parameter. (b) Input-output characteristics.

Fig. 11

Measured output components of second doubler.

than f2 , respectively. Because the 6-GHz band signal, f1 , is 6-GHz away from the desired signal at 12 GHz, it can be easily suppressed and the output driver amplifier does not amplify the signal at 6 GHz. Figure 12 shows the measured characteristics of the output driver amplifier. Its gain is 10 dB ± 0.5 dB between 11.2 and 13.0 GHz. Meanwhile, its gain is −19 dB at 6 GHz, which is the highest spurious output component frequency of the second doubler. The output return loss of the output driver amplifier is below −10 dB between 11.2 and 15.2 GHz. Its drain current is 8 mA. Figure 13 shows a photograph of the fabricated quadrupler 3D-MMIC. Large capacitors, such as 5-pF capacitors, are located under the ground planes. Their total capacitance and area is 83 pF and 0.23 mm2 , respectively. This area is

Fig. 13

Photograph of fabricated MMIC.

Fig. 14

Measured return loss of MMIC.

10% of the total area of the MMIC. There are 11 stacked inductors and their total area is 0.13 mm2 , which is one third of the area when they are replaced by single layer inductors. TFMS lines can be arranged in one-tenth of the spacing of ordinary microstrip lines. They can be bent with narrow line spacing. This significantly miniaturizes the MMIC. The MMIC integrates circuits on only 2.25 mm × 1.05 mm area. Figure 14 shows the measured return loss of the developed MMIC. Its input port is matched well at 3 GHz, and its output port is matched well at 12 GHz. Figure 15 shows the measured output components of the MMIC when a 2.95-GHz signal is input. The fourth harmonic component, 4 fin , which is the desired output component, is constantly 5 dBm when the input signal level is more than −10 dBm. The third harmonic component, 3 fin ,


1749

4.

Fig. 15

Measured output components of MMIC.

Conclusion

A highly integrated X-band frequency quadrupler with driver amplifiers using 3D-MMIC technology was presented. It consists of four amplifiers, two doublers, and a 2band elimination filter, which are integrated in a 2.36 mm2 area. The nearest spurious components of the MMIC are well suppressed. The desired/undesired ratio is about 40 dB. The MMIC supplies +5 dBm of the desired component at an input power as low as −10 dBm and requires no external buffer amplifiers. The power dissipation of the MMIC is only 160 mW. This MMIC will help reduce the cost of equipment for quasi-millimeter FWA systems. Acknowledgments

Fig. 16

Measured output spectrum of the MMIC.

Table 1

Frequency multiplier MMIC performance.

and the fifth harmonic component, 5 fin , which are the nearest spurious components, are adequately suppressed. The 4 fin /3 fin and 4 fin /5 fin ratios are 42 dB and 46 dB, respectively, at an input power of −10 dBm. The power dissipation of the MMIC is about 160 mW (3 V, 53 mA) at an input power of −10 dBm. Figure 16 shows the measured output spectrum of the MMIC when the input frequency is 2.95 GHz and the input power is −10 dBm. It shows that the maximum intensity component is the desired component, 4 fin , and the nearest spurious components, 3 fin and 5 fin , are suppressed. The performance of this MMIC and other frequency multiplier MMICs [4], [5], [9], [15] are compared in Table 1. This MMIC integrates quite a large number of circuits, seven circuits, on a chip only 2.36 mm2 and requires no external buffer amplifiers. It has a higher desired/undesired ratio, higher conversion gain, and higher degree of integration and requires lower input power than other MMICs.

The authors thank Dr. S. Kubota, Prof. M. Umehira, and Mr. K. Inoue for their encouragement throughout this work. They also thank Dr. T. Nakagawa, Dr. K. Nishikawa, Dr. T. Tokumitsu, Mr. Y. Shindo, Mr. T. Yoshie, Mr. T. Taniguchi, Mr. T. Shirosaki, Mr. Y. Toriyama, and Mr. S. Nagamine for their fruitful discussions and comments on the work. References [1] K. Nidaira, T. Sirouzu, M. Baba, and K. Inoue, “Wireless IP access system for broadband access services,” IEEE Int. Conf. Commun., vol.6, pp.3438–3438, June 2004. [2] S. Chartier, J. Dederer, B. Schleicher, and H. Schumacher, “Millimeter-wave Si/SiGe HBT frequency divider using dynamic and static division stages,” 2007 Asia Pacific. Microwave Conf. Dig., pp.1313–1316, Dec. 2007. [3] H. Okazaki and Y. Yamaguchi, “Wide-band SSB subharmonically pumped mixer MMIC,” 1997 IEEE MTT-S Int. Microwave Symp. Dig., pp.1035–1038, June 1997. [4] K. Nishikawa, B. Piernas, T. Nakagawa, and K. Araki, “Miniaturized and broadband V-band balanced frequency doubler for highly integrated 3-D MMIC,” 2002 IEEE MTT-S Int. Microwave Symp. Dig., pp.351–354, June 2002. [5] D. Kang, D. Baek, S. Jeon, J. Park, and S. Hong, “A miniaturized K-band balanced frequency doubler using InGaP HBT technology,” 2003 IEEE MTT-S Int. Microwave Symp. Dig., pp.107–110, June 2003. [6] T. Weller and L. Katehi, “Miniature stub and filter designs using the microshield transmission line,” 1995 IEEE MTT-S Int. Microwave Symp. Dig., pp.675–678, June 1995. [7] I. Totoda, T. Tokumitsu, and K. Nishikawa, “A multilayer MMIC filter using short-line meshes (SLMs),” 24th European. Microwave Conf. Dig., pp.443–447, Sept. 1994. [8] K. Hettak, N. Dib, A. Omar, G. Delisle, M. Stubbs, and S. Toutain, “A useful new class of miniature CPW shunt stubs and its impact on millimeter-wave integrated circuits,” IEEE Trans. Microw. Theory Tech., vol.47, no.12, pp.2340–2349, Dec. 1999. [9] Y. Shizuki, Y. Fuchida, F. Sasaki, and S. Watanabe, “A K-band MMIC frequency doubler using resistive series feedback circuit,” IEICE Trans. Electron., vol.E83-C, no.5, pp.759–766, May 2000. [10] T. Hirota, A. Minakawa, and M. Muraguchi, “Reduced-size branchline and rat-race hybrids for uniplanar MMICs,” IEEE Trans. Microw. Theory Tech., vol.38, no.3, pp.270–275, March 1990. [11] Y. Yamaguchi, T. Nakagawa, and K. Araki, “A frequency doubler


1750

[12]

[13]

[14]

[15]

MMIC with a small 2-Band elimination filter,” 2004 IEEE Compound Semiconductor IC Symp. Dig., pp.268–271, Oct. 2004. K. Nishikawa, B. Piernas, T. Nakagawa, K. Araki, and K. Cho, “Vband fully-integrated TX/RX single-chip 3-D MMICs using commercial GaAs pHEMT technology for high-speed wireless applications,” 2003 IEEE GaAs IC Symp. Dig., pp.97–100, Nov. 2003. T. Kaho, M. Sasaki, Y. Yamaguchi, K. Nishikawa, and K. Uehara, “Miniaturized multilayer inductors on GaAs three-dimensional MMIC,” 2007 Korea-Japan Microwave Conf Dig., pp.149–152, Nov. 2007. Y. Yamaguchi, T. Kaho, and K. Uehara, “A highly integrated X-band frequency quadrupler MMIC using 3D-MMIC technology,” 2007 IEEE RF IC Symp. Dig., pp.757–760, June 2007. F. Giannini, E. Limiti, A. Serino, and M. Feudale, “Broadband monolithic active frequency doubler for X-band satellite communication system,” Proc. 31st European Microwave Conf., pp.303–306, Sept. 2001.

Yo Yamaguchi received the B.S. and M.S. degrees in chemistry, from Osaka University, Osaka, Japan, in 1989, and 1991, respectively. In 1991, he joined NTT Radio Communication Systems Laboratories, Yokosuka, Japan, where he was engaged in research and development on MMIC’s. From 1999 to 2001, he was an Associate Manager at STE Telecommunication Engineering Co., Ltd., where he served as a Technical Consultant on wireless communications. Since 2001, he has been a Senior Research Engineer at NTT Network Innovation Laboratories, Yokosuka, Japan. He is currently involved in the design of MMICs. Mr. Yamaguchi is a member of the Japan Society of Applied Physics.

Takana Kaho received the B.S. and M.S. degrees in physics from Tokyo Metropolitan University, Japan, in 1994 and 1996, respectively. She received the Dr.Eng. degree in communication engineering from Tokyo Institute of Technology, Japan, 2007. She joined the NTT Radio Communication Systems Laboratories, Yokosuka, Japan, in 1996. She is currently involved in the design of quasi-millimeter-wave transceivers for fixed wireless access systems. She received the Japan Microwave Prize in 1998 Asia Pacific Microwave Conference, and the Young Researchers’ Award in 2004 presented by IEICE.

Kazuhiro Uehara was born in Tokyo, Japan, on April 30, 1963. He received the B.E., M.E., and Ph.D. degrees from Tohoku University, Sendai, Japan, in 1987, 1989, and 1992, respectively. He joined Nippon Telegraph and Telephone Corporation (NTT) in 1992 and was engaged in the research of array antennas, active antennas, and indoor propagation in millimeterwave and microwave frequency bands. From 1997 to 1998, he was a Visiting Associate at the Department of Electrical Engineering, California Institute of Technology, CA. From 2003 to 2008, he was a Part-time Lecturer at the Department of Electrical Engineering, Tohoku University. He is currently a Senior Research Engineer, Supervisor at NTT Network Innovation Laboratories, where he engages in the research and development of software defined radio and cognitive radio systems. He is currently serving as Vice-Chair of Technical Committee on Software Radio, IEICE Communication Society from May 2005. He received the Young Engineer Award and the Excellent Paper Award from the IEICE, the 1st Yokosuka Research Park (YRP) Award, and the 18th Telecom System Technology Award from the Telecommunications Advancement Foundation, Japan, in 1995, 1997, 2002, and 2003 respectively.