A Wide Dynamic Range CMOS Image Sensor With ... - IEEE Xplore

IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 40, NO. 12, DECEMBER 2005

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A Wide Dynamic Range CMOS Image Sensor With Multiple Exposure-Time Signal Outputs and 12-bit Column-Parallel Cyclic A/D Converters Mitsuhito Mase, Shoji Kawahito, Senior Member, IEEE, Masaaki Sasaki, Member, IEEE, Yasuo Wakamori, and Masanori Furuta, Member, IEEE

Abstract—A wide dynamic range CMOS image sensor with a burst readout multiple exposure method is proposed. In this method, maximally four different exposure-time signals are read out in one frame. To achieve the high-speed readout, a compact cyclic analog-to-digital converter (ADC) with noise canceling function is proposed and arrays of the cyclic ADCs are integrated at the column. A prototype wide dynamic range CMOS image sensor has been developed with 0.25- m 1-poly 4-metal CMOS image sensor technology. The dynamic range is expanded maximally by a factor of 1791 compared to the case of single exposure. The dynamic range is measured to be 19.8 bit or 119 dB. The 12-bit ADC integrated at the column of the CMOS image sensor has DNL of 0.2/ 0.8 LSB.

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Index Terms—Burst readout multiple exposure, column-parallel cyclic A/D converter, wide dynamic range.

I. INTRODUCTION

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AMERAS for automobile, scientific, and industrial applications often require very wide linear dynamic range with consistently high signal-to-noise ratio (SNR) in the whole illumination range. CMOS image sensors are expected to be used for such applications. Numerous methods to expand the dynamic range of the CMOS image sensor have been reported. The methods can be classified into two categories. One uses nonlinear response of the pixel devices or circuits. The use of logarithmic response [1], the combination of linear and logarithmic responses [2], and well capacity adjusting [3] are well known. The other group uses two or more exposure time signals to expand the dynamic range. A dual sampling method using the difference of the signal readout timing [4], and a multiple sampling technique using an in-pixel analog-to-digital conversion (ADC) [5] have been reported. Since most applications require low-noise high-sensitivity characteristics in imaging of the dark region as well as dynamic range expansion to the bright region, the availability of a low-noise high-sensitivity pixel device with Manuscript received April 19, 2005; revised August 3, 2005. This work was supported by the Knowledge Cluster Initiative of Ministry of Education, Culture, Sports, Science and Technology. M. Mase is with Shizuoka University, Hamamatsu 438-8011, Japan (e-mail: [email protected]). S. Kawahito and M. Furuta are with the Research Institute of Electronics, Shizuoka University, Hamamatsu 432-8011, Japan. M. Sasaki is with the Department of Information and Communication Engineering, Sendai National College of Technology, Sendai 989-3128, Japan. Y. Wakamori is with the LSI Development Department Semiconductor Division, Yamaha Corporation, Iwata, Shizuoka 438-0192, Japan. Digital Object Identifier 10.1109/JSSC.2005.858477

pinned photodiode structure [6]–[9] is particularly important. The dynamic range expansion methods with nonlinear response of the pixel are not compatible with the pinned photodiode structure. The latter group of the methods using two or more exposure time signals usually allows us to use the pinned photodiode structure in the pixel. The dual sampling is a simple and useful technique for dynamic range expansion. Recently, a pinned photodiode CMOS image sensor with an optional function of dynamic range expansion using the dual sampling technique has been developed [10]. The dual sampling, however, may not be sufficient to represent the areas of the scene that are too dark to be captured by the short exposure time signals and too bright to be captured by the long exposure time signals if the required dynamic range is larger than 100 dB. A sophisticated wide dynamic range CMOS image sensor using a multiple sampling technique and in-pixel ADC has been developed and the digital dynamic range of 16 bit (65536:1) has been achieved [5]. An improved version with the in-pixel ADC has 100 dB dynamic range [11]. However, the in-pixel ADC requires six transistors in each pixel. This paper presents a new type of wide dynamic range image sensor with multiple exposure time signals. Our method uses high-speed signal readout mode in CMOS image sensors, and maximally four different exposure time signals are read out within one frame period. The read image signals are synthesized in the external system. This method provides many advantages for high-quality wide dynamic range imaging at the expense of complexity of an external system and frame memories. First, the image capturing conditions such as the number of different exposure times and the choice of each exposure time can be flexibly controlled in real time. Second, the four different exposure times are sufficient for expanding the dynamic range to 120 dB while maintaining a sufficient image quality. Any type of pixel devices and circuits can be used, and therefore, a CMOS image sensor with low-noise characteristics as well as wide dynamic range can be realized if the device technology of the pinned photodiode is available. Furthermore, the image can be treated as a very wide linear digital data. This property is particular important if the wide dynamic range image is used for image recognition in real-world applications such as automobile, biometrics, and security systems. As a key device for reading four different exposure time signals in one frame period with sufficient image quality, this paper introduces a new type of column-parallel cyclic ADC with 12-bit resolution. A two-stage cyclic ADC has been used

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Fig. 1. Accumulation and readout timing of the burst readout method.

for the column integration in a wide dynamic range image sensor using the well capacity adjusting method [3]. However, in the configuration of [3], the column ADC with a noise canceller needs three operational amplifiers and the accuracy was limited to 9 bits. The proposed cyclic ADC with a built-in pixel noise canceller uses a single operational amplifier per column. This compact configuration allows us to integrate the array of the ADC at the column of the 1/2-inch VGA-size CMOS image sensor. The technique of wide dynamic range imaging is described in Section II. The imager design is discussed in Section III. Measured results from the implemented prototype CMOS image sensor are presented in Section IV.

II. DYNAMIC RANGE EXPANSION METHOD The proposed burst readout multiple exposure (BROME) method is based on the image readout timing shown in Fig. 1. In the burst readout method, the unit frame image signal is read as shown in Fig. 1. In the figure, LA out within a fraction of and LR denote the terms of signal accumulation and readout, respectively. In conventional CMOS image sensors, one frame image signal is read out in whole frame period . In the burst readout method, one frame image signal is read out in time , is which is a fraction of the frame period. The ratio denoted by , and is chosen as a positive integer. The signal accumulation and readout timing of the BROME is shown in and , where is the number of Fig. 2 for different accumulation-time signals. Fig. 2 is a conceptual diagram. It is assumed that the sensor has five vertical pixels. One long and three short accumulation-time signals are read out in a frame period. The long, short, very short, and extremely short accumulation times are denoted by LA, SA, VSA, and ESA, for signal respectively. The LA signals occupy three slots accumulation. Using the time slots for reading the LA signals, the SA signals are accumulated. The VSA and ESA signals are accumulated using the time slots for reading the SA and VSA signals, respectively. The accumulation time of the SA, VSA, and ESA signals can be controlled to be shorter than by resetting the pixel during accumulation using an additional vertical scanner for resetting. The dynamic range expansion ratio is determined by the ratio of long accumulation time and the shortest accumulation time. The long accumulation time is given by (1)

Fig. 2. Accumulation and readout timing of the wide dynamic range CMOS image sensor.

and the minimum accumulation time

is given by (2)

represents the number of vertical pixels, and where is the reset pulse width. Therefore, the minimum accumulation time can be set to a value which is a little shorter than the horizontal readout period. The maximum dynamic range expansion ratio is given by (3) In the design of a VGA-size image sensor with , and , and , the dynamic range is expanded by a factor of 1791 or 65.1 dB. When compared with the image sensor without the multiple exposures, the longest exposure time is reduced by half in the and . Therefore, the minimum illuminacase of tion level in which the signal-to-noise ratio becomes 1 is doubled. However, the actual dynamic range expansion ratio when compared with the single exposure case becomes 65.1 dB if the noise level is the same. An advantage of the wide dynamic range CMOS image sensor with the multiple exposure method is that a relatively high SNR is kept in the whole illumination range. In the dual sample method, which reads one long and one short accumulation-time signal in one frame period, the SNR dip at the boundary of the high and low illumination regions increases as the time ratio of long to short exposures increases [12]. If the noise level is dominated by photon shot noise, the SNR dip is given when the accumulation time is switched from to by (4) In the proposed method, by choosing each accumulation time ratio of LA to SA, SA to VSA, and VSA to ESA to be minimum, the SNR dip can be sufficiently reduced at each boundary. For example, assuming that the dynamic range expansion ratio is

MASE et al.: A WIDE DYNAMIC RANGE CMOS IMAGE SENSOR WITH MULTIPLE EXPOSURE-TIME SIGNAL OUTPUTS

Fig. 3.

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SNR dip in dual exposure.

Fig. 5. Dual vertical shift register.

Fig. 4. Block diagram of the proposed wide dynamic range CMOS image sensor.

1000, and , the best choice for each accumulation time ratio is 10, and the ideal SNR dip is 10 dB. In the case of the dual sampling, the SNR dip will be 30 dB for the dynamic range expansion ratio of 1000. Fig. 3 shows the SNR as a function of photo current in the dual sampling method for the case that the conversion gain is 32 V/electron , the read noise is 10 electrons, the saturation level is 40 000 electrons, the long exposure time is 33.3 ms, and the ratio of the long to the short accumulation time is 1000. The SNR dip in this case is 37.8 dB, which is larger than 30 dB because of the influence of the read noise. In the proposed wide dynamic range image sensor, the image capturing conditions of wide dynamic range image can be flexibly and adaptively changed to the scene. The image capturing conditions include the number of different accumulation-time and each accumulation time. The short accumusignals lation time can be chosen from 1/2, 1/4, 1/8, 1/16, 1/32, 1/96, in the present design. 1/256, and 1/597 of The number of exposures is determined, for example, by checking if there are saturation pixels in each exposure time signal. If there is no saturation pixel in the long exposure signal, there is no need to capture short exposure signals. Similarly, if

Fig. 6.

Reset timing of a pixel.

there is no saturation pixel in the short exposure signals, a very short exposure signal is not necessary. Therefore, the simplest way to determine the number of exposures is to check if there are saturation pixels in each pixel. For example, if there are saturation pixels in the short exposure time image, and there is no saturation pixel in the very short exposure time, the best number of exposures is obviously three. Increasing the number of exposures leads to the smaller SNR dip for a large dynamic range expansion. However, it also leads to the reduction of the longest accumulation time, the resulting reduction of the sensitivity, and the increase of the power consumption. Therefore, the best image capturing conditions must be chosen adaptively to the scene.

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Fig. 7.


Schematic of the cyclic ADC.

III. IMAGE SENSOR DESIGN A. Architecture Fig. 4 shows a block diagram of the wide dynamic range CMOS image sensor. The upper and lower ADC arrays are for odd and even columns, respectively. The implemented wide dynamic range CMOS image sensor has two vertical shift registers for signal readout and resetting. The schematic and timing diagrams of the dual vertical shift register are shown in Figs. 5 and 6, respectively. The timing diagram of Fig. 6 shows the case that the sensor has five vertical pixels and three accumulation signals are read out. Trigger pulses VTRG1 and VTRG2 are used for the signal readout and resetting, respectively. The both shift regis. The reset pulsewidth and ters are operated by a clock pulse is a the actual timing are determined by a pulse RR. In Fig. 6, frame period, is readout time, and , , and are the accumulation times for the long, short, and very short, respectively. The accumulation time is determined by the internal of the adjacent VTRG1 pulses if the VTRG2 pulse is not given. is equal to multiple of , is equal to , In Fig. 6, is determined by the interval between the VTRG2 and pulse and the next VTRG1 pulse.

Fig. 8. Timing diagram of the cyclic ADC.

B. Column-Parallel Cyclic ADCs A schematic of the cyclic ADC with a built-in noise canceller is shown in Fig. 7. It consists of an amplifier, six capacitors, two comparators, and switch transistors. This ADC works as an ADC with 1.5-bit/cycle algorithm [13]. A straightforward cyclic ADC consists of sample-and-hold and gain stages [14]. A noise canceller is necessary in front of the ADC. Therefore, the conventional method requires three amplifiers. In the proposed method, an amplifier and capacitors are shared for the noise canceller, the sample and hold and 1.5-bit gain stages. The power dissipation and the size can be sufficiently small for the column integration. A timing diagram of the cyclic ADC is shown in Fig. 8. Fig. 9 depicts the equivalent circuits for the operation of the pixel noise canceling. In the signal sampling phase of the noise cancellation

Fig. 9. Equivalent circuits for the noise cancelation mode. (a) Signal sampling. (b) Reset sampling.

mode, the signal level of the pixel output is connected to and , and a reference the bottom plates of capacitors is connected to the bottom plates of capacitors signal and . The bottom plates of capacitors and are


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Fig. 12. Equivalent circuits for the cyclic ADC mode. (a) Sampling. (b) Amplification. Fig. 10. Relationship between input and output ranges in the noise cancelation mode of the ADC.

Fig. 11.

Residue plots of the 1.5-bit/cycle ADC.

connected to reference signals and , respectively. The switches controlled by , , , , and are turned on in the signal sampling phase. The signal level is sampled when and are turned off. In the the switches controlled by reset sampling phase, the reset level of the pixel output is given to and . After that, the switch controlled by is turned on, and the bottom plates of and are connected to the amplifier output. The reset level is sampled are turned off. After when the switches controlled by and these operations, the differential output is given by (5) , and . By choosing all capacitors are equal, the is amplified by a factor of 2. In order difference to fit the amplified signal to the full scale, the reference voltage is subtracted from the output. As a result, the relationship and is as shown in Fig. 10. between At the beginning of the cyclic ADC mode, the amplifier output is sampled by the two comparators in a sub-ADC and and . To do this, the switches controlled the capacitors are turned off, and the switches controlled by and by are turned on. Fig. 11(a) shows an ideal residue plot of the 1.5-bit cyclic ADC. In the 1.5-bit/cycle algorithm, a signed digit set is used. The signed digit values 1, 0, and 1 correspond to the comparator output codes and , respectively. Fig. 11(b) shows an actual case of the residue plot if an offset exists in the lower . If there exists comparator for comparing the input with in the lower comparator, the switching points an offset of where

between and will be shifted to from . As a result, the amplifier output takes different value from the case without comparator offset. An important property of the 1.5-bit/cycle algorithm is that the comparator can be corrected in offset up to (1/4) digital domain [15]. This property of the 1.5-bit/cycle algorithm greatly relaxes the comparator precision and leads to a great reduction of power dissipation of comparators. In the amplification phase, as shown in Fig. 12(b), the bottom and are connected to a 1.5-bit plates of the capacitors DAC using the decision results of the comparators. To do this, are turned on, the switches conthe switches controlled by and are turned off. Then the relationship betrolled by tween the input and output of the -th cycle of the ADC is given by

(6) is the sub-ADC output and where and the th cycle. If to

is the output of , (6) is simplified (7)

The th sub-ADC output

is given by

if (8) if if . The comparator reference voltages and are chosen such that . For 12-bit resolution, the above operation is repeated 11 times. Fig. 13 shows the schematic of the internal amplifier [16]. The designed internal amplifier has open-loop gain of 87 dB, phase margin of 64 degrees, and unity gain frequency of 40 MHz. Since the dominant pole is located at the amplifier output, the compensation to stabilize the amplifier is done by connecting the sampling capacitor at the output. The common-mode of the internal amplifier is controlled by a technique of common-mode feedback using two capacitors and several switches [16]. The switching operation of the common-mode feedback is performed before the noise canceling mode is started. The designed cyclic ADC dissipates 149 W at supply voltage of 3.3 V and clock frequency of 3.75 MHz. For 12-bit resolution, the conversion time is 2.9 s. This speed is sufficient for the designed VGA-size wide dynamic range image sensor

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Fig. 13.


Schematic of the internal amplifier.

Fig. 14. Chip microphotograph.

in which the readout speed is 6 times faster than that of the conventional VGA-size video rate (30 frame/s) image sensor. The horizontal read time is 11.2 s including the times for the noise cancellation, the A/D conversion, and horizontal data scanning. IV. EXPERIMENTAL RESULTS A prototype wide dynamic range CMOS image sensor which has outputs of maximally four different exposure-time signals in one frame is designed and implemented. A chip microphotograph of the developed wide dynamic range image sensor with 0.25 m 1-poly 4-metal CMOS image sensor technology is shown in Fig. 14. The image array has 664 448 pixels with m m. The chip size is 8.34 mm the pixel size of 9.84 mm. Two sets of a 332 cyclic ADC array are integrated

Fig. 15. Component image to synthesize a wide dynamic range image. (a) Long accumulation time image. (b) Short accumulation time image. (c) Very short accumulation time image. (d) Extremely short accumulation time image.

at the upper and lower sides of the image array. The references of the ADC array are driven by an external reference generator. The power consumption of the external reference generator is 15 mA. This amount of drive current is not optimized, and so it may be further reduced.


Fig. 16.

Synthesized wide dynamic range image.

Fig. 17.

Sensor linearity.

Fig. 15(a)–(d) shows component images whose accumula, , and , respection time is set to tively, captured at 20 frames/s. A synthesized image is shown in Fig. 16. The filament of a bulb and the relatively dark illumination region of right side are simultaneously captured without saturation. The wide dynamic range image signal is synthesized in an external system. The required memory size to synthesize the wide dynamic range image is at least that for one frame. This is because the wide DR image can be synthesized by repeating the reading of temporal image stored in a frame memory and the restoring the synthesized intermediate image to the same frame memory. Fig. 17 shows the linearity of the image sensor outputs. The are 1/2, 1/4, 1/8, 1/16, short accumulation times as a unit of 1/32, 1/96, 1/256, and 1/597, respectively, and the long accumulation-time signal is 3. All the accumulation-time signals have sufficient linearity. The SNR characteristic of the developed wide dynamic range CMOS image sensor is measured as shown in Fig. 18. In this case, the accumulation-time ratios of long (LA) to short (SA), very short (VSA), and extremely short (ESA) are set to 1/12, 1/96, and 1/1791, respectively. In other words, the ratios of LA to SA, SA to VSA, and VSA to ESA are 1/12, 1/8, and 1/18.7,

Fig. 18.

SNR of the prototype wide dynanic range image sensor.

Fig. 19.

Measured 12-bit DNL and INL.

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respectively. The measured SNR dip at the boundaries of LA to SA, SA to VSA, and VSA to ESA is 16 dB, 14 dB, and 16 dB, respectively. These are larger than the theoretical SNR dip if the noise is limited by photon shot noise. This is because of the relatively large readout noise and the small conversion gain in this experimental chip. Fig. 19 shows the measured linearity of the 12-bit ADC integrated at the column of the developed image sensor without any calibration. The measured 12-bit differential nonlinearity (DNL) and integral nonlinearity (INL) are within 0.8/ 0.2 LSB, and 8.0/ 1.0 LSB, respectively. The input referred random noise is 6.2 LSB rms. The nonlinearity of the cyclic ADC is caused by the capacitor mismatch, charge injection due to switch transistors and noise coupling from other channels or digital circuits. The column-to-column fixed pattern noise . The (FPN) due to the cyclic ADC is measured to be 0.27% FPN can be cancelled in digital domain using a line memory. Using the digital FPN cancellation, the FPN is reduced to less . than 0.1% A single-channel cyclic ADC with the same design as that integrated at the column of the image sensor is also implemented in a test chip. The maximum DNL and INL in 12-bit resolution are within 0.8/ 0.6 LSB, and 4.0/ 3.9 LSB, respectively. The input referred random noise is 2.7 LSB (667 V) in 12 bits.

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V. CONCLUSION

TABLE I PERFORMANCE OF THE DEVELOPED CMOS IMAGE SENSOR

In this paper, a wide dynamic range CMOS image sensor with 12-bit column-parallel high-speed cyclic ADCs has been described. The developed image sensor can capture maximally four different accumulation-time signals in one frame. The dynamic range is expanded by 65.1 dB. The 12-bit cyclic ADC with the noise canceling function integrated at the column has a sufficient linearity. A clear wide dynamic range image keeping relatively high SNR in all the illumination range can be synthesized using the image signals captured by the developed CMOS image sensor. In this image sensor, pinned photodiode technology, which is becoming a common technology in high-sensitivity CMOS image sensors, is not used. The application of the pinned photodiode technology will much improve the performance of our image sensor at the low light level. The developed cyclic ADC can be used for high-resolution, wide dynamic range image sensors at the expense of power dissipation. It is also useful for other types of CMOS image sensors such as used for HDTV and high-speed cameras in which high-speed readout rate and high grayscale resolution are required. ACKNOWLEDGMENT The authors wish to thank Dr. Y. Ohta and Mr. J.-H. Park for helpful discussion. REFERENCES The INL of 8 LSB and the input noise of 2.7 LSB are large compared with the standard 12 bit ADC. However, the DNL of 0.2/ 0.8 LSB is acceptable for 12-bit resolution. The importance of the linearity of the ADC depends on the application. For ADCs for video signals, the INL is not so important because the human eye is not sensitive to nonlinearity of the photo conversion curve. The INL of 8 LSB in 12 bits corresponds to the maximum nonlinearity of 0.2% of full scale. The human eye cannot detect the nonlinearity of 0.2%. The DNL is very important in video applications, because a large DNL behaves like noise and degrades the image quality in low illumination region when a large digital gain is applied. The problem of the relatively large noise is due to the capacitive coupling of the comparator switching noise, and an improved version of the 12-bit ADC has already been implemented and measured in a test chip. The noise level was improved to 1.5 LSB. Therefore, the present design can achieve almost true 12-bit performance. The wide dynamic range image sensor was designed to be operated at 6 times faster readout speed than that of the normal video rate (30 frames/s). The resulting output data rate is 60 MHz. However, in the developed CMOS image sensor, the output data rate of up to 40 MHz without degradation of image quality has been demonstrated. This corresponds to 30 frames/s for , and 20 frames/s for , . The performance of the developed CMOS image sensor is summarized in Table I. The maximum accumulation time ratio is 1791 to 1, or 10.9 bits. In the above frame rates, the noise level of the multiple exposure methods is almost the same as the single (long only) exposure case. From the noise measurement results, the dynamic range is measured to be 19.8 bits or 119 dB.

[1] D. Scheer, B. Dierickx, and G. Meynants, “Random addressable 2048 2048 active pixel image sensor,” IEEE Trans. Electron Devices, vol. 44, no. 10, pp. 1716–1720, Oct. 1997. [2] T. Kakumoto, S. Yano, M. Kusuda, K. Kamon, and Y. Tanaka, “Logarithmic conversion CMOS image sensor with FPN cancellation and integration circuits,” J. Inst. Image Inf. TV Eng., vol. 57, no. 8, pp. 1013–1018, 2003. In Japanese. [3] S. Decker, R. D. McGrath, K. Brehmer, and C. G. Sodini, “A 256 256 CMOS imaging array with wide dynamic range pixels and columnparallel digital output,” IEEE J. Solid-State Circuits, vol. 33, no. 12, pp. 2081–2091, Dec. 1998. [4] O. Yadid-Pecht and E. R. Fossum, “Wide intrascene dynamic range CMOS APS using dual sampling,” IEEE Trans. Electon Devices, vol. 44, no. 10, pp. 1721–1723, Oct. 1997. [5] X. D. Y. David, A. El Gammal, B. Fowler, and H. Tian, “A 640 512 CMOS image sensor with ultra wide dynamic range floating-point pixellevelADC,” IEEE J. Solid-State Circuits, vol. 34, no. 12, pp. 1821–1999, Dec. 1999. [6] R. M. Guidash et al., “A 0.6 m CMOS pinned photodiode color imager technology,” in IEDM Tech. Dig., Dec. 1997, pp. 927–929. [7] K. Yonemoto, H. Sumi, R. Suzuki, and T. Ueno, “A CMOS image sensor with a FPN reduction technology and a hole accumulated diode,” in IEEE ISSCC Dig. Tech. Papers, Feb. 2000, pp. 102–103. [8] I. Inoue, H. Nozaki, H. Yamashita, T. Yamaguchi, H. Ishiwata, H. Ihara, R. Miyagawa, H. Miura, N. Nakamura, Y. Egawa, and Y. Matsunaga, “New LV-BPD (low voltage buried photodiode) for CMOS imager,” in IEDM Tech. Dig., Dec. 1999, pp. 883–886. [9] K. Findlator, R. Henderson, D. Baxter, J. Hurwitz, L. Grant, Y. Cazaux, F. Roy, D. Hrault, and Y. Marcellier, “SXGA pinned photodiode CMOS image sensor in 0.35 m CMOS technology,” in IEEE ISSCC Dig. Tech. Papers, Feb. 2003, pp. 218–219. [10] K. Mabuchi, N. Nakamura, E. Furatsu, T. Abe, T. Umeda, T. Hoshino, R. Suzuki, and H. Sumi, “CMOS image sensor using a floating diffusion driving buried photodiode,” in IEEE ISSCC Dig. Tech. Papers, 2004, pp. 112–113. [11] W. Bidermann, A. E. Gamal, S. Ewedemi, J. Reyneti, H. Tian, D. Wile, and D. Yang, “A 0.18 um high dynamic range NTSC/PAL imaging system-on-a-chip with enhanced DRAM frame buffer,” in IEEE ISSCC Dig. Tech. Papers, Feb. 1999, pp. 212–213.

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2

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[12] D. Yang and A. El Gamal, “Comparative analysis of SNR for image sensors with widened dynamic range,” in Proc. SPIE, vol. 3649, San Jose, CA, Feb. 1999, pp. 197–211. [13] B. Ginetti, P. G. A. Jespers, and A. Vandemeulebroecke, “A CMOS 13-b cyclic RSD A/D converter,” IEEE J. Solid-State Circuits, vol. 27, no. 7, pp. 957–965, Jul. 1992. [14] K. Nagaraj, “Efficient circuit configurations for algorithmic analog to digital converters,” IEEE J. Solid-State Circuits, vol. 40, no. 12, pp. 777–785, Dec. 1993. [15] S. H. Lewis and P. R. Gray, “A pipelined 5-MSample/s 9-bit analog-todigital converter,” IEEE J. Solid-State Circuits, vol. SC-22, no. 6, pp. 954–961, Dec. 1987. [16] T. B. Cho and P. R. Gray, “A 10 bit 20 Msample/s 35 mW pipeline A/D converter,” IEEE J. Solid-State Circuits, vol. 30, no. 3, pp. 166–172, Mar. 1995.

Mitsuhito Mase was born in Shizuoka, Japan, in 1980. He received the B.E. and M.E. degrees in electrical and electronic engineering from Shizuoka University, Hamamatsu, Japan, in 2003 and 2005, respectively. His research interest is in wide dynamic range CMOS image sensors and column-parallel A/D converters. Mr. Mase is a member of the Institute of Image Information and Television Engineers of Japan.

Shoji Kawahito (M’86–SM’00) was born in Tokushima, Japan, in 1961. He received the B.E. and M.E. degrees in electrical and electronic engineering from Toyohashi University of Technology, Toyohashi, Japan, in 1983 and 1985, respectively, and the D.E. degree from Tohoku University, Sendai, Japan, in 1988. In 1988, he joined Tohoku University as a Research Associate. From 1989 to 1999, he was with Toyohashi University of Technology. From 1996 to 1997, he was a Visiting Professor at ETH, Zurich. Since 1999, he has been a Professor with the Research Institute of Electronics, Shizuoka University. His research interests are in mixed analog/digital circuit design for imaging and sensing devices and systems. Dr. Kawahito received the Outstanding Paper Award at the 1987 IEEE International Symposium on Multiple-Valued Logic, the Special Feature Award in LSI Design Contest at the 1998 Asia and South Pacific Design Automation Conference, Beatrice Winner Award at the 2005 IEEE International Solid-State Circuits Conference. He is a member of the Institute of Electronics, Information and Communication Engineers of Japan and the Institute of Image Information and Television Engineers of Japan, and the International Society for Optical Engineering.

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Masaaki Sasaki (M’98) was born in Akita, Japan, in 1973. He received the B.E. and M.E. degrees in information and computer sciences from Toyohashi University of Technology, Toyohashi, Japan, in 1996 and 1998, respectively. In 1998, he joined Sendai National College of Technology as a Research Associate. From 2002 to 2004, he was with Toyohashi University of Technology. Since 2004, he has been a Research Associate with Sendai National College of Technology. His research interests include wide dynamic range CMOS image sensors and wide dynamic range image processing. Mr. Sasaki is a member of the Institute of Image Information and Television Engineers of Japan.

Yasuo Wakamori received the M.S. degree in physics from Kanazawa University, Kanazawa, Japan, in 1982. From 1982 to 1985, he has been engaged in the development of high-speed static RAM with Hitachi ULSI Systems Company, Ltd. From 1985 to 1989, he was engaged in research on CMOS device technology in Fuji Xerox Company, Ltd. In 1989, he joined Yamaha Corporation, Iwata, Japan, where he worked on the design of static RAM and ASSP. He is currently engaged in work on CMOS image sensors.

Masanori Furuta (S’01–M’04) was born in Mie, Japan, in 1975. He received the B.E. and M.E. degrees in information and computer sciences from Toyohashi University of Technology, Toyohashi, Japan, in 1998 and 2000, respectively, and the Ph.D. degree from Shizuoka Univesity, Hamamatsu, Japan, in 2004. Currently, he is a Research Associate in the Research Institute of Electronics, Shizuoka University, Hamamatsu, Japan. His research interest is in highspeed low-power A/D converter design.