IEEE BCTM 16.5
A Wideband Fully Integrated 0.25pm BiCMOS SGHz Medium Power Amplifier Michele Vaiana, Giuseppe Gramegna and Mario Paparo STMicroelectronics,Str. Pnmosole 50,95121 Catania, ITALY tel.: +39-095-7404138, fax:+39-095-7404001,e-mail:
[email protected]
II. S i C k C BIPOLAR TECHNOLOGY
Abstract. A wideband 4.2GHz-5.6GHz balanced Medium Power Amplifier has been designed in a 0.2Spm SiGe:C bipolar process. The two stage amplifier is housed in a VFQF’F”20 package with integrated inputloutput matcbing networks and onboard printed rat-race balnns. A saturated output power of 16dBm has been measured with a small signal gain of IS.2dB at SGHz with a total current consumption of llOmA from a 2.4V supply voltage at ambient temperature. The measured 3dB bandwidth is IIGHz, the best value ever reported in literature for a fully integrated medium PA housed in a standard padage for mass production witb DO external components required for inputloutput matching. The die size is 1.4~1.750m d .
I. INTRODUCTION Several narrowband SGHz power amplifiers have been presented so far [1,2,3]. An on-chip matching networks with no extemal components with the die directly mounted onto the Printed Circuit Board has been reported in [I]. Off-chip matching networks to drive the output balun have been used in [2]. A CMOS PA is reported in [3] with performances evaluated at chip level by using on wafer probes. However, the introduction of 802.1la standard calls for wideband designs and mass production requires cost-effective, standard package, solutions for the designed RF PA. Wideband design is not power efficient and package severely affects RF performances. These issues have not been addressed simultaneously in [1-3] and for similar design the challenge is often in the careful evaluation of parasitic associated to the package. This paper presents the design of a wideband class A Medium Power Amplifier (MPA) for SGHz, housed in a leadless VFQFPN20 package with 2.4V voltage supply. The presence of package required extensive use of electromagnetic simulations. The MPA does not require any external components, since rate-race baluns are printed on the Printed Circuit Board (F‘CB). The saturated output power is 16dBm at SGHz with a small signal gain of 1S.2dB. The 3dB bandwidth from 4.2GHz-S.6GHz (1.4 GHz) is the widest bandwidth reported so far for a packaged MPA with no external components. The MPA is ESD protected.
0-7803-8618-3/04/$20.00 02004 IEEE
The reported MPA has been integrated in a 0.2Spm SiGe:C BiCMOS process with high resistive substrate (ISVcm), S metal layers, npn transistors with quasi selfaligned emitter-base architecture and deep trench isolation to reduce collector to substrate parasitic capacitance. Carbon incorporation in the SiGe npn transistors allows very thin base profile and reduced base resistance at almost no penalty in fl. On chip inductors with quality factor in excess of 12 at SGHz can he implemented using thick top AlCu metal layer (2.5pm) and patterned ground shield. Two SiGe:C npn transistors are available: low voltage npn with BVCEO of 3V and Whax of 60GHzl9OGHz, suitable for low noise amplifier and high frequency applications; high voltage npn with BVCEO of 6V with reduced collector implant and fVfmax of 3OGHd9OGHz, suitahle for power applications. The SEM cross-section of a fabricated SiGe:C npn transistor with an effective emitter opening of 0 . 2 S p is shown in Figure 1. h4IM capacitors of SfF/prn’ and high value poly resistors of 1Wsq are also available.
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IEEE BCTM 16.5 In. CIRCUIT DESIGN
Package effects have been taken into account during design phase by means of extensive use of Ansofi HFSS 3D electromagnetic simulator. This tool has been used to extract an S-parameters representation of the package as well as to design the on-chip matching networks.
The fully integrated two stages class A amplifier has been designed by using internal matching networks and requires no external components. A push-pull configuration has been implemented taking advantage of a 4:1 load line benefit described in [l]. The driver stage features lOdB voltage gain and is depicted in Figure 2.
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A cascode differential pair with emitter degeneration provides an almost noise-less real part impedance equal to 2'(2x*fT*LI). Low voltage npn transistor (TI, TZ) with BVCEO of 3V have been used as common emitter transistor pair of the differential cascode driver stage. TI and T2 are biased with a quiescent current of 25mA. High voltage npn transistors have been selected for the common base pair (T3-T6). Efficiency has been improved by careful bias of the input stage (through Vcascode of T3-T4) in order to reduce Vce of TI-TZ and increase headroom for the output stage T3-T4. This yields in an increased output voltage swing with same DC current. 20dB gain control is implemented by steering signal current through T5-T6. No change in the input match is incurred for any gain setting, since TI-T2 bias current is unchanged regardless of bias condition of T3-T6. The second stage is shown in Figure 3. T7 and T8 are biased with a quiescent current of 25mA. Two emitter inductors (LS-L6) have been used in order to increase the bandwidth of the amplifier. In addition, emitter inductors introduce a series-series feedback that increases the output impedance between collector and ground. A trade-off between small signal output matching and output power matching has been realized increasing the output impedance of the stage in order to decrease the output mismatch at maximum power condition. Thus, improved matchinn- between the medium power amplifier and the following stage (i.e. balun or power amplifier) can be achieved at the expenses of gain and efficiency.
The bias circuits of the two stages consist in mirror devices with centroid layout far better matching and symmetrical layout. The bias circuit affects the linearity of the M P A emitter followers decrease low frequency impedance seen from the base tehinal of each stage towards bias circuit. This solution reduces regeneration of heat frequencies present in the modulation, improving IP3 of the amplifier and reducing back-off needed by IEEE 802.1 lamiperLAN applications.
IV.EXPERIMENTAL RESULTS A photo of the manufactured medium power amplifier is shorn in Figure 4. The die size is 1.4 x 1.750 nun* including pads.
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IEEE BCTM 16.5 IM3 (2'fl-t2) power levels are reported in Figure 8, resulting in an output IP3 of 23dBm.
Performances have been measured by using an evaluation board with a 2Omils thick ROGERS 4003 substrate (& = 3.38, tan 6 = 0.0027) Rat-race baluns have been designed and separately characterized to de-embed their associated losses. Measured insertion loss from the output chip plane to SMA connectors is in the range of 0.8dB in the whole bandwidth. No external components have been used to match the amplifier, with exception of DC coupling capacitances and bypass supply caps. Baluns have been printed directly on PCB. The complete evaluation board with input-output baluns is shoun in Figure 5 . Scattering Parameters of the amplifier in the 4GHz-6GHz frequency range are shown in Figure 6.
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Since IP3 measurements can only be used to predict lMD3 power levels with a two-tone input, power amplifier for wireless LAN can be fully characterized by driving the PA with OFDM input signals (64Q4M, 54Mbitls correspond to 12dB of peak-to-average power ratio) and measuring the Error Vector Magnitude (EVM) at the output of the MPA [4].
SI I and S22 < -10 dB have been achieved between 4.4GHz-5.6GHz with inputloutput isolation higher than 40dB over the entire bandwidth. dB
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Figure 6. Meastired S-Parameters Figure 7 reports output power versus input power (supplied through a CW power source) at 5GHz at three different temperatures. A saturated output power of I6dBm with a PldB of 12.75dBm has been achieved at 2 S T degree with a total current consumption of 1I O m A Same measurements have been carried out between -20°C to X O T degrees: PldB and gain variations are smaller than i1.25dB, showing the ruggedness of the amplifier over prior designs. Output IP3 of the amplifier has been evaluated driving the input of the MPA with two tones respectively at 4.9GHz and 5.1GHz. Measured fundamental (fl) and
EVM measurements have been carried out, at ambient temperature, driving the MPA with IEEE 802.1 l a Agilent E4338C vector signal generator at 5.32GHz. 64Q4M mode at 54Mbitis. The resulting EVM has been measured through an Agilent 896009 vector signal analym. The Complementary Cumulative Distribution Function (CCDF) of the output signal [5] is shown in Figure 9, together with a reference-ideal CCDF, i.e. as it would be with a distortion-less power amplifier. The measured and ideal CCDF are quite identical for low power levels, close to the average output power of 5.66dBm; when the compression of the MPA becomes significant, the measured output power SMS to diverge from the ideal CCDF curves.
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IEEE BCTM 16.5 V. CONCLUSION
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In this condition, a 3% EVM has been obtained with an average output power of 5.66dBm. Measurements have shorn that 7.2548 back-off from compression (PldB measured is 12.7SdBm) is necessary to meet the 3% EVM specification. The 7.25dB back-off needed is much lower than 12dB peak-to-average power ratio presented by the input OFDM signal (64QAM mode at 54MbiVs) confirming linearity of the MF'A and effectiveness of the bias network design.
A fully integrated MPA has been designed in a 0.25pm SiGe:C technology with on chip input output matching networks. The MPA has been housed in a leadless package for mass production (VFQFPNZO) and features a die area of 1.4 x 1.750 mm2. Measurements at connectors' plane reports a PldB of 12.75 dBm at 5GHz with a 3dB bandwidth of I .4GHz, the widest reported so far for a packaged fully integrated MPA. EVM measurements have shown that 3% of EVM can be met with only 7.25dB back-off from PldB compression with an average output power of 5.66dBm. RF performances achieved over the 1.4GHz bandwidth and the use of a standard package called for a design where high quality factors allowed by the technology couldn't be exploited. Despite the wideband design technique employed, this resulted into a total current consumption of 1 l O m A from a 2.4V supply
VI. ACKNOWLEDGEMENTS
The authors wish to acknowledge the conbibution of Giuseppe Cantnne and Giuseppe Di Chiara for board design and characterization support and Michele De Fazio for package simulation This work has been carried aut in the framework of EUCLID W A G CEPA 2 European project MOSES in cooperation with Thales. Authors thank Giusy Gambino and Lauren1 Vantrepol for program management. 3
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VII. REFERENCES
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[ I ] Bakalski W., Simburrger W., Thurhger R., Vasylyev A., Sholtz A. L., " A fully integrated 5.3 GHz, 2.4 V, 0.3 W
Figure IO. Ouputpowersperrrum @ 3% EVM The spechum of the output signal corresponding to an average output power of 5.66dBm and 3% EVM is reported in Figure IO. Higher average output power can be achieved at the expenses of the EVM: an average output power of 6.3dBm results in 4% EVM.
depicted-in Fi&re- 11. No major distortions have been measured in the received symbols in this condition. t5
SiGe-Bipolar Power Amplifier with 50 0 output ).L IEEE Jvnrnol U/ Solid-Store Cirorifs, vol. KK, no. pp. 1000I 000, Nnv. 2003.
[2] Margarit M. A., Shih D., Sullivan P. J., Ortega F., '' A 5GHz BiCMOS RFlC Front-End for IEEE 802.1 IdHiperLAN Wireless LAN ," IEEE Joanrol 01 Solid-Sfore Circsifs, vol. 38, no. 7 pp. 1281- 1287, July
2003. [3] Zhang W.,Khoo Ee-Sze, Tear T., "A low Voltage FullyIntegrated 0.18 pm CMOS Power Amplifier for 5 GHz
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WLAN, ESSCIRC 2002, pp. 215-218.
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Agilent Technologies, "Using Enor Vector Magnihlde Measurements to Analyze and Troubleshoot VectorModulated Signals," Agilent PN 89300-14 product note
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fromhttp://www.agilent.com
[4] OD
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[ 5 ] Agilent Technologies, "Characterizing Digitally Modulated
uwntiw 1-l7 Figure I I . Symbol constellation diagram
Signals with CCDF Cutver," Application Note from http://www.agilent.com
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