electronics Article

A ZVS Bidirectional Inverting Buck-Boost Converter Using Coupled Inductors Xu-Feng Cheng, Yong Zhang * and Chengliang Yin School of Mechanical Engineering, Shanghai Jiao Tong University, Shanghai 200240, China; [email protected] (X.-F.C.); [email protected] (C.Y.) * Correspondence: [email protected]; Tel.: +86-021-3463-6203 Received: 21 August 2018; Accepted: 26 September 2018; Published: 28 September 2018

Abstract: The bidirectional inverting buck-boost converter (BIBBC) has a simple structure and a wide voltage ratio. It can be used in the battery supercapacitor hybrid energy storage system (BSHESS) and the motor drive system. However, the traditional continuous conduction mode (CCM) BIBBC will have severe switching loss. The triangular current mode (TCM) BIBBC can reduce the switching loss, but it will increase core loss and filter capacitance. To solve these problems, this paper proposes a new zero voltage switching (ZVS) BIBBC using a coupled inductor. This ZVS BIBBC will provide ZVS conditions for both transistors whether in positive operation or negative operation. Meanwhile, this ZVS BIBBC has small core losses and filter capacitance, and can be used simply. Finally, experimental results obtained from these BIBBC experimental prototypes are presented to validate the soft-switching achieving and the efficiency improvement performance. Experimental results show that both transistors of the ZVS BIBBC achieve ZVS turn-on conditions. The efficiency of the ZVS BIBBC increased by up to 10 percent compared to the traditional CCM BIBBC at heave load, and by up to 1.5 percent compared to the TCM BIBBC at a light load. Keywords: bidirectional DC/DC converter; inverting buck-boost; soft-switching; coupled inductor

1. Introduction The nonisolated bidirectional DC/DC converter (NIBDC) can be used in the motor drive system and the battery supercapacitor hybrid energy storage system (BSHESS) [1–5]. In the BSHESS, the NIBDC is used to control the power flow between the supercapacitor and the battery. The energy management system of the BSHESS uses the NIBDC to manage and distribute the energy of the BIHESS to obtain two goals: improve battery life and increase vehicle efficiency [6–8]. Commonly-used NIBDCs have two types: The buck/boost converter and the buck-boost converter [9]. These NIBDCs have two operation directions: The positive operation and the negative operation. The buck/boost converter only has the voltage step-down function in positive operation, and only has the voltage step-up function in negative operation. In contrast with the bidirectional buck/boost converter, the bidirectional inverting buck-boost converter (BIBBC) has both voltage step-down and step-up functions whether in positive or negative operation. This means that the BIBBC will improve the performance of the motor drive system and the BSHESS. However, the BIBBC has higher voltage and current stress than the buck/boost converter under the same output voltage and current. Meanwhile the traditional continuous conduction mode (CCM) BIBBC works under hard-switching conditions. These factors introduce serious conducting and switching losses. To improve the efficiency of the BIBBC, the soft-switching technique is required. For the BIBBC, one of switches can always obtain the soft-switching condition. Therefore the key is the soft-switching condition for another switch. The simplest soft-switching technology for the BIBBC is the triangular current mode (TCM) method [10], which provides soft-switching conditions Electronics 2018, 7, 221; doi:10.3390/electronics7100221

www.mdpi.com/journal/electronics

Electronics 2018, 7, 221

2 of 15

for both switches by adjusting the value of the main inductor L. This technology does not use any auxiliary circuitry. However with this technology, the inductor current iL has large current ripples, which will introduce large current stresses, large core losses, and a large filter capacitance. In order to overcome these shortcomings, many new soft-switching technologies are proposed. The zero voltage transition (ZVT) technology is a commonly used method for the BIBBC [11–16]. By adding auxiliary switches, the ZVT technology gives zero voltage switching (ZVS) conditions for the main switches and zero current switching (ZCS) conditions for the auxiliary switches. Some improved ZVT methods use a coupled inductor to reduce core numbers and improve soft-switching performance [11,13,15]. ZVT-based topologies have high efficiency. The main shortcoming is the cost of auxiliary switches and the complex control timing, because the soft-switching condition is dependent on the control timing. The active clamped soft-switching technology was proposed in multiple previous papers [17,18] for the buck/boost converter, and this technology can also be used in the bidirectional buck-boost converter. In this method only one auxiliary switch is used to obtain soft-switching conditions for two main switches. The coupled inductor can also be used in this topology to improve performance [18]. The shortcoming of these active clamped topologies is the cost of auxiliary switches and the complex control timing. In order to reduce the control complexity of soft-switching topologies, some soft-switching technologies without auxiliary switches were proposed previously [19,20]. In these topologies, the auxiliary circuit, composed of inductors and capacitors, is introduced to the BIBBC to obtain soft-switching conditions. These topologies have a simple structure and have no auxiliary switches. However a previously proposed method is based on the special application (battery equalization applications) [19], and another previously proposed method also faces the problem of large current stresses and core losses [20]. For the existing soft-switching BIBBCs, TCM BIBBCs introduces large current stresses, large core losses, and large filter capacitance; ZVT BIBBCs need auxiliary switches and complex control timing. To overcome these shortcomings, this paper proposes a new ZVS BIBBC using a coupled inductor based on the buck-boost converter in literature [21,22], in which the converter can only obtain soft-switching conditions in positive operation. The structural difference between the proposed ZVS BIBBC and the original converter is the introduced diode. With this diode the ZVS BIBBC has a different operation principle to the original converter, and can provide soft-switching conditions for both transistors whether in positive operation or negative operation. The proposed ZVS BIBBC has comprehensive advantages over similar existing converters:

• • • • • • •

Higher efficiency than the CCM BIBBC in most power ranges and higher efficiency than the TCM BIBBC in the medium and low power range; A simpler control method and lower cost than ZVT converters; Lower core losses and filter capacitance than the TCM BIBBC. In short, this paper provides the following contributions: Proposal of a new ZVS BIBBC using a coupled inductor with abovementioned advantages; Detailed theoretical analysis and design guidelines of the new ZVS BIBBC; Experimental analysis and comparison between the proposed ZVS BIBBC and two other BIBBCs.

This paper is organized as follows. Section 2 presents the topology description and operating principle; the soft-switching achieving condition, stress and loss analysis, and design guidelines are given in Section 3. Experimental results and the related analysis are presented in Section 4. Section 5 summarizes the content and contributions of the full paper. 2. Topology and Its Principle 2.1. Proposed Converter The proposed new ZVS BIBBC, which has bidirectional soft-switching capability, is shown in Figure 1. This converter does not use an auxiliary switch and, therefore, the control complexity of the

Electronics 2018, 7, 221 Electronics 2018, 7, x FOR PEER REVIEW

3 of 15 3 of 16

the new ZVS BIBBC is theassame as a traditional CCM BIBBC. Thisisconverter is nonisolated suitable for new ZVS BIBBC is the same a traditional CCM BIBBC. This converter suitable for nonisolated bidirectional DC/DC applications requiring wide voltage The of drawback of the bidirectional DC/DC applications requiring wide voltage ratios. The ratios. drawback the proposed proposed new ZVS BIBBC is the additional loss caused by auxiliary diodes. Nonetheless, the new ZVS BIBBC is the additional loss caused by auxiliary diodes. Nonetheless, the achieving achieving of soft-switching will the improve the efficiency comparing to the hard-switching of soft-switching conditionsconditions will improve efficiency comparing to the hard-switching BIBBC. BIBBC. The proposed ZVSalso BIBBC also operation has two operation directions: Theoperation positive operation and the The proposed ZVS BIBBC has two directions: The positive and the negative negative operation. positive operation, power flow is transferred a to vb. In negative operation. In positiveInoperation, the powerthe flow is transferred from va to vfrom negative operation, b . In v operation, the power flow isfrom transferred vb to in va.Figure As shown Figure 1, theauxiliary soft-switching the power flow is transferred vb to va . from As shown 1, the in soft-switching circuit auxiliary circuit of the proposed BIBBC includes two power diodes, D 1 and D 2 , a coupled inductor of the proposed BIBBC includes two power diodes, D1 and D2 , a coupled inductor Lc , and a resonance Lc, and aLresonance r. The main the new ZVS BIBBC includes transistors S1 inductor circuit ofLthe new ZVScircuit BIBBCof includes two transistors S1 and S2two , a main inductor r . The maininductor and , a main capacitors inductor L,Cr1 two snubber capacitors r1 and Cr2,Cand two filter capacitors C a and C b . C r1 L, twoS2snubber and Cr2 , and two filter C capacitors and C . C and C are connected to a r1 r2 b and C r2 are connected to transistors S 1 and S 2 in parallel, respectively. L r is used to compensate transistors S1 and S2 in parallel, respectively. Lr is used to compensate negative effects of Cr1 and Cr2 negative of Cr1 The and coupled Cr2 on ZVS-on conditions. The coupled Lc2, and auxiliaryZVS-on diodes on ZVS-oneffects conditions. inductor Lc , and auxiliary diodesinductor D1 and D will provide D1 and D2for will provide ZVS-on conditions S 1 negative (the positive operation) and S 2 (the negative conditions S1 (the positive operation) and Sfor (the operation). Other symbols are defined 2 operation). arevoltage definedvalues, as follows. a and vbacross are the voltage values, the as follows. vaOther and vbsymbols are the DC ic is thevcurrent Lc , iDC current acrossic L,isand L is the across L c , i L is the current across L, and i r is the current across L. icurrent is the current across L. r

Figure 1. Proposed zero voltage switching (ZVS) bidirectional inverting buck-boost converter (BIBBC). Figure 1. Proposed zero voltage switching (ZVS) bidirectional inverting buck-boost converter In the following sections, the mathematical model of the new ZVS BIBBC will be presented. (BIBBC).

All variables are International System of Units. Based on the circuit conduction state of the ZVS BIBBC, proposed sections, ZVS BIBBC have fourmodel operation intervals byBIBBC ignoring charging and In the following the will mathematical of the new ZVS willthe be presented. All discharging of snubber capacitors. Equivalent of these intervals are of shown in Figure 2. variables areprocess International System of Units. Based oncircuits the circuit conduction state the ZVS BIBBC, These equivalent circuits canwill be used build the mathematical model of the the newcharging ZVS BIBBC. the proposed ZVS BIBBC have tofour operation intervals by ignoring and For Interval I,process the differential equations of currents (ic , iLcircuits , and irof ) are discharging of snubber capacitors. Equivalent these intervals are shown in Figure 2. These equivalent circuits can be used to build the mathematical model of the new ZVS BIBBC. −v a ( M− Lr )−vb ( Lc + M) k L1 = didtL of =currents For Interval I, the differential , i)+( L, and ir))(are ( L+ M)( Lr(i −cM Lc + M L + Lr ) equations v ( L+ L )+v ( L+ M)

k = dic = ( L+ M)(a L − Mr )+( Lb + M)( L+ L ) (1) c1 didtL r − L ) − cv ( Lc + M r) −v ( M = dir = −v a (aL+ M)−rvb ( L+bLc + 2M ) kk L1 = dt −MM)+( ) +L(c L +)(ML+)(LLr )+ Lr ) dt =( L( L++M M)( )(L Lr − +cM r1 di v (L + L ) + v (L + M ) = c = L anda L . Ifr k is bthe coupling coefficient, then M2 = k2 LL(1) kc1 between where M is the mutual inductance c. dt ( L + M )( Lrc− M ) + ( Lc + M )( L + Lr ) For Interval II, they are di −va ( L + M ) − vb ( L + Lc + 2 M ) k = r = r1 dtdi ( L + M )( Lr −−M ( LLcr )+ M )( L + Lr ) v ()L+c + k = dtL = ( L+ M)( L − Mb )+( Lc + M )( L+ Lr ) r L2 ) dic coupling coefficient, then M2 = k2LL(2) c. where M is the mutual inductance between L and Lcv. bIf( Mk−isLrthe k c2 = = dt ( L+ M)( Lr − M)+( Lc + M)( L+ Lr ) For Interval II, they are −vb ( Lc + M ) k = dir = r2

dt

( L+ M)( Lr − M)+( Lc + M)( L+ Lr )

Electronics 2018, 7, 221

diL −vb ( Lc + Lr ) = kL 2 = dt ( L M )( L M ) + ( Lc + M )( L + Lr ) + − r dic vb ( M − Lr ) = kc 2 = dt ( L + M )( L − M ) + ( Lc + M )( L + Lr ) r di −vb ( Lc + M ) kr 2 = r = dt ( L + M )( Lr − M ) + ( Lc + M )( L + Lr )

(2) 4 of 15

Figure 2. Equivalent circuits of operation intervals: (a) Interval I; (b) Interval II; (c) Interval III; and (d) Figure 2. Equivalent circuits of operation intervals: (a) Interval I; (b) Interval II; (c) Interval III; and (d) Interval IV. Interval IV.

For Interval III, they are For Interval III, they are v a ( Lc + M )+vb ( M− Lr ) k = di L = LcLr+−M + vLbc(+MM− M))+( )( LL+ kL3 = diLdt= ( L+vM a ()( r )Lr ) L3 −v a ( L+ M)−vb ( L+ Lr ) dic dt ( L M )( L M ) ( L M )( L+L ) + − + + k = = (3) c3 dt ( L+ M)( Lrr − M)+( Lc +c M)( L+ Lr ) r v−av( L(+LL+ 2M )+ v ( L + M ) k =didic r = c +M ) − vbb( L + Lr ) a dt= ( L+ M)( Lr − M)+( Lc + M)( L+ Lr ) (3) kr3 c3 = ( )( ) dt L + M L − M + ( Lc + M )( L + Lr ) r di va ( L + Lc + 2 M ) + vb ( L + M ) For Interval IV, they are kr 3 = r = dt ( L + M )( Lr − M ) + ( Lc + M )( L + Lr ) v a ( L c + Lr ) di L k = = L4 dt ( L+ M)( Lr − M)+( Lc + M)( L+ Lr ) For Interval IV, they are − v ( M − Lr ) (4) k c4 = didtc = ( L+ M)( L − Ma )+( L + r c M )( L + Lr ) vvaa((LLcc++ML)r ) k =didiL r = dt = ( L+ M )( L − M)+( L + M )( L+ L ) r4 L4 = dt ( L + M )( Lrr − M ) + (cLc + M )( Lr + Lr ) dic −va ( M − Lr ) 2.2. Positive Operation = (4) kc 4 = dt ( L + M )( L − M ) + ( Lc + M )( L + Lr ) r To describe the operation principle clearly, this section gives the analysis of voltage and current dir va ( Lc + M ) = of the positive kr 4 = (T) waveforms in one switching period operation. As shown in Figures 3 and 4, dt ( L + M )( L − M ) + ( Lc + M )( L + Lr ) the voltage and current waveforms of the proposedr ZVS BIBBC can be divided into eight modes based on the circuit conduction state. Figure 3 gives gate signal waveforms (VGS1 and VGS2 ) and drain-source 2.2. Positive Operation voltage waveforms (VS1 and VS2 ) respectively for S1 and S2 , and also gives main current waveforms (iL , ir , and ic ). In Figure 3, D is the duty cycle of the gate signal (VGS1 ) of S1 . Figure 4 gives circuit To describe the operation principle clearly, this section gives the analysis of voltage and conduction states of these modes. In positive operation, the mean value of iL will be positive, and the current waveforms in one switching period (T) of the positive operation. As shown in Figure 3 and energy is transferred from va to vb . If the load current is large enough (all waveforms of iL are above the Figure 4, the voltage and current waveforms of the proposed ZVS BIBBC can be divided into eight time-axis), iL will be continuous. D1 and D2 will not conduct at the same time. ir will be bidirectional modes based on the circuit conduction state. Figure 3 gives gate signal waveforms (VGS1 and VGS2) in DT and (1 − D)T will provide soft-switching conditions for S1 and S2 . The detailed analysis of each and drain-source voltage waveforms (VS1 and VS2) respectively for S1 and S2, and also gives main mode is presented as follows. current waveforms (iL, ir, and ic). In Figure 3, D is the duty cycle of the gate signal (VGS1) of S1. Figure Mode 1 (t –t1 , Figure 4a): At the beginning of this mode (t0 ), S1 is turned off by the low-level of 4 gives circuit 0conduction states of these modes. In positive operation, the mean value of iL will be VGS1 . After t0 the changing of VS1 and VS2 is slow due to the existence of Cr1 and Cr2 . The ZVS-off positive, and the energy is transferred from va to vb. If the load current is large enough (all condition of S1 is obtained. iL and ir are positive and start to decrease. ic is negative and starts waveforms of iL are above the time-axis), iL will be continuous. D1 and D2 will not conduct at the to increase. same time. ir will be bidirectional in DT and (1 − D)T will provide soft-switching conditions for S1 Mode 2 (t1 –t2 , Figure 4b): In this mode VS2 decreases to 0 at t1 , and then is kept to 0 due to the and S2. The detailed analysis of each mode is presented as follows. conduction of the body diode of S2 . Mode 1 (t0–t1, Figure 4a): At the beginning of this mode (t0), S1 is turned off by the low-level of Mode 3 (t2 –t3 , Figure 4c): Because VS2 is 0 at t2 , S2 conducts at ZVS-on condition. In this mode VGS1. After t0 the changing of VS1 and VS2 is slow due to the existence of Cr1 and Cr2. The ZVS-off the changing trend of waveforms of iL , ir , and ic is same to Mode 1 and Mode 2. Mode 4 (t3 –t4 , Figure 4d): At t3 , the current across D1 decreases to 0, and then D1 turns off. The current across D2 starts to increase from 0, therefore, D2 turns on. ic is crossing the time-axis and become positive. The increasing rate of ic slows. The decreasing rate of iL and ir also decrease. When ic is equal to iL , ir starts to be negative.

Mode 3 (t2–t3, Figure 4c): Because VS2 is 0 at t2, S2 conducts at ZVS-on condition. In this mode the changing trend of waveforms of iL, ir, and ic is same to Mode 1 and Mode 2. Mode 4 (t3–t4, Figure 4d): At t3, the current across D1 decreases to 0, and then D1 turns off. The current across D2 starts to increase from 0, therefore, D2 turns on. ic is crossing the time-axis and become Electronicspositive. 2018, 7, 221The increasing rate of ic slows. The decreasing rate of iL and ir also decrease. When 5 of 15 ic is equal to iL, ir starts to be negative.

Electronics 2018, 7, x FOR PEER REVIEW

6 of 16

Figure 4. Operating modes in positive operation: (a) Mode 1: t0–t1; (b) Mode 2: t1–t2; (c) Mode 3: t2–t3; (d) Mode 4: t3–t4; (e) Mode 5: t4–t5; (f) Mode 6: t5–t6; (g) Mode 7: t6–t7; and (h) Mode 8: t7–t8.

2.3. Negative Operation

Figure 3. Key waveforms in positive operation. Figure 3. Key waveforms in positive operation.

Mode 5 (t4–t5, Figure 4e): S2 is turned off at the beginning of this mode (t4). Similar to mode 1, the changing of VS1 and VS2 is also slow. The ZVS-off condition for S2 is achieved. After t4, iL and ir start to increase. ic starts to decrease. Mode 6 (t5–t6, Figure 4f): VS1 decreases to 0 at t5, and is clamped to 0 due to the conduction of the body diode of S1. iL, ic, and ir have the same state as Mode 5. Mode 7 (t6–t7, Figure 4g): Because VS1 is kept at 0, S1 starts to conduct at the ZVS-on condition at t6. When ic is equal to iL, ir starts to become positive. The conducting state in this mode is the same as Mode 6. Mode 8 (t7–t8, Figure 4h): At t7, the current across D2 decreases to 0, and then D2 turns off. And the current across D1 starts to increase from 0, therefore, D1 turns on. ic is crossing the time-axis and becomes negative. The decreasing rate of ic reduces. The rising rate of iL and ir also reduce. Similar toFigure the positive operation, the negative operation also has eight modes. Figure 5 presents the 4. Operating modes in positive operation: (a) Mode 1: t0 –t1 ; (b) Mode 2: t1 –t2 ; (c) Mode 3: t2 –t3 ; key voltages and current waveforms, Figure 6 presents the circuit conductive states of the (d) Mode 4: t3 –t4 ; (e) Mode 5: t4 –tand 5 ; (f) Mode 6: t5 –t6 ; (g) Mode 7: t6 –t7 ; and (h) Mode 8: t7 –t8 . negative operation. Comparing the negative operation to the positive operation, the mean value of iL is negative, and the will beStransferred to vat a. ithe c of beginning the negative operation sameto state Mode 5 (t 4e): of this mode has (t4 ).the Similar mode 1, 4 –tenergy 5 , Figure 2 is turned off as thethepositive operation. i r moves to the negative direction compared to the positive operation. changing of VS1 and VS2 is also slow. The ZVS-off condition for S2 is achieved. After t4 , iL and ir Therefore, zero crossing position of ir (mode 3 and mode 8) is different from the positive start tothe increase. ic starts to decrease. operation Mode (mode6 4(t5and mode 7). detailed mode ofisthe negative refer theof the –t6 , Figure 4f):AVS1 decreases to 0analysis at t5 , and clamped to 0operation due to thecan conduction modebody analysis of of theS1positive operation 2.2. as Mode 5. diode . iL , ic , and ir have in theSection same state Mode 7 (t6 –t7 , Figure 4g): Because VS1 is kept at 0, S1 starts to conduct at the ZVS-on condition at t6 . When ic is equal to iL , ir starts to become positive. The conducting state in this mode is the same as Figure 5. Key waveforms in negative operation. Mode 6. Mode 8 (t7 –t8 , Figure 4h): At t7 , the current across D2 decreases to 0, and then D2 turns off. And the current across D1 starts to increase from 0, therefore, D1 turns on. ic is crossing the time-axis and becomes negative. The decreasing rate of ic reduces. The rising rate of iL and ir also reduce.

Figure 4. 7,Operating modes in positive operation: (a) Mode 1: t0–t1; (b) Mode 2: t1–t2; (c) Mode 3: t2–t3;6 of 15 Electronics 2018, 221 (d) Mode 4: t3–t4; (e) Mode 5: t4–t5; (f) Mode 6: t5–t6; (g) Mode 7: t6–t7; and (h) Mode 8: t7–t8.

2.3. Negative Negative Operation Operation 2.3. Similar to operation, the the negative operation also has Figure 5Figure presents Similar tothe thepositive positive operation, negative operation alsoeight hasmodes. eight modes. 5 the key voltages and current waveforms, and Figure 6 presents the circuit conductive states of the presents the key voltages and current waveforms, and Figure 6 presents the circuit conductive negative Comparing theComparing negative operation to the operation positive operation, the mean value of ithe L is states of operation. the negative operation. the negative to the positive operation, negative, and the energy will be transferred to v . i of the negative operation has the same state as the a c mean value of iL is negative, and the energy will be transferred to va. ic of the negative operation has positive operation. i moves to the negative direction compared to the positive operation. Therefore, the same state as ther positive operation. ir moves to the negative direction compared to the positive the zero crossing position ir (mode 3 and mode of 8) is the positive operationfrom (mode operation. Therefore, the of zero crossing position ir different (mode 3 from and mode 8) is different the4 and mode 7). A detailed mode analysis of the negative operation can refer the mode analysis of the positive operation (mode 4 and mode 7). A detailed mode analysis of the negative operation can positive operation in Section 2.2. refer the mode analysis of the positive operation in Section 2.2.

Electronics 2018, 7, x FOR PEER REVIEW

7 of 16

Figure 6. Operating modes in negative operation: (a) Mode 1: t0–t1; (b) Mode 2: t1–t2; (c) Mode 3: t2–t3; (d) Mode 4: t3–t4; (e) Mode 5: t4–t5; (f) Mode 6: t5–t6; (g) Mode 7: t6–t7; and (h) Mode 8: t7–t8.

3. Converter Analysis and Design 3.1. Soft-Switching Conditions

Figure 5. Key waveforms in negative operation. Figure 5. Key waveforms in negative operation.

The introduction of Cr1 and Cr2 can reduce operation: the rising(a)rate of 1: VS1t –t and VS2 to provide passive ZVS-off Figure 6. Operating modes in negative Mode 0 1 ; (b) Mode 2: t1 –t2 ; (c) Mode 3: t2 –t3 ; conditions for S 1 and S2. But the existence of Cr1 and Cr2 has an adverse effect on achieving ZVS-on (d) Mode 4: t3 –t4 ; (e) Mode 5: t4 –t5 ; (f) Mode 6: t5 –t6 ; (g) Mode 7: t6 –t7 ; and (h) Mode 8: t7 –t8 . conditions. Therefore, the resonant inductor Lr is used to compensate the capacitive feature of switches (S1 and S2) introduced by Cr1 and Cr2. Based on the capacitor and inductor energy storage formula [23], the compensation energy formula is (Cr1 + Cr 2 )(va + vb ) 2 Lr ir2 = 2 2

(5)

Based on the above operation mode analyses, soft-switching conditions of the proposed ZVS

Figure modes in negative operation: (a) Mode 1: t0–t1; (b) Mode 2: t1–t2; (c) Mode 3: t2–t37; of 15 Electronics 2018,6.7,Operating 221 (d) Mode 4: t3–t4; (e) Mode 5: t4–t5; (f) Mode 6: t5–t6; (g) Mode 7: t6–t7; and (h) Mode 8: t7–t8.

3. 3. Converter Analysis Analysis and and Design Design 3.1. 3.1. Soft-Switching Soft-Switching Conditions Conditions The can reduce the rising rate of VS1S1 and to provide passive The introduction introduction of of CCr1r1 and and CCr2 r2 can reduce the rising rate of V and VVS2 S2 to provide passive ZVS-off conditions for S and S . But the existence of C and C has an adverse r1 r2 1 2 ZVS-off conditions for S1 and S2. But the existence of Cr1 and Cr2 has an adverse effect effect on on achieving achieving ZVS-on conditions. Therefore, the resonant inductor L is used to compensate the capacitive feature of ZVS-on conditions. Therefore, the resonant inductor rLr is used to compensate the capacitive feature switches (S1 and S2 ) introduced by Cr1 on theon capacitor and inductor energy storage r2 . Based of switches (S1 and S2) introduced byand Cr1 Cand Cr2. Based the capacitor and inductor energy formula [23], the compensation energy formula is storage formula [23], the compensation energy formula is 2

2

(CC + )( Crv2 a)(+ va v +bv)b2) LLrririr2 (Cr1 + r1 r2 == 2 22 2

(5) (5)

Based on on the the above above operation operation mode mode analyses, analyses, soft-switching soft-switching conditions conditions of of the the proposed proposed ZVS ZVS Based BIBBC are areshown showninin Figure 7. Figure the ZVS-on condition the positive operation. In BIBBC Figure 7. Figure 7a is7a theisZVS-on condition for the for positive operation. In positive positive operation, S2 willobtain always obtain thecondition. ZVS-on condition. Thecondition ZVS-on condition of Sir1 must is thatbeir operation, S2 will always the ZVS-on The ZVS-on of S1 is that must be at negative at t7b 6. Figure 7b is thecondition ZVS-on for condition for theoperation. negative operation. negative negative t6 . Figure is the ZVS-on the negative In negativeInoperation, S1 will always obtain the ZVS-on condition. The ZVS-on condition of S2 is that ir must be Soperation, 1 will always obtain the ZVS-on condition. The ZVS-on condition of S2 is that ir must be positive at t2 . positive at t2. Then the soft-switching of the proposed BIBBC arebe that ir must at bet6negative Then the soft-switching conditions of conditions the proposed BIBBC are that ir must negative and be at t 6 and be positive at t 2 . positive at t2 .

Figure7.7.ZVS-on ZVS-onachieving achievingconditions: conditions:(a)(a)The Thepositive positiveoperation operationand and(b) (b)the thenegative negativeoperation operation. Figure .

Then Then soft-switching soft-switching achieving achieving equations equations are are at t6 : ir = i L − ic < 0 at t2 : ir = i L − ic > 0

(6)

iave is set as the average value of iL , iL is marked as iL6 at t6 , and iL is marked as iL2 at t2 . iave can be used to represent the load level of the new ZVS BIBBC. Because iave will be roughly equal to the median value of iL , iL can be estimated by (

i L6 = i ave + i L2 = i ave +

k L1 (t3 −t0 )+k L2 (t4 −t3 ) 2 k L3 (t7 −t4 )+k L4 (t8 −t7 ) 2

+ k L3 (t6 − t4 ) + k L1 (t2 − t0 )

At t6 , ic is marked as ic6 , and at t2 , ic is marked as ic2 , then ic will be ( ic6 = k c2 (t4 − t3 ) + k c3 (t6 − t4 ) ic2 = k c4 (t8 − t7 ) + k c1 (t2 − t0 )

(7)

(8)

Electronics 2018, 7, 221

8 of 15

Substituting (7) and (8) into (6),the soft-switching achieving equations can be rewritten as at t6 : i ave + at t2 : i ave +

k L1 (t3 −t0 )+(k L2 −2k c2 )(t4 −t3 ) 2 k L3 (t7 −t4 )+(k L4 −2k c4 )(t8 −t7 ) 2

+ (k L3 − k c3 )(t6 − t4 ) < 0 + (k L1 − k c1 )(t2 − t0 ) > 0

(9)

To guarantee the achieving of ZVS-on conditions, the first equation of (9) limits the maximum value of the positive load (the maximum value of iave is positive), and the second equation of (9) limits the maximum value of the negative load (the minimum value of iave is negative). Equation (9) is the initial soft-switching achieving condition of the proposed converter. Because values of the time in (9) are unknown, Equation (9) cannot be used in the actual design. To further simplify (9), setting d1 = t3 − t0 , d2 = t4 − t3 , d3 = t7 − t4 , d4 = t8 − t7 , x1 = d1 /(d1 + d2 ), x2 = d3 /(d3 + d4 ). Then ( d1 + d2 = (1 − D ) T (10) d3 + d4 = DT In one period, the changing of ir and ic is zero. Then kr1 d1 + kr2 d2 + kr3 d3 + kr4 d4 = 0 k c2 d3 + k c3 d3 = 0 k d +k d = 0 c1 1 c4 4 Based on (10) and (11), x1 and x2 are (

x1 = x2 =

(11)

D ( M − Lr ) L+ M (1− D )( M− Lr ) L+ M

(12)

Based on (9) and (10), the soft-switching achieving equation can be rewritten as i ave + i ave +

T (1− D )[k L1 x1 +(k L2 −2k c2 )(1− x1 )] + (k L3 − k c3 )tde < 2 DT [k L3 x2 +(k L4 −2k c4 )(1− x2 )] + ( k L1 − k c1 ) tde > 0 2

0

(13)

tde is the dead time, tde = t6 − t4 = t2 − t0 . Then substituting (1)–(4), and (12) into (13), the softswitching achieving condition is 2(i ave +kr3 tde ) Tvb (1− D ) 2(i ave +kr1 tde ) DTv a

< >

(1−2D )( M− Lr )2 +( L+ M)( Lc +2M− Lr ) ( L+ M)[( L+ M)( Lr − M)+( Lc + M)( L+ Lr )] (1−2D )( M− Lr )2 −( L+ M)( Lc +2M− Lr ) ( L+ M)[( L+ M)( Lr − M)+( Lc + M)( L+ Lr )]

(14)

Equation (14) is the soft-switching limited condition. From (14), we can determine that this equation limits the range of iave from the negative value to the positive value. The negative value of iave represents the negative power flow, and the positive value of iave represents the positive power flow. This soft-switching limited condition gives a load limiting soft-switching condition. For a designed converter, if the absolute value of iave is smaller than the designed iave , the soft-switching conditions will always be obtained. We can also know that a large Lc and small L is beneficial to achieving ZVS-on. However a small L will lead to large current ripples of iL . Therefore, Lc is the best parameter to adjust the soft-switching range. 3.2. Stress and Losses Analysis In the proposed ZVS BIBBC, no extra voltage stress is introduced by auxiliary circuits. However the BIBBC has higher voltage stress than the buck/boost converter. The maximum voltage of main semiconductor devices (S1 , S2 , D1 , and D2 ) is va + vb in both the traditional buck-boost converter and the proposed converter. Figure 8 shows the current stress analysis for S1 , S2 , D1 , and D2 . Due to

In the proposed ZVS BIBBC, no extra voltage stress is introduced by auxiliary circuits. However the BIBBC has higher voltage stress than the buck/boost converter. The maximum voltage of main semiconductor devices (S1, S2, D1, and D2) is va + vb in both the traditional buck-boost converter and the proposed converter. Figure 8 shows the current stress analysis for S1, S2, D1, and D 2. Due to the soft-switching requirement, ir crosses the 0-axis two times in one period, and has Electronics 2018, 7, 221 9 of 15 large ripples. These large ripples give the S1 and S2 of the proposed BIBBC larger current stress than the traditional CCM BIBBC. In zero-power condition, S1 and S2 have minimum current stress, and the soft-switching requirement, the output 0-axis two times in one period, has large ripples. the current stress increases withir crosses increasing power (whether positiveand power or negative These large ripples give the S and S of the proposed BIBBC larger current stress than the traditional power). In the maximum transmission power, S1 and S2 have maximum current stress. In this 1 2 CCM BIBBC. zero-power condition, condition, theIn maximum absolute valueS1ofand ir isS2 have minimum current stress, and the current stress increases with increasing output power (whether positive power or negative power). In the maximum DTva (2M + Lc − Lr ) irppmaximum = transmission power, S1 and S2 have current stress. In this condition, the maximum absolute (15) ( L + M )( Lr − M ) + ( Lc + M )( L + Lr ) value of ir is DTv a (2M + Lc − Lr ) ic determines the current irppstress = of D1 and D2. The maximum current values for D1 and D2 are(15) ( L + M)( Lr − M) + ( Lc + M)( L + Lr ) vbT (1 − D)( M − Lr ) [ L + Lr + DM − DLr ] ic determines the currenticpstress of D1 and D2 . The maximum current values for D1 and D2 are 1 = ( L + M ) [ ( L + M )( Lr − M ) + ( Lc + M )( L + Lr ) ] (16) −)( DM )( M−−LLr)( )[L L+ DM − DL ] ) r ++ v Tv(1 DL +LM − rDM b T−(1D icpi2cp1 = = (bL+ M)[( L+ M)( Lrr− M)+( Lc + M)(rL+ Lr )] (16) + +( LDL M )( L + Lr ) ] (L + M )(−LLr−)(M v )T[((1L−+ DM )( M L+)M c + r − DM ) icp2 = ( L+b M)[( L+ M)( Lr − M )+( L + M )( L+ L )] r

c

r

Figure 8. Current stress for semiconductor devices. Figure 8. Current stress for semiconductor devices.

The loss of the proposed converter includes three parts: the on-loss and switching loss for S1 and S2 , the auxiliary circuit loss, and the core loss. Thanks to the achieving of ZVS-on and ZVS-off conditions for S1 and S2 , the turn-on loss is eliminated and the turn-off loss is reduced. The on-loss is larger than the traditional CCM BIBBC due to the existence of large ripples of ir . The auxiliary circuit loss is caused by diodes D1 and D2 , and can be reduced using low forward voltage diodes. The core loss is related to the current ripple and the core material. In the proposed converter, ic and ir both have large ripples. So to reduce core losses, low-loss cores should be used. By rational design, the switching loss and the core loss will be reduced by the soft-switching achieving and the use of low loss cores. So for the proposed BIBBC, the conduction loss (the on-loss of S1 and S2 , the on-loss of D1 and D2 ) is dominant. 3.3. Design Guidelines Equation (14) can be used in the actual soft-switching design of the proposed BIBBC. iave can represent the load level of the BIBBC. It is known from (14) that the maximum absolute value of iave can be used to design the soft-switching converter. Thus soft-switching conditions can be guaranteed when the absolute value of iave is smaller than the design value. According to the above soft-switching condition analysis, the design steps are presented: Step 1: Determine the voltage level (va , vb ) and the load level (maximum absolute value of iave ) according to the application environment and the stress analysis in Section 3.2. Then D=

|vb | |v a | + |vb |

(17)

Electronics 2018, 7, 221

10 of 15

Step 2: Snubber capacitors (Cr1 , Cr2 ) are used to reduce the increasing rate of drain-source voltages (VS1 , VS2 ) to obtain ZVS-off conditions. Based on the increasing time and the voltage level, Cr1 and Cr2 can be selected. Lr is the resonant inductor, which is used to compensate the snubber capacitors (Cr1 , Cr2 ). Lr can be designed based on (5). Step 3: Current ripples of iL can be calculated based on i Lpp =

v a DT ( M − Lr )2 + ( Lc + Lr )( L + M) L + M ( L + M )( Lr − M ) + ( Lc + M )( L + Lr )

(18)

If ignoring the magnetic coupling effect, the current ripple equation will be i Lpp =

v a DT L + Lr

(19)

Then, based on the ripple requirement of iL , the initial value of L can be calculated by (19). Step 4: Equation (14) is the soft-switching achieving condition. Based on the above calculation, all parameters except Lc and M are known. Considering k = 0.7, substituting the positive maximum value of iave in the first equation of (14), and substituting the negative minimum value of iave in the second equation of (14), Lc and M can be calculated. Step 5: Based on (18), the final value of L can be calculated. 4. Experimental Results 4.1. Experimental Setup In this section, a 200 W experimental prototype was built to illustrate the features and benefits of the proposed BIBBC. The experimental platform is composed of the experimental prototype, the control signal generator (a XC2267M board, Qianqin Technology, Beijing, China), the DC voltage source, the resistive load, and measuring tools, as shown in Figure 9. The main experimental parameters of the components of the experimental prototype are presented in Table 1. This experimental platform uses the open-loop method to test the experimental prototype in the voltage level of 70 V to 70 V. Switching waveforms of main voltages and currents are measured by voltage probes, current probes (CP8150A and CP9012S by CYBERTEK, ShenZhen ZhiYong Electronics Co., Ltd., Shenzhen, Guangdong, China), and by oscilloscope (TDS 2024C by Tektronix, Tektronix, Inc., Beaverton, OR, USA). The efficiency is measured by the power analyzer Yokogawa WT1800 (Yokogawa Test & Measurement, Musashino-shi, Tokyo, Japan). These measuring tools have appropriate precisions to reduce the effect of measurement errors on the experimental results. To prove the superiority of the proposed converter, efficiency measurement results are compared to a traditional BIBBC respectively with CCM and TCM. Table 1. Proposed converter parameters. Parameter

Value

Parameter

Value

va vb D f L Lr D1 , D2

DC 70 V DC 70 V 0.5 100 kHz 159.2 µH 2.4 µH DSSK60-02A

Cr1 , Cr2 C a , Cb M Lc S1 , S2 L, Lc core Lr core

2.2 nF 1000 µF 18.9 µH 4.1 µH IRFP4668 Kool mu Kool mu

Ltd., Shenzhen, Guangdong, China), and by oscilloscope (TDS 2024C by Tektronix, Tektronix, Inc., Beaverton, OR, USA). The efficiency is measured by the power analyzer Yokogawa WT1800 (Yokogawa Test & Measurement, Musashino-shi, Tokyo, Japan). These measuring tools have appropriate precisions to reduce the effect of measurement errors on the experimental results. To Electronics 2018, 7, 221 11 of prove the superiority of the proposed converter, efficiency measurement results are compared to15a traditional BIBBC respectively with CCM and TCM.

Figure Figure 9. 9. Experimental Experimental setup. setup.

4.2. Results Analysis

Table 1. Proposed converter parameters.

Soft-switching achieving: Switching waveforms of the main switches (S1 and S2 ) are presented Parameter Value Parameter Value in Figures 10 and 11. Figure 10 shows the switching waveforms of VGS1 , VGS2 , VS1 , VS2 , iS1 , and iS2 va these waveforms, DC 70 V it can be Cr1seen , Cr2 that the PWM 2.2 nF gate signal V in positive operation. From GS1 rises to v b DC 70 V C a, Cb 1000 a high level after VS1 decreases to 0. The ZVS turn-on condition of S1 isμFobtained. Similar to the 0.5to a high levelMafter V decreases 18.9 μH to 0. The ZVS condition switching waveforms of S1D, VGS2 also rises S2 f 100 kHz L c μH of S2 is also obtained. Figure 11 shows the switching waveforms for S4.1 1 and S2 in negative operation. L 159.2 μH S 1, S2 IRFP4668 ZVS conditions for S1 and S2 were also obtained based on the same analysis method. Based on these r 2.4converter μH L, Lc core Kool conditions mu experimental waveforms,Lthe proposed provides ZVS turn-on for both S1 and D 1, D2 DSSK60-02A L r core Kool mu S2 , whether in positive operation or negative operation. These waveforms are measured at an output power of approximately 115 w. Electronics 2018, 7, x FOR PEER REVIEW 12 of 16 4.2. Results Analysis

Soft-switching achieving: Switching waveforms of the main switches (S1 and S2) are presented in Figures 10 and 11. Figure 10 shows the switching waveforms of VGS1, VGS2, VS1, VS2, iS1, and iS2 in positive operation. From these waveforms, it can be seen that the PWM gate signal VGS1 rises to a high level after VS1 decreases to 0. The ZVS turn-on condition of S1 is obtained. Similar to the switching waveforms of S1, VGS2 also rises to a high level after VS2 decreases to 0. The ZVS condition of S2 is also obtained. Figure 11 shows the switching waveforms for S1 and S2 in negative operation. ZVS conditions for S1 and S2 were also obtained based on the same analysis method. Based on these experimental waveforms, the proposed converter provides ZVS turn-on conditions for both S1 and S2, whether in positive operation or negative operation. These waveforms are measured at an output power of approximately 115 w.

Figure 10. Soft-switching waveforms of the positive operation: (a) Whole waveforms of S1 ; (b) ZVS Figure 10. Soft-switching waveforms of the positive operation: (a) Whole waveforms of S1; (b) ZVS turn-on of S1 ; (c) whole waveforms of S2 ; and (d) ZVS turn-on of S2 . turn-on of S1; (c) whole waveforms of S2; and (d) ZVS turn-on of S2.

Electronics 2018, 7, Soft-switching 221 12 of 15 Figure 10. waveforms of the positive operation: (a) Whole waveforms of S1; (b) ZVS

turn-on of S1; (c) whole waveforms of S2; and (d) ZVS turn-on of S2.

Figure 11. Soft-switching waveforms of the negative operation: (a) Whole waveforms of S1 ; (b) ZVS Figure 11. Soft-switching waveforms of the negative operation: (a) Whole waveforms of S1; (b) ZVS turn-on of S1 ; (c) whole waveforms of S2 ; and (d) ZVS turn-on of S2 . turn-on of S1; (c) whole waveforms of S2; and (d) ZVS turn-on of S2.

Current waveforms: To prove the current waveform analysis in Section 2, current waveforms of ir , Current prove current waveform analysis in Section and 2, current waveforms ic , and iL werewaveforms: measured asTo shown inthe Figure 12. We can see that iL is continuous has a lower ripple of i r , i c , and i L were measured as shown in Figure 12. We can see that i L is continuous than ir and ic . ic is composed of currents in D1 and D2 . Because D1 and D2 will not conduct atand the has samea lowerthe ripple than r and ic. ic is composed of currents in D1 and D2. Because D1 and D2 will not time, current in iD 1 and D2 can be obtained from ic . ir has larger ripples, which are used to provide Electronics 2018, 7, x same FOR PEER REVIEW of 16 conduct at the time, the current in Dare 1 and D2 can with be obtained fromshown ic. ir has larger ripples, soft-switching conditions. These waveforms consistent the analysis in Figures 313 and 5. which are used to provide soft-switching conditions. These waveforms are consistent with the analysis shown in Figure 3 and 5.

Figure 12. Current waveforms: (a) ir in positive operation; (b) ic in positive operation; (c) iL in positive Figure 12. Current waveforms: (a) ir in positive operation; (b) ic in positive operation; (c) iL in positive operation; (d) ir in negative operation; (e) ic in negative operation; and (f) iL in negative operation. operation; (d) ir in negative operation; (e) ic in negative operation; and (f) iL in negative operation.

Efficiency comparison: The measured efficiency of the proposed BIBBC is presented in Figure 13. Efficiency comparison: The BIBBC measured the and proposed BIBBC is presented It is compared with a traditional withefficiency regard to of CCM TCM. The CCM BIBBC hasin theFigure same 13. It is compared with a traditional BIBBC with regard to CCM and TCM. The CCM BIBBC has the L as the proposed BIBBC, and it works under hard-switching conditions. The value of L in the TCM same as18.95 the proposed and it works under hard-switching value ofcurves L in the BIBBCL is µH, and BIBBC, it works under soft-switching conditions. conditions. From theseThe efficiency in TCM BIBBC is 18.95 μH, and it works under soft-switching conditions. From these efficiency curves Figure 13, the proposed BIBBC and the TCM BIBBC have higher efficiency than the CCM BIBBC in in Figure 13, the proposed BIBBC and the TCM BIBBC have higher efficiency than the CCM BIBBC in most output power range. The proposed BIBBC has a higher efficiency at medium and low output power, but a lower efficiency at heavy output power than the TCM BIBBC. With the increase of the output power, the proportion of auxiliary circuit losses in the whole power reduces, efficiency curves rise rapidly. For the proposed BIBBC, efficiency curves of the positive operation

Efficiency comparison: The measured efficiency of the proposed BIBBC is presented in Figure 13. It is compared with a traditional BIBBC with regard to CCM and TCM. The CCM BIBBC has the same L as the proposed BIBBC, and it works under hard-switching conditions. The value of L in the TCM BIBBC 18.95 μH, and it works under soft-switching conditions. From these efficiency curves Electronics 2018, is 7, 221 13 of 15 in Figure 13, the proposed BIBBC and the TCM BIBBC have higher efficiency than the CCM BIBBC in most output power range. The proposed BIBBC has a higher efficiency at medium and low most output power The proposed BIBBC has apower higher efficiency at BIBBC. mediumWith and the lowincrease output output power, but a range. lower efficiency at heavy output than the TCM power, but a lower efficiency at heavy output power than the TCM BIBBC. With the increase of the of the output power, the proportion of auxiliary circuit losses in the whole power reduces, output power, therise proportion auxiliary circuit losses in efficiency the whole curves power reduces, efficiency curves efficiency curves rapidly.ofFor the proposed BIBBC, of the positive operation rise rapidly. For the proposed BIBBC, efficiency curves of the positive operation and the negative and the negative operation are roughly the same. For the CCM BIBBC, the efficiency is operation are roughly same. For the BIBBC, the efficiency is approximately to 83%the in approximately 82% tothe 83% in both theCCM positive operation and negative operation.82% Overall, both the positive operation and negative operation. the proposed an efficiency proposed BIBBC has an efficiency improvement of upOverall, to 10 percent greater BIBBC than thehas CCM BIBBC at improvement of up to 10 percent greater than the CCM BIBBC at heavy load, and has heavy load, and has efficiency improvement of up to 1.5 percent greater than the TCM efficiency BIBBC at improvement of up to 1.5 percent greater than the TCM BIBBC at light load. light load. Proposed BIBBC 96

92

92

88

-220

-180

-140 Output Power

-100

CCM BIBBC

96

Efficiency

TCM BIBBC

Efficiency

CCM BIBBC

Proposed BIBBC

88

84

84

80

80

-60

TCM BIBBC

60

100

140 Output Power

180

220

Figure 13. Measured efficiency: (a) The negative operation and (b) the positive operation.

4.3. Power Supply and Extended Converter 4.3. Power Supply and Extended Converter The power supply used in the experiment is a DC voltage source. Its power characteristics Electronics 7, x supply FOR PEER REVIEW 14 of 16 The 2018, power used in the experiment is a DC voltage source. Its power characteristics are are shown in Figure 14a. It can be seen that the voltage is a constant value (70 V) with small shown in Figure 14a. It can be seen that the voltage is a constant value (70 V) with small fluctuations power is increasing. Figure 14b shows another new similar ZVS BIBBC fluctuations when whenthe theoutput output power is increasing. Figure 14b shows another new similar ZVS by changing the magnetic coupling method of the proposed ZVS BIBBC. This ZVS BIBBC type II BIBBC by changing the magnetic coupling method of the proposed ZVS BIBBC. This ZVS BIBBC has characteristics to the to proposed ZVS BIBBC. It canItbe used as anasoptional topology for typesimilar II has similar characteristics the proposed ZVS BIBBC. can be used an optional topology practical applications. for practical applications. Voltage(10V/div)

Current(1A/div)

Voltage and Current (div)

8 7 6 5 4 3 2 1 0 50

100

150 Output Power (w)

200

250

Figure 14. Power supply and extended converter: (a) Power behaviors and (b) ZVS BIBBC type II.

5. Conclusions 5. Conclusions In to obtain obtain the the bidirectional bidirectionalsoft-switching soft-switchingcapability capabilityand andhigh highefficiency efficiencyfor forthe theBIBBC, BIBBC, In order order to a anew newZVS ZVSBIBBC BIBBCwith withcoupled coupledinductors inductorsisis proposed proposed by by introducing introducing one one diode diode into into the existing the existing soft-switching The operating soft-switching buck-boost buck-boost converter. converter. The operating principle principle analysis, analysis, soft-switching soft-switching achieving achieving condition, and stress analysis are presented for the proposed BIBBC. By giving thethe design guidelines of condition, and stress analysis are presented for the proposed BIBBC. By giving design guidelines

of the new ZVS BIBBC, a 200W experimental prototype was built, and the abovementioned performance analysis verified. From the experimental switching waveforms, both transistors of the ZVS BIBBC achieve ZVS turn-on conditions. From efficiency comparing results, the proposed ZVS BIBBC has higher efficiency than the CCM BIBBC in most output power ranges, and displays an efficiency improvement of up to 10 percent at heavy load. The proposed ZVS BIBBC also has higher

Electronics 2018, 7, 221

14 of 15

the new ZVS BIBBC, a 200W experimental prototype was built, and the abovementioned performance analysis verified. From the experimental switching waveforms, both transistors of the ZVS BIBBC achieve ZVS turn-on conditions. From efficiency comparing results, the proposed ZVS BIBBC has higher efficiency than the CCM BIBBC in most output power ranges, and displays an efficiency improvement of up to 10 percent at heavy load. The proposed ZVS BIBBC also has higher efficiency than the TCM BIBBC in the medium and low power range; an efficiency improvement of up to 1.5 percent at light load can be realized. Author Contributions: Conceptualization, X.-F.C. and Y.Z.; Methodology, X.-F.C.; Software, X.-F.C.; Investigation, X.-F.C., Y.Z.; Validation, X.-F.C., Y.Z.; Writing-Original Draft Preparation, X.-F.C.; Writing-Review & Editing, Y.Z.; Resources, C.Y.; Supervision, C.Y.; Project Administration, C.Y.; Funding Acquisition, Y.Z. Funding: This research was funded by National Key R&D Program of China under Grant number 2017YFB0103700. Conflicts of Interest: The authors declare no conflicts of interest.

References 1.

2.

3.

4.

5. 6. 7.

8.

9.

10. 11. 12.

13.

Moshirvaziri, M.; Li, C.; Trescases, O. A quasi-resonant bi-directional tri-mode DC-DC converter with limited valley current. In Proceedings of the Twenty-Seventh Annual IEEE Applied Power Electronics Conference and Exposition, Orlando, FL, USA, 5–9 February 2012. Du, Y.; Zhou, X.; Bai, S.; Lukic, S.; Huang, A. Review of non-isolated bi-directional DC-DC converters for plug-in hybrid electric vehicle charge station application at municipal parking decks. In Proceedings of the Twenty-Fifth Annual IEEE Applied Power Electronics Conference and Exposition, Palm Springs, CA, USA, 21–25 February 2010. Kong, Z.; Zhu, C.; Yang, S.; Cheng, S. Study of Bidirectional DC-DC Converter for Power Management in Electric Bus with Supercapacitors. In Proceedings of the IEEE Vehicle Power and Propulsion Conference, Windsor, UK, 6–8 September 2006. Kumar, B.V.; Singh, R.K.; Mahanty, R. A modified non-isolated bidirectional DC-DC converter for EV/HEV’s traction drive systems. In Proceedings of the 2016 IEEE International Conference on Power Electronics, Drives and Energy Systems, Trivandrum, India, 14–17 December 2016. Cao, J.; Emadi, A. A New Battery/UltraCapacitor Hybrid Energy Storage System for Electric, Hybrid, and Plug-In Hybrid Electric Vehicles. IEEE Trans. Power Electron. 2012, 27, 122–132. [CrossRef] Kouchachvili, L.; Yaïci, W.; Entchev, E. Hybrid battery/supercapacitor energy storage system for the electric vehicles. J. Power Sources 2018, 374, 237–248. [CrossRef] Capassoa, C.; Lauriab, D.; Veneria, O. Experimental evaluation of model-based control strategies of sodium-nickel chloride battery plus supercapacitor hybrid storage systems for urban electric vehicles. Appl. Energy 2018, 228, 2478–2489. [CrossRef] Veneria, O.; Capassoa, C.; Patalanob, S. Experimental investigation into the effectiveness of a super-capacitor based hybrid energy storage system for urban commercial vehicles. Appl. Energy 2018, 227, 312–323. [CrossRef] Tytelmaier, K.; Husev, O.; Veligorskyi, O.; Yershov, R. A review of non-isolated bidirectional dc-dc converters for energy storage systems. In Proceedings of the 2016 II International Young Scientists Forum on Applied Physics and Engineering (YSF), Kharkiv, Ukraine, 10–14 October 2016. Rodriguez, A.; Vazquez, A.; Rogina, M.R.; Briz, F. Synchronous Boost Converter with High Efficiency at Light Load using QSW-ZVS and SiC MOSFETs. IEEE Trans. Ind. Electron. 2018, 65, 386–393. [CrossRef] Mohammadi, M.R.; Farzanehfard, H. New Family of Zero-Voltage-Transition PWM Bidirectional Converters with Coupled Inductors. IEEE Trans. Ind. Electron. 2012, 59, 912–919. [CrossRef] Mohammadi, M.R.; Farzanehfard, H. Analysis of Diode Reverse Recovery Effect on the Improvement of Soft-Switching Range in Zero-Voltage-Transition Bidirectional Converters. IEEE Trans. Ind. Electron. 2015, 62, 1471–1479. [CrossRef] Mohammadi, M.R.; Farzanehfard, H. A New Family of Zero-Voltage-Transition Nonisolated Bidirectional Converters with Simple Auxiliary Circuit. IEEE Trans. Ind. Electron. 2016, 63, 1519–1527. [CrossRef]

Electronics 2018, 7, 221

14.

15.

16. 17. 18. 19. 20.

21. 22.

23.

15 of 15

Beltrame, R.C.; Zientarski, J.R.R.; Martins, M.L.D.S.; Pinheiro, J.R.; Hey, H.L. Simplified zero-voltagetransition circuits applied to bidirectional poles: concept and synthesis methodology. IEEE Trans. Power Electron. 2011, 26. [CrossRef] Chen, G.; Deng, Y.; Chen, L.; Hu, Y.; Jiang, L.; He, X.; Wang, Y. A Family of Zero-Voltage-Switching Magnetic Coupling Nonisolated Bidirectional DC–DC Converters. IEEE Trans. Ind. Electron. 2017, 64, 6223–6233. [CrossRef] Ahmadi, M.; Shenai, K. New, efficient, low-stress buck/boost bidirectional DC-DC converter. In Proceedings of the IEEE Energytech, Cleveland, OH, USA, 29–31 May 2012. Das, P.; Laan, B.; Mousavi, S.A.; Moschopoulos, G. A nonisolated bidirectional ZVS-PWM active clamped dc–dc converter. IEEE Trans. Power Electron. 2009, 24, 553–558. [CrossRef] Das, P.; Mousavi, S.A.; Moschopoulos, G. Analysis and Design of a Nonisolated Bidirectional ZVS-PWM DC–DC Converter with Coupled Inductors. IEEE Trans. Power Electron. 2010, 25, 2630–2641. [CrossRef] Lee, Y.S.; Cheng, G.T. Quasi-Resonant Zero-Current-Switching Bidirectional Converter for Battery Equalization Applications. IEEE Trans. Power Electron. 2006, 21, 1213–1224. [CrossRef] Broday, G.R.; Nascimento, C.B.; Lopes, L.A.C.; Agostini, E. Analysis and simulation of a buck-boost operation in a bidirectional ZVS DC-DC converter. In Proceedings of the International Conference on Electrical Systems for Aircraft, Railway, Ship Propulsion and Road Vehicles & International Transportation Electrification Conference, Toulouse, France, 2–4 November 2016. Zhang, Y.; Sen, P.C. A new soft switching technique for buck, boost and buck-boost converters. IEEE Trans. Ind. Appl. 2003, 39, 1775–1782. [CrossRef] Chen, G.; Deng, Y.; Tao, Y.; He, X.; Wang, Y.; Hu, Y. Topology derivation and generalized analysis of zero-voltage-switching synchronous dc–dc converters with coupled inductors. IEEE Trans. Ind. Electron. 2016, 63, 4805–4815. [CrossRef] Qiu, G.Y.; Luo, X.J. Circuit, 5th ed.; Higher Education Press: Beijing, China, 2006; pp. 126–131. © 2018 by the authors. Licensee MDPI, Basel, Switzerland. This article is an open access article distributed under the terms and conditions of the Creative Commons Attribution (CC BY) license (http://creativecommons.org/licenses/by/4.0/).

A ZVS Bidirectional Inverting Buck-Boost Converter Using Coupled Inductors Xu-Feng Cheng, Yong Zhang * and Chengliang Yin School of Mechanical Engineering, Shanghai Jiao Tong University, Shanghai 200240, China; [email protected] (X.-F.C.); [email protected] (C.Y.) * Correspondence: [email protected]; Tel.: +86-021-3463-6203 Received: 21 August 2018; Accepted: 26 September 2018; Published: 28 September 2018

Abstract: The bidirectional inverting buck-boost converter (BIBBC) has a simple structure and a wide voltage ratio. It can be used in the battery supercapacitor hybrid energy storage system (BSHESS) and the motor drive system. However, the traditional continuous conduction mode (CCM) BIBBC will have severe switching loss. The triangular current mode (TCM) BIBBC can reduce the switching loss, but it will increase core loss and filter capacitance. To solve these problems, this paper proposes a new zero voltage switching (ZVS) BIBBC using a coupled inductor. This ZVS BIBBC will provide ZVS conditions for both transistors whether in positive operation or negative operation. Meanwhile, this ZVS BIBBC has small core losses and filter capacitance, and can be used simply. Finally, experimental results obtained from these BIBBC experimental prototypes are presented to validate the soft-switching achieving and the efficiency improvement performance. Experimental results show that both transistors of the ZVS BIBBC achieve ZVS turn-on conditions. The efficiency of the ZVS BIBBC increased by up to 10 percent compared to the traditional CCM BIBBC at heave load, and by up to 1.5 percent compared to the TCM BIBBC at a light load. Keywords: bidirectional DC/DC converter; inverting buck-boost; soft-switching; coupled inductor

1. Introduction The nonisolated bidirectional DC/DC converter (NIBDC) can be used in the motor drive system and the battery supercapacitor hybrid energy storage system (BSHESS) [1–5]. In the BSHESS, the NIBDC is used to control the power flow between the supercapacitor and the battery. The energy management system of the BSHESS uses the NIBDC to manage and distribute the energy of the BIHESS to obtain two goals: improve battery life and increase vehicle efficiency [6–8]. Commonly-used NIBDCs have two types: The buck/boost converter and the buck-boost converter [9]. These NIBDCs have two operation directions: The positive operation and the negative operation. The buck/boost converter only has the voltage step-down function in positive operation, and only has the voltage step-up function in negative operation. In contrast with the bidirectional buck/boost converter, the bidirectional inverting buck-boost converter (BIBBC) has both voltage step-down and step-up functions whether in positive or negative operation. This means that the BIBBC will improve the performance of the motor drive system and the BSHESS. However, the BIBBC has higher voltage and current stress than the buck/boost converter under the same output voltage and current. Meanwhile the traditional continuous conduction mode (CCM) BIBBC works under hard-switching conditions. These factors introduce serious conducting and switching losses. To improve the efficiency of the BIBBC, the soft-switching technique is required. For the BIBBC, one of switches can always obtain the soft-switching condition. Therefore the key is the soft-switching condition for another switch. The simplest soft-switching technology for the BIBBC is the triangular current mode (TCM) method [10], which provides soft-switching conditions Electronics 2018, 7, 221; doi:10.3390/electronics7100221

www.mdpi.com/journal/electronics

Electronics 2018, 7, 221

2 of 15

for both switches by adjusting the value of the main inductor L. This technology does not use any auxiliary circuitry. However with this technology, the inductor current iL has large current ripples, which will introduce large current stresses, large core losses, and a large filter capacitance. In order to overcome these shortcomings, many new soft-switching technologies are proposed. The zero voltage transition (ZVT) technology is a commonly used method for the BIBBC [11–16]. By adding auxiliary switches, the ZVT technology gives zero voltage switching (ZVS) conditions for the main switches and zero current switching (ZCS) conditions for the auxiliary switches. Some improved ZVT methods use a coupled inductor to reduce core numbers and improve soft-switching performance [11,13,15]. ZVT-based topologies have high efficiency. The main shortcoming is the cost of auxiliary switches and the complex control timing, because the soft-switching condition is dependent on the control timing. The active clamped soft-switching technology was proposed in multiple previous papers [17,18] for the buck/boost converter, and this technology can also be used in the bidirectional buck-boost converter. In this method only one auxiliary switch is used to obtain soft-switching conditions for two main switches. The coupled inductor can also be used in this topology to improve performance [18]. The shortcoming of these active clamped topologies is the cost of auxiliary switches and the complex control timing. In order to reduce the control complexity of soft-switching topologies, some soft-switching technologies without auxiliary switches were proposed previously [19,20]. In these topologies, the auxiliary circuit, composed of inductors and capacitors, is introduced to the BIBBC to obtain soft-switching conditions. These topologies have a simple structure and have no auxiliary switches. However a previously proposed method is based on the special application (battery equalization applications) [19], and another previously proposed method also faces the problem of large current stresses and core losses [20]. For the existing soft-switching BIBBCs, TCM BIBBCs introduces large current stresses, large core losses, and large filter capacitance; ZVT BIBBCs need auxiliary switches and complex control timing. To overcome these shortcomings, this paper proposes a new ZVS BIBBC using a coupled inductor based on the buck-boost converter in literature [21,22], in which the converter can only obtain soft-switching conditions in positive operation. The structural difference between the proposed ZVS BIBBC and the original converter is the introduced diode. With this diode the ZVS BIBBC has a different operation principle to the original converter, and can provide soft-switching conditions for both transistors whether in positive operation or negative operation. The proposed ZVS BIBBC has comprehensive advantages over similar existing converters:

• • • • • • •

Higher efficiency than the CCM BIBBC in most power ranges and higher efficiency than the TCM BIBBC in the medium and low power range; A simpler control method and lower cost than ZVT converters; Lower core losses and filter capacitance than the TCM BIBBC. In short, this paper provides the following contributions: Proposal of a new ZVS BIBBC using a coupled inductor with abovementioned advantages; Detailed theoretical analysis and design guidelines of the new ZVS BIBBC; Experimental analysis and comparison between the proposed ZVS BIBBC and two other BIBBCs.

This paper is organized as follows. Section 2 presents the topology description and operating principle; the soft-switching achieving condition, stress and loss analysis, and design guidelines are given in Section 3. Experimental results and the related analysis are presented in Section 4. Section 5 summarizes the content and contributions of the full paper. 2. Topology and Its Principle 2.1. Proposed Converter The proposed new ZVS BIBBC, which has bidirectional soft-switching capability, is shown in Figure 1. This converter does not use an auxiliary switch and, therefore, the control complexity of the

Electronics 2018, 7, 221 Electronics 2018, 7, x FOR PEER REVIEW

3 of 15 3 of 16

the new ZVS BIBBC is theassame as a traditional CCM BIBBC. Thisisconverter is nonisolated suitable for new ZVS BIBBC is the same a traditional CCM BIBBC. This converter suitable for nonisolated bidirectional DC/DC applications requiring wide voltage The of drawback of the bidirectional DC/DC applications requiring wide voltage ratios. The ratios. drawback the proposed proposed new ZVS BIBBC is the additional loss caused by auxiliary diodes. Nonetheless, the new ZVS BIBBC is the additional loss caused by auxiliary diodes. Nonetheless, the achieving achieving of soft-switching will the improve the efficiency comparing to the hard-switching of soft-switching conditionsconditions will improve efficiency comparing to the hard-switching BIBBC. BIBBC. The proposed ZVSalso BIBBC also operation has two operation directions: Theoperation positive operation and the The proposed ZVS BIBBC has two directions: The positive and the negative negative operation. positive operation, power flow is transferred a to vb. In negative operation. In positiveInoperation, the powerthe flow is transferred from va to vfrom negative operation, b . In v operation, the power flow isfrom transferred vb to in va.Figure As shown Figure 1, theauxiliary soft-switching the power flow is transferred vb to va . from As shown 1, the in soft-switching circuit auxiliary circuit of the proposed BIBBC includes two power diodes, D 1 and D 2 , a coupled inductor of the proposed BIBBC includes two power diodes, D1 and D2 , a coupled inductor Lc , and a resonance Lc, and aLresonance r. The main the new ZVS BIBBC includes transistors S1 inductor circuit ofLthe new ZVScircuit BIBBCof includes two transistors S1 and S2two , a main inductor r . The maininductor and , a main capacitors inductor L,Cr1 two snubber capacitors r1 and Cr2,Cand two filter capacitors C a and C b . C r1 L, twoS2snubber and Cr2 , and two filter C capacitors and C . C and C are connected to a r1 r2 b and C r2 are connected to transistors S 1 and S 2 in parallel, respectively. L r is used to compensate transistors S1 and S2 in parallel, respectively. Lr is used to compensate negative effects of Cr1 and Cr2 negative of Cr1 The and coupled Cr2 on ZVS-on conditions. The coupled Lc2, and auxiliaryZVS-on diodes on ZVS-oneffects conditions. inductor Lc , and auxiliary diodesinductor D1 and D will provide D1 and D2for will provide ZVS-on conditions S 1 negative (the positive operation) and S 2 (the negative conditions S1 (the positive operation) and Sfor (the operation). Other symbols are defined 2 operation). arevoltage definedvalues, as follows. a and vbacross are the voltage values, the as follows. vaOther and vbsymbols are the DC ic is thevcurrent Lc , iDC current acrossic L,isand L is the across L c , i L is the current across L, and i r is the current across L. icurrent is the current across L. r

Figure 1. Proposed zero voltage switching (ZVS) bidirectional inverting buck-boost converter (BIBBC). Figure 1. Proposed zero voltage switching (ZVS) bidirectional inverting buck-boost converter In the following sections, the mathematical model of the new ZVS BIBBC will be presented. (BIBBC).

All variables are International System of Units. Based on the circuit conduction state of the ZVS BIBBC, proposed sections, ZVS BIBBC have fourmodel operation intervals byBIBBC ignoring charging and In the following the will mathematical of the new ZVS willthe be presented. All discharging of snubber capacitors. Equivalent of these intervals are of shown in Figure 2. variables areprocess International System of Units. Based oncircuits the circuit conduction state the ZVS BIBBC, These equivalent circuits canwill be used build the mathematical model of the the newcharging ZVS BIBBC. the proposed ZVS BIBBC have tofour operation intervals by ignoring and For Interval I,process the differential equations of currents (ic , iLcircuits , and irof ) are discharging of snubber capacitors. Equivalent these intervals are shown in Figure 2. These equivalent circuits can be used to build the mathematical model of the new ZVS BIBBC. −v a ( M− Lr )−vb ( Lc + M) k L1 = didtL of =currents For Interval I, the differential , i)+( L, and ir))(are ( L+ M)( Lr(i −cM Lc + M L + Lr ) equations v ( L+ L )+v ( L+ M)

k = dic = ( L+ M)(a L − Mr )+( Lb + M)( L+ L ) (1) c1 didtL r − L ) − cv ( Lc + M r) −v ( M = dir = −v a (aL+ M)−rvb ( L+bLc + 2M ) kk L1 = dt −MM)+( ) +L(c L +)(ML+)(LLr )+ Lr ) dt =( L( L++M M)( )(L Lr − +cM r1 di v (L + L ) + v (L + M ) = c = L anda L . Ifr k is bthe coupling coefficient, then M2 = k2 LL(1) kc1 between where M is the mutual inductance c. dt ( L + M )( Lrc− M ) + ( Lc + M )( L + Lr ) For Interval II, they are di −va ( L + M ) − vb ( L + Lc + 2 M ) k = r = r1 dtdi ( L + M )( Lr −−M ( LLcr )+ M )( L + Lr ) v ()L+c + k = dtL = ( L+ M)( L − Mb )+( Lc + M )( L+ Lr ) r L2 ) dic coupling coefficient, then M2 = k2LL(2) c. where M is the mutual inductance between L and Lcv. bIf( Mk−isLrthe k c2 = = dt ( L+ M)( Lr − M)+( Lc + M)( L+ Lr ) For Interval II, they are −vb ( Lc + M ) k = dir = r2

dt

( L+ M)( Lr − M)+( Lc + M)( L+ Lr )

Electronics 2018, 7, 221

diL −vb ( Lc + Lr ) = kL 2 = dt ( L M )( L M ) + ( Lc + M )( L + Lr ) + − r dic vb ( M − Lr ) = kc 2 = dt ( L + M )( L − M ) + ( Lc + M )( L + Lr ) r di −vb ( Lc + M ) kr 2 = r = dt ( L + M )( Lr − M ) + ( Lc + M )( L + Lr )

(2) 4 of 15

Figure 2. Equivalent circuits of operation intervals: (a) Interval I; (b) Interval II; (c) Interval III; and (d) Figure 2. Equivalent circuits of operation intervals: (a) Interval I; (b) Interval II; (c) Interval III; and (d) Interval IV. Interval IV.

For Interval III, they are For Interval III, they are v a ( Lc + M )+vb ( M− Lr ) k = di L = LcLr+−M + vLbc(+MM− M))+( )( LL+ kL3 = diLdt= ( L+vM a ()( r )Lr ) L3 −v a ( L+ M)−vb ( L+ Lr ) dic dt ( L M )( L M ) ( L M )( L+L ) + − + + k = = (3) c3 dt ( L+ M)( Lrr − M)+( Lc +c M)( L+ Lr ) r v−av( L(+LL+ 2M )+ v ( L + M ) k =didic r = c +M ) − vbb( L + Lr ) a dt= ( L+ M)( Lr − M)+( Lc + M)( L+ Lr ) (3) kr3 c3 = ( )( ) dt L + M L − M + ( Lc + M )( L + Lr ) r di va ( L + Lc + 2 M ) + vb ( L + M ) For Interval IV, they are kr 3 = r = dt ( L + M )( Lr − M ) + ( Lc + M )( L + Lr ) v a ( L c + Lr ) di L k = = L4 dt ( L+ M)( Lr − M)+( Lc + M)( L+ Lr ) For Interval IV, they are − v ( M − Lr ) (4) k c4 = didtc = ( L+ M)( L − Ma )+( L + r c M )( L + Lr ) vvaa((LLcc++ML)r ) k =didiL r = dt = ( L+ M )( L − M)+( L + M )( L+ L ) r4 L4 = dt ( L + M )( Lrr − M ) + (cLc + M )( Lr + Lr ) dic −va ( M − Lr ) 2.2. Positive Operation = (4) kc 4 = dt ( L + M )( L − M ) + ( Lc + M )( L + Lr ) r To describe the operation principle clearly, this section gives the analysis of voltage and current dir va ( Lc + M ) = of the positive kr 4 = (T) waveforms in one switching period operation. As shown in Figures 3 and 4, dt ( L + M )( L − M ) + ( Lc + M )( L + Lr ) the voltage and current waveforms of the proposedr ZVS BIBBC can be divided into eight modes based on the circuit conduction state. Figure 3 gives gate signal waveforms (VGS1 and VGS2 ) and drain-source 2.2. Positive Operation voltage waveforms (VS1 and VS2 ) respectively for S1 and S2 , and also gives main current waveforms (iL , ir , and ic ). In Figure 3, D is the duty cycle of the gate signal (VGS1 ) of S1 . Figure 4 gives circuit To describe the operation principle clearly, this section gives the analysis of voltage and conduction states of these modes. In positive operation, the mean value of iL will be positive, and the current waveforms in one switching period (T) of the positive operation. As shown in Figure 3 and energy is transferred from va to vb . If the load current is large enough (all waveforms of iL are above the Figure 4, the voltage and current waveforms of the proposed ZVS BIBBC can be divided into eight time-axis), iL will be continuous. D1 and D2 will not conduct at the same time. ir will be bidirectional modes based on the circuit conduction state. Figure 3 gives gate signal waveforms (VGS1 and VGS2) in DT and (1 − D)T will provide soft-switching conditions for S1 and S2 . The detailed analysis of each and drain-source voltage waveforms (VS1 and VS2) respectively for S1 and S2, and also gives main mode is presented as follows. current waveforms (iL, ir, and ic). In Figure 3, D is the duty cycle of the gate signal (VGS1) of S1. Figure Mode 1 (t –t1 , Figure 4a): At the beginning of this mode (t0 ), S1 is turned off by the low-level of 4 gives circuit 0conduction states of these modes. In positive operation, the mean value of iL will be VGS1 . After t0 the changing of VS1 and VS2 is slow due to the existence of Cr1 and Cr2 . The ZVS-off positive, and the energy is transferred from va to vb. If the load current is large enough (all condition of S1 is obtained. iL and ir are positive and start to decrease. ic is negative and starts waveforms of iL are above the time-axis), iL will be continuous. D1 and D2 will not conduct at the to increase. same time. ir will be bidirectional in DT and (1 − D)T will provide soft-switching conditions for S1 Mode 2 (t1 –t2 , Figure 4b): In this mode VS2 decreases to 0 at t1 , and then is kept to 0 due to the and S2. The detailed analysis of each mode is presented as follows. conduction of the body diode of S2 . Mode 1 (t0–t1, Figure 4a): At the beginning of this mode (t0), S1 is turned off by the low-level of Mode 3 (t2 –t3 , Figure 4c): Because VS2 is 0 at t2 , S2 conducts at ZVS-on condition. In this mode VGS1. After t0 the changing of VS1 and VS2 is slow due to the existence of Cr1 and Cr2. The ZVS-off the changing trend of waveforms of iL , ir , and ic is same to Mode 1 and Mode 2. Mode 4 (t3 –t4 , Figure 4d): At t3 , the current across D1 decreases to 0, and then D1 turns off. The current across D2 starts to increase from 0, therefore, D2 turns on. ic is crossing the time-axis and become positive. The increasing rate of ic slows. The decreasing rate of iL and ir also decrease. When ic is equal to iL , ir starts to be negative.

Mode 3 (t2–t3, Figure 4c): Because VS2 is 0 at t2, S2 conducts at ZVS-on condition. In this mode the changing trend of waveforms of iL, ir, and ic is same to Mode 1 and Mode 2. Mode 4 (t3–t4, Figure 4d): At t3, the current across D1 decreases to 0, and then D1 turns off. The current across D2 starts to increase from 0, therefore, D2 turns on. ic is crossing the time-axis and become Electronicspositive. 2018, 7, 221The increasing rate of ic slows. The decreasing rate of iL and ir also decrease. When 5 of 15 ic is equal to iL, ir starts to be negative.

Electronics 2018, 7, x FOR PEER REVIEW

6 of 16

Figure 4. Operating modes in positive operation: (a) Mode 1: t0–t1; (b) Mode 2: t1–t2; (c) Mode 3: t2–t3; (d) Mode 4: t3–t4; (e) Mode 5: t4–t5; (f) Mode 6: t5–t6; (g) Mode 7: t6–t7; and (h) Mode 8: t7–t8.

2.3. Negative Operation

Figure 3. Key waveforms in positive operation. Figure 3. Key waveforms in positive operation.

Mode 5 (t4–t5, Figure 4e): S2 is turned off at the beginning of this mode (t4). Similar to mode 1, the changing of VS1 and VS2 is also slow. The ZVS-off condition for S2 is achieved. After t4, iL and ir start to increase. ic starts to decrease. Mode 6 (t5–t6, Figure 4f): VS1 decreases to 0 at t5, and is clamped to 0 due to the conduction of the body diode of S1. iL, ic, and ir have the same state as Mode 5. Mode 7 (t6–t7, Figure 4g): Because VS1 is kept at 0, S1 starts to conduct at the ZVS-on condition at t6. When ic is equal to iL, ir starts to become positive. The conducting state in this mode is the same as Mode 6. Mode 8 (t7–t8, Figure 4h): At t7, the current across D2 decreases to 0, and then D2 turns off. And the current across D1 starts to increase from 0, therefore, D1 turns on. ic is crossing the time-axis and becomes negative. The decreasing rate of ic reduces. The rising rate of iL and ir also reduce. Similar toFigure the positive operation, the negative operation also has eight modes. Figure 5 presents the 4. Operating modes in positive operation: (a) Mode 1: t0 –t1 ; (b) Mode 2: t1 –t2 ; (c) Mode 3: t2 –t3 ; key voltages and current waveforms, Figure 6 presents the circuit conductive states of the (d) Mode 4: t3 –t4 ; (e) Mode 5: t4 –tand 5 ; (f) Mode 6: t5 –t6 ; (g) Mode 7: t6 –t7 ; and (h) Mode 8: t7 –t8 . negative operation. Comparing the negative operation to the positive operation, the mean value of iL is negative, and the will beStransferred to vat a. ithe c of beginning the negative operation sameto state Mode 5 (t 4e): of this mode has (t4 ).the Similar mode 1, 4 –tenergy 5 , Figure 2 is turned off as thethepositive operation. i r moves to the negative direction compared to the positive operation. changing of VS1 and VS2 is also slow. The ZVS-off condition for S2 is achieved. After t4 , iL and ir Therefore, zero crossing position of ir (mode 3 and mode 8) is different from the positive start tothe increase. ic starts to decrease. operation Mode (mode6 4(t5and mode 7). detailed mode ofisthe negative refer theof the –t6 , Figure 4f):AVS1 decreases to 0analysis at t5 , and clamped to 0operation due to thecan conduction modebody analysis of of theS1positive operation 2.2. as Mode 5. diode . iL , ic , and ir have in theSection same state Mode 7 (t6 –t7 , Figure 4g): Because VS1 is kept at 0, S1 starts to conduct at the ZVS-on condition at t6 . When ic is equal to iL , ir starts to become positive. The conducting state in this mode is the same as Figure 5. Key waveforms in negative operation. Mode 6. Mode 8 (t7 –t8 , Figure 4h): At t7 , the current across D2 decreases to 0, and then D2 turns off. And the current across D1 starts to increase from 0, therefore, D1 turns on. ic is crossing the time-axis and becomes negative. The decreasing rate of ic reduces. The rising rate of iL and ir also reduce.

Figure 4. 7,Operating modes in positive operation: (a) Mode 1: t0–t1; (b) Mode 2: t1–t2; (c) Mode 3: t2–t3;6 of 15 Electronics 2018, 221 (d) Mode 4: t3–t4; (e) Mode 5: t4–t5; (f) Mode 6: t5–t6; (g) Mode 7: t6–t7; and (h) Mode 8: t7–t8.

2.3. Negative Negative Operation Operation 2.3. Similar to operation, the the negative operation also has Figure 5Figure presents Similar tothe thepositive positive operation, negative operation alsoeight hasmodes. eight modes. 5 the key voltages and current waveforms, and Figure 6 presents the circuit conductive states of the presents the key voltages and current waveforms, and Figure 6 presents the circuit conductive negative Comparing theComparing negative operation to the operation positive operation, the mean value of ithe L is states of operation. the negative operation. the negative to the positive operation, negative, and the energy will be transferred to v . i of the negative operation has the same state as the a c mean value of iL is negative, and the energy will be transferred to va. ic of the negative operation has positive operation. i moves to the negative direction compared to the positive operation. Therefore, the same state as ther positive operation. ir moves to the negative direction compared to the positive the zero crossing position ir (mode 3 and mode of 8) is the positive operationfrom (mode operation. Therefore, the of zero crossing position ir different (mode 3 from and mode 8) is different the4 and mode 7). A detailed mode analysis of the negative operation can refer the mode analysis of the positive operation (mode 4 and mode 7). A detailed mode analysis of the negative operation can positive operation in Section 2.2. refer the mode analysis of the positive operation in Section 2.2.

Electronics 2018, 7, x FOR PEER REVIEW

7 of 16

Figure 6. Operating modes in negative operation: (a) Mode 1: t0–t1; (b) Mode 2: t1–t2; (c) Mode 3: t2–t3; (d) Mode 4: t3–t4; (e) Mode 5: t4–t5; (f) Mode 6: t5–t6; (g) Mode 7: t6–t7; and (h) Mode 8: t7–t8.

3. Converter Analysis and Design 3.1. Soft-Switching Conditions

Figure 5. Key waveforms in negative operation. Figure 5. Key waveforms in negative operation.

The introduction of Cr1 and Cr2 can reduce operation: the rising(a)rate of 1: VS1t –t and VS2 to provide passive ZVS-off Figure 6. Operating modes in negative Mode 0 1 ; (b) Mode 2: t1 –t2 ; (c) Mode 3: t2 –t3 ; conditions for S 1 and S2. But the existence of Cr1 and Cr2 has an adverse effect on achieving ZVS-on (d) Mode 4: t3 –t4 ; (e) Mode 5: t4 –t5 ; (f) Mode 6: t5 –t6 ; (g) Mode 7: t6 –t7 ; and (h) Mode 8: t7 –t8 . conditions. Therefore, the resonant inductor Lr is used to compensate the capacitive feature of switches (S1 and S2) introduced by Cr1 and Cr2. Based on the capacitor and inductor energy storage formula [23], the compensation energy formula is (Cr1 + Cr 2 )(va + vb ) 2 Lr ir2 = 2 2

(5)

Based on the above operation mode analyses, soft-switching conditions of the proposed ZVS

Figure modes in negative operation: (a) Mode 1: t0–t1; (b) Mode 2: t1–t2; (c) Mode 3: t2–t37; of 15 Electronics 2018,6.7,Operating 221 (d) Mode 4: t3–t4; (e) Mode 5: t4–t5; (f) Mode 6: t5–t6; (g) Mode 7: t6–t7; and (h) Mode 8: t7–t8.

3. 3. Converter Analysis Analysis and and Design Design 3.1. 3.1. Soft-Switching Soft-Switching Conditions Conditions The can reduce the rising rate of VS1S1 and to provide passive The introduction introduction of of CCr1r1 and and CCr2 r2 can reduce the rising rate of V and VVS2 S2 to provide passive ZVS-off conditions for S and S . But the existence of C and C has an adverse r1 r2 1 2 ZVS-off conditions for S1 and S2. But the existence of Cr1 and Cr2 has an adverse effect effect on on achieving achieving ZVS-on conditions. Therefore, the resonant inductor L is used to compensate the capacitive feature of ZVS-on conditions. Therefore, the resonant inductor rLr is used to compensate the capacitive feature switches (S1 and S2 ) introduced by Cr1 on theon capacitor and inductor energy storage r2 . Based of switches (S1 and S2) introduced byand Cr1 Cand Cr2. Based the capacitor and inductor energy formula [23], the compensation energy formula is storage formula [23], the compensation energy formula is 2

2

(CC + )( Crv2 a)(+ va v +bv)b2) LLrririr2 (Cr1 + r1 r2 == 2 22 2

(5) (5)

Based on on the the above above operation operation mode mode analyses, analyses, soft-switching soft-switching conditions conditions of of the the proposed proposed ZVS ZVS Based BIBBC are areshown showninin Figure 7. Figure the ZVS-on condition the positive operation. In BIBBC Figure 7. Figure 7a is7a theisZVS-on condition for the for positive operation. In positive positive operation, S2 willobtain always obtain thecondition. ZVS-on condition. Thecondition ZVS-on condition of Sir1 must is thatbeir operation, S2 will always the ZVS-on The ZVS-on of S1 is that must be at negative at t7b 6. Figure 7b is thecondition ZVS-on for condition for theoperation. negative operation. negative negative t6 . Figure is the ZVS-on the negative In negativeInoperation, S1 will always obtain the ZVS-on condition. The ZVS-on condition of S2 is that ir must be Soperation, 1 will always obtain the ZVS-on condition. The ZVS-on condition of S2 is that ir must be positive at t2 . positive at t2. Then the soft-switching of the proposed BIBBC arebe that ir must at bet6negative Then the soft-switching conditions of conditions the proposed BIBBC are that ir must negative and be at t 6 and be positive at t 2 . positive at t2 .

Figure7.7.ZVS-on ZVS-onachieving achievingconditions: conditions:(a)(a)The Thepositive positiveoperation operationand and(b) (b)the thenegative negativeoperation operation. Figure .

Then Then soft-switching soft-switching achieving achieving equations equations are are at t6 : ir = i L − ic < 0 at t2 : ir = i L − ic > 0

(6)

iave is set as the average value of iL , iL is marked as iL6 at t6 , and iL is marked as iL2 at t2 . iave can be used to represent the load level of the new ZVS BIBBC. Because iave will be roughly equal to the median value of iL , iL can be estimated by (

i L6 = i ave + i L2 = i ave +

k L1 (t3 −t0 )+k L2 (t4 −t3 ) 2 k L3 (t7 −t4 )+k L4 (t8 −t7 ) 2

+ k L3 (t6 − t4 ) + k L1 (t2 − t0 )

At t6 , ic is marked as ic6 , and at t2 , ic is marked as ic2 , then ic will be ( ic6 = k c2 (t4 − t3 ) + k c3 (t6 − t4 ) ic2 = k c4 (t8 − t7 ) + k c1 (t2 − t0 )

(7)

(8)

Electronics 2018, 7, 221

8 of 15

Substituting (7) and (8) into (6),the soft-switching achieving equations can be rewritten as at t6 : i ave + at t2 : i ave +

k L1 (t3 −t0 )+(k L2 −2k c2 )(t4 −t3 ) 2 k L3 (t7 −t4 )+(k L4 −2k c4 )(t8 −t7 ) 2

+ (k L3 − k c3 )(t6 − t4 ) < 0 + (k L1 − k c1 )(t2 − t0 ) > 0

(9)

To guarantee the achieving of ZVS-on conditions, the first equation of (9) limits the maximum value of the positive load (the maximum value of iave is positive), and the second equation of (9) limits the maximum value of the negative load (the minimum value of iave is negative). Equation (9) is the initial soft-switching achieving condition of the proposed converter. Because values of the time in (9) are unknown, Equation (9) cannot be used in the actual design. To further simplify (9), setting d1 = t3 − t0 , d2 = t4 − t3 , d3 = t7 − t4 , d4 = t8 − t7 , x1 = d1 /(d1 + d2 ), x2 = d3 /(d3 + d4 ). Then ( d1 + d2 = (1 − D ) T (10) d3 + d4 = DT In one period, the changing of ir and ic is zero. Then kr1 d1 + kr2 d2 + kr3 d3 + kr4 d4 = 0 k c2 d3 + k c3 d3 = 0 k d +k d = 0 c1 1 c4 4 Based on (10) and (11), x1 and x2 are (

x1 = x2 =

(11)

D ( M − Lr ) L+ M (1− D )( M− Lr ) L+ M

(12)

Based on (9) and (10), the soft-switching achieving equation can be rewritten as i ave + i ave +

T (1− D )[k L1 x1 +(k L2 −2k c2 )(1− x1 )] + (k L3 − k c3 )tde < 2 DT [k L3 x2 +(k L4 −2k c4 )(1− x2 )] + ( k L1 − k c1 ) tde > 0 2

0

(13)

tde is the dead time, tde = t6 − t4 = t2 − t0 . Then substituting (1)–(4), and (12) into (13), the softswitching achieving condition is 2(i ave +kr3 tde ) Tvb (1− D ) 2(i ave +kr1 tde ) DTv a

< >

(1−2D )( M− Lr )2 +( L+ M)( Lc +2M− Lr ) ( L+ M)[( L+ M)( Lr − M)+( Lc + M)( L+ Lr )] (1−2D )( M− Lr )2 −( L+ M)( Lc +2M− Lr ) ( L+ M)[( L+ M)( Lr − M)+( Lc + M)( L+ Lr )]

(14)

Equation (14) is the soft-switching limited condition. From (14), we can determine that this equation limits the range of iave from the negative value to the positive value. The negative value of iave represents the negative power flow, and the positive value of iave represents the positive power flow. This soft-switching limited condition gives a load limiting soft-switching condition. For a designed converter, if the absolute value of iave is smaller than the designed iave , the soft-switching conditions will always be obtained. We can also know that a large Lc and small L is beneficial to achieving ZVS-on. However a small L will lead to large current ripples of iL . Therefore, Lc is the best parameter to adjust the soft-switching range. 3.2. Stress and Losses Analysis In the proposed ZVS BIBBC, no extra voltage stress is introduced by auxiliary circuits. However the BIBBC has higher voltage stress than the buck/boost converter. The maximum voltage of main semiconductor devices (S1 , S2 , D1 , and D2 ) is va + vb in both the traditional buck-boost converter and the proposed converter. Figure 8 shows the current stress analysis for S1 , S2 , D1 , and D2 . Due to

In the proposed ZVS BIBBC, no extra voltage stress is introduced by auxiliary circuits. However the BIBBC has higher voltage stress than the buck/boost converter. The maximum voltage of main semiconductor devices (S1, S2, D1, and D2) is va + vb in both the traditional buck-boost converter and the proposed converter. Figure 8 shows the current stress analysis for S1, S2, D1, and D 2. Due to the soft-switching requirement, ir crosses the 0-axis two times in one period, and has Electronics 2018, 7, 221 9 of 15 large ripples. These large ripples give the S1 and S2 of the proposed BIBBC larger current stress than the traditional CCM BIBBC. In zero-power condition, S1 and S2 have minimum current stress, and the soft-switching requirement, the output 0-axis two times in one period, has large ripples. the current stress increases withir crosses increasing power (whether positiveand power or negative These large ripples give the S and S of the proposed BIBBC larger current stress than the traditional power). In the maximum transmission power, S1 and S2 have maximum current stress. In this 1 2 CCM BIBBC. zero-power condition, condition, theIn maximum absolute valueS1ofand ir isS2 have minimum current stress, and the current stress increases with increasing output power (whether positive power or negative power). In the maximum DTva (2M + Lc − Lr ) irppmaximum = transmission power, S1 and S2 have current stress. In this condition, the maximum absolute (15) ( L + M )( Lr − M ) + ( Lc + M )( L + Lr ) value of ir is DTv a (2M + Lc − Lr ) ic determines the current irppstress = of D1 and D2. The maximum current values for D1 and D2 are(15) ( L + M)( Lr − M) + ( Lc + M)( L + Lr ) vbT (1 − D)( M − Lr ) [ L + Lr + DM − DLr ] ic determines the currenticpstress of D1 and D2 . The maximum current values for D1 and D2 are 1 = ( L + M ) [ ( L + M )( Lr − M ) + ( Lc + M )( L + Lr ) ] (16) −)( DM )( M−−LLr)( )[L L+ DM − DL ] ) r ++ v Tv(1 DL +LM − rDM b T−(1D icpi2cp1 = = (bL+ M)[( L+ M)( Lrr− M)+( Lc + M)(rL+ Lr )] (16) + +( LDL M )( L + Lr ) ] (L + M )(−LLr−)(M v )T[((1L−+ DM )( M L+)M c + r − DM ) icp2 = ( L+b M)[( L+ M)( Lr − M )+( L + M )( L+ L )] r

c

r

Figure 8. Current stress for semiconductor devices. Figure 8. Current stress for semiconductor devices.

The loss of the proposed converter includes three parts: the on-loss and switching loss for S1 and S2 , the auxiliary circuit loss, and the core loss. Thanks to the achieving of ZVS-on and ZVS-off conditions for S1 and S2 , the turn-on loss is eliminated and the turn-off loss is reduced. The on-loss is larger than the traditional CCM BIBBC due to the existence of large ripples of ir . The auxiliary circuit loss is caused by diodes D1 and D2 , and can be reduced using low forward voltage diodes. The core loss is related to the current ripple and the core material. In the proposed converter, ic and ir both have large ripples. So to reduce core losses, low-loss cores should be used. By rational design, the switching loss and the core loss will be reduced by the soft-switching achieving and the use of low loss cores. So for the proposed BIBBC, the conduction loss (the on-loss of S1 and S2 , the on-loss of D1 and D2 ) is dominant. 3.3. Design Guidelines Equation (14) can be used in the actual soft-switching design of the proposed BIBBC. iave can represent the load level of the BIBBC. It is known from (14) that the maximum absolute value of iave can be used to design the soft-switching converter. Thus soft-switching conditions can be guaranteed when the absolute value of iave is smaller than the design value. According to the above soft-switching condition analysis, the design steps are presented: Step 1: Determine the voltage level (va , vb ) and the load level (maximum absolute value of iave ) according to the application environment and the stress analysis in Section 3.2. Then D=

|vb | |v a | + |vb |

(17)

Electronics 2018, 7, 221

10 of 15

Step 2: Snubber capacitors (Cr1 , Cr2 ) are used to reduce the increasing rate of drain-source voltages (VS1 , VS2 ) to obtain ZVS-off conditions. Based on the increasing time and the voltage level, Cr1 and Cr2 can be selected. Lr is the resonant inductor, which is used to compensate the snubber capacitors (Cr1 , Cr2 ). Lr can be designed based on (5). Step 3: Current ripples of iL can be calculated based on i Lpp =

v a DT ( M − Lr )2 + ( Lc + Lr )( L + M) L + M ( L + M )( Lr − M ) + ( Lc + M )( L + Lr )

(18)

If ignoring the magnetic coupling effect, the current ripple equation will be i Lpp =

v a DT L + Lr

(19)

Then, based on the ripple requirement of iL , the initial value of L can be calculated by (19). Step 4: Equation (14) is the soft-switching achieving condition. Based on the above calculation, all parameters except Lc and M are known. Considering k = 0.7, substituting the positive maximum value of iave in the first equation of (14), and substituting the negative minimum value of iave in the second equation of (14), Lc and M can be calculated. Step 5: Based on (18), the final value of L can be calculated. 4. Experimental Results 4.1. Experimental Setup In this section, a 200 W experimental prototype was built to illustrate the features and benefits of the proposed BIBBC. The experimental platform is composed of the experimental prototype, the control signal generator (a XC2267M board, Qianqin Technology, Beijing, China), the DC voltage source, the resistive load, and measuring tools, as shown in Figure 9. The main experimental parameters of the components of the experimental prototype are presented in Table 1. This experimental platform uses the open-loop method to test the experimental prototype in the voltage level of 70 V to 70 V. Switching waveforms of main voltages and currents are measured by voltage probes, current probes (CP8150A and CP9012S by CYBERTEK, ShenZhen ZhiYong Electronics Co., Ltd., Shenzhen, Guangdong, China), and by oscilloscope (TDS 2024C by Tektronix, Tektronix, Inc., Beaverton, OR, USA). The efficiency is measured by the power analyzer Yokogawa WT1800 (Yokogawa Test & Measurement, Musashino-shi, Tokyo, Japan). These measuring tools have appropriate precisions to reduce the effect of measurement errors on the experimental results. To prove the superiority of the proposed converter, efficiency measurement results are compared to a traditional BIBBC respectively with CCM and TCM. Table 1. Proposed converter parameters. Parameter

Value

Parameter

Value

va vb D f L Lr D1 , D2

DC 70 V DC 70 V 0.5 100 kHz 159.2 µH 2.4 µH DSSK60-02A

Cr1 , Cr2 C a , Cb M Lc S1 , S2 L, Lc core Lr core

2.2 nF 1000 µF 18.9 µH 4.1 µH IRFP4668 Kool mu Kool mu

Ltd., Shenzhen, Guangdong, China), and by oscilloscope (TDS 2024C by Tektronix, Tektronix, Inc., Beaverton, OR, USA). The efficiency is measured by the power analyzer Yokogawa WT1800 (Yokogawa Test & Measurement, Musashino-shi, Tokyo, Japan). These measuring tools have appropriate precisions to reduce the effect of measurement errors on the experimental results. To Electronics 2018, 7, 221 11 of prove the superiority of the proposed converter, efficiency measurement results are compared to15a traditional BIBBC respectively with CCM and TCM.

Figure Figure 9. 9. Experimental Experimental setup. setup.

4.2. Results Analysis

Table 1. Proposed converter parameters.

Soft-switching achieving: Switching waveforms of the main switches (S1 and S2 ) are presented Parameter Value Parameter Value in Figures 10 and 11. Figure 10 shows the switching waveforms of VGS1 , VGS2 , VS1 , VS2 , iS1 , and iS2 va these waveforms, DC 70 V it can be Cr1seen , Cr2 that the PWM 2.2 nF gate signal V in positive operation. From GS1 rises to v b DC 70 V C a, Cb 1000 a high level after VS1 decreases to 0. The ZVS turn-on condition of S1 isμFobtained. Similar to the 0.5to a high levelMafter V decreases 18.9 μH to 0. The ZVS condition switching waveforms of S1D, VGS2 also rises S2 f 100 kHz L c μH of S2 is also obtained. Figure 11 shows the switching waveforms for S4.1 1 and S2 in negative operation. L 159.2 μH S 1, S2 IRFP4668 ZVS conditions for S1 and S2 were also obtained based on the same analysis method. Based on these r 2.4converter μH L, Lc core Kool conditions mu experimental waveforms,Lthe proposed provides ZVS turn-on for both S1 and D 1, D2 DSSK60-02A L r core Kool mu S2 , whether in positive operation or negative operation. These waveforms are measured at an output power of approximately 115 w. Electronics 2018, 7, x FOR PEER REVIEW 12 of 16 4.2. Results Analysis

Soft-switching achieving: Switching waveforms of the main switches (S1 and S2) are presented in Figures 10 and 11. Figure 10 shows the switching waveforms of VGS1, VGS2, VS1, VS2, iS1, and iS2 in positive operation. From these waveforms, it can be seen that the PWM gate signal VGS1 rises to a high level after VS1 decreases to 0. The ZVS turn-on condition of S1 is obtained. Similar to the switching waveforms of S1, VGS2 also rises to a high level after VS2 decreases to 0. The ZVS condition of S2 is also obtained. Figure 11 shows the switching waveforms for S1 and S2 in negative operation. ZVS conditions for S1 and S2 were also obtained based on the same analysis method. Based on these experimental waveforms, the proposed converter provides ZVS turn-on conditions for both S1 and S2, whether in positive operation or negative operation. These waveforms are measured at an output power of approximately 115 w.

Figure 10. Soft-switching waveforms of the positive operation: (a) Whole waveforms of S1 ; (b) ZVS Figure 10. Soft-switching waveforms of the positive operation: (a) Whole waveforms of S1; (b) ZVS turn-on of S1 ; (c) whole waveforms of S2 ; and (d) ZVS turn-on of S2 . turn-on of S1; (c) whole waveforms of S2; and (d) ZVS turn-on of S2.

Electronics 2018, 7, Soft-switching 221 12 of 15 Figure 10. waveforms of the positive operation: (a) Whole waveforms of S1; (b) ZVS

turn-on of S1; (c) whole waveforms of S2; and (d) ZVS turn-on of S2.

Figure 11. Soft-switching waveforms of the negative operation: (a) Whole waveforms of S1 ; (b) ZVS Figure 11. Soft-switching waveforms of the negative operation: (a) Whole waveforms of S1; (b) ZVS turn-on of S1 ; (c) whole waveforms of S2 ; and (d) ZVS turn-on of S2 . turn-on of S1; (c) whole waveforms of S2; and (d) ZVS turn-on of S2.

Current waveforms: To prove the current waveform analysis in Section 2, current waveforms of ir , Current prove current waveform analysis in Section and 2, current waveforms ic , and iL werewaveforms: measured asTo shown inthe Figure 12. We can see that iL is continuous has a lower ripple of i r , i c , and i L were measured as shown in Figure 12. We can see that i L is continuous than ir and ic . ic is composed of currents in D1 and D2 . Because D1 and D2 will not conduct atand the has samea lowerthe ripple than r and ic. ic is composed of currents in D1 and D2. Because D1 and D2 will not time, current in iD 1 and D2 can be obtained from ic . ir has larger ripples, which are used to provide Electronics 2018, 7, x same FOR PEER REVIEW of 16 conduct at the time, the current in Dare 1 and D2 can with be obtained fromshown ic. ir has larger ripples, soft-switching conditions. These waveforms consistent the analysis in Figures 313 and 5. which are used to provide soft-switching conditions. These waveforms are consistent with the analysis shown in Figure 3 and 5.

Figure 12. Current waveforms: (a) ir in positive operation; (b) ic in positive operation; (c) iL in positive Figure 12. Current waveforms: (a) ir in positive operation; (b) ic in positive operation; (c) iL in positive operation; (d) ir in negative operation; (e) ic in negative operation; and (f) iL in negative operation. operation; (d) ir in negative operation; (e) ic in negative operation; and (f) iL in negative operation.

Efficiency comparison: The measured efficiency of the proposed BIBBC is presented in Figure 13. Efficiency comparison: The BIBBC measured the and proposed BIBBC is presented It is compared with a traditional withefficiency regard to of CCM TCM. The CCM BIBBC hasin theFigure same 13. It is compared with a traditional BIBBC with regard to CCM and TCM. The CCM BIBBC has the L as the proposed BIBBC, and it works under hard-switching conditions. The value of L in the TCM same as18.95 the proposed and it works under hard-switching value ofcurves L in the BIBBCL is µH, and BIBBC, it works under soft-switching conditions. conditions. From theseThe efficiency in TCM BIBBC is 18.95 μH, and it works under soft-switching conditions. From these efficiency curves Figure 13, the proposed BIBBC and the TCM BIBBC have higher efficiency than the CCM BIBBC in in Figure 13, the proposed BIBBC and the TCM BIBBC have higher efficiency than the CCM BIBBC in most output power range. The proposed BIBBC has a higher efficiency at medium and low output power, but a lower efficiency at heavy output power than the TCM BIBBC. With the increase of the output power, the proportion of auxiliary circuit losses in the whole power reduces, efficiency curves rise rapidly. For the proposed BIBBC, efficiency curves of the positive operation

Efficiency comparison: The measured efficiency of the proposed BIBBC is presented in Figure 13. It is compared with a traditional BIBBC with regard to CCM and TCM. The CCM BIBBC has the same L as the proposed BIBBC, and it works under hard-switching conditions. The value of L in the TCM BIBBC 18.95 μH, and it works under soft-switching conditions. From these efficiency curves Electronics 2018, is 7, 221 13 of 15 in Figure 13, the proposed BIBBC and the TCM BIBBC have higher efficiency than the CCM BIBBC in most output power range. The proposed BIBBC has a higher efficiency at medium and low most output power The proposed BIBBC has apower higher efficiency at BIBBC. mediumWith and the lowincrease output output power, but a range. lower efficiency at heavy output than the TCM power, but a lower efficiency at heavy output power than the TCM BIBBC. With the increase of the of the output power, the proportion of auxiliary circuit losses in the whole power reduces, output power, therise proportion auxiliary circuit losses in efficiency the whole curves power reduces, efficiency curves efficiency curves rapidly.ofFor the proposed BIBBC, of the positive operation rise rapidly. For the proposed BIBBC, efficiency curves of the positive operation and the negative and the negative operation are roughly the same. For the CCM BIBBC, the efficiency is operation are roughly same. For the BIBBC, the efficiency is approximately to 83%the in approximately 82% tothe 83% in both theCCM positive operation and negative operation.82% Overall, both the positive operation and negative operation. the proposed an efficiency proposed BIBBC has an efficiency improvement of upOverall, to 10 percent greater BIBBC than thehas CCM BIBBC at improvement of up to 10 percent greater than the CCM BIBBC at heavy load, and has heavy load, and has efficiency improvement of up to 1.5 percent greater than the TCM efficiency BIBBC at improvement of up to 1.5 percent greater than the TCM BIBBC at light load. light load. Proposed BIBBC 96

92

92

88

-220

-180

-140 Output Power

-100

CCM BIBBC

96

Efficiency

TCM BIBBC

Efficiency

CCM BIBBC

Proposed BIBBC

88

84

84

80

80

-60

TCM BIBBC

60

100

140 Output Power

180

220

Figure 13. Measured efficiency: (a) The negative operation and (b) the positive operation.

4.3. Power Supply and Extended Converter 4.3. Power Supply and Extended Converter The power supply used in the experiment is a DC voltage source. Its power characteristics Electronics 7, x supply FOR PEER REVIEW 14 of 16 The 2018, power used in the experiment is a DC voltage source. Its power characteristics are are shown in Figure 14a. It can be seen that the voltage is a constant value (70 V) with small shown in Figure 14a. It can be seen that the voltage is a constant value (70 V) with small fluctuations power is increasing. Figure 14b shows another new similar ZVS BIBBC fluctuations when whenthe theoutput output power is increasing. Figure 14b shows another new similar ZVS by changing the magnetic coupling method of the proposed ZVS BIBBC. This ZVS BIBBC type II BIBBC by changing the magnetic coupling method of the proposed ZVS BIBBC. This ZVS BIBBC has characteristics to the to proposed ZVS BIBBC. It canItbe used as anasoptional topology for typesimilar II has similar characteristics the proposed ZVS BIBBC. can be used an optional topology practical applications. for practical applications. Voltage(10V/div)

Current(1A/div)

Voltage and Current (div)

8 7 6 5 4 3 2 1 0 50

100

150 Output Power (w)

200

250

Figure 14. Power supply and extended converter: (a) Power behaviors and (b) ZVS BIBBC type II.

5. Conclusions 5. Conclusions In to obtain obtain the the bidirectional bidirectionalsoft-switching soft-switchingcapability capabilityand andhigh highefficiency efficiencyfor forthe theBIBBC, BIBBC, In order order to a anew newZVS ZVSBIBBC BIBBCwith withcoupled coupledinductors inductorsisis proposed proposed by by introducing introducing one one diode diode into into the existing the existing soft-switching The operating soft-switching buck-boost buck-boost converter. converter. The operating principle principle analysis, analysis, soft-switching soft-switching achieving achieving condition, and stress analysis are presented for the proposed BIBBC. By giving thethe design guidelines of condition, and stress analysis are presented for the proposed BIBBC. By giving design guidelines

of the new ZVS BIBBC, a 200W experimental prototype was built, and the abovementioned performance analysis verified. From the experimental switching waveforms, both transistors of the ZVS BIBBC achieve ZVS turn-on conditions. From efficiency comparing results, the proposed ZVS BIBBC has higher efficiency than the CCM BIBBC in most output power ranges, and displays an efficiency improvement of up to 10 percent at heavy load. The proposed ZVS BIBBC also has higher

Electronics 2018, 7, 221

14 of 15

the new ZVS BIBBC, a 200W experimental prototype was built, and the abovementioned performance analysis verified. From the experimental switching waveforms, both transistors of the ZVS BIBBC achieve ZVS turn-on conditions. From efficiency comparing results, the proposed ZVS BIBBC has higher efficiency than the CCM BIBBC in most output power ranges, and displays an efficiency improvement of up to 10 percent at heavy load. The proposed ZVS BIBBC also has higher efficiency than the TCM BIBBC in the medium and low power range; an efficiency improvement of up to 1.5 percent at light load can be realized. Author Contributions: Conceptualization, X.-F.C. and Y.Z.; Methodology, X.-F.C.; Software, X.-F.C.; Investigation, X.-F.C., Y.Z.; Validation, X.-F.C., Y.Z.; Writing-Original Draft Preparation, X.-F.C.; Writing-Review & Editing, Y.Z.; Resources, C.Y.; Supervision, C.Y.; Project Administration, C.Y.; Funding Acquisition, Y.Z. Funding: This research was funded by National Key R&D Program of China under Grant number 2017YFB0103700. Conflicts of Interest: The authors declare no conflicts of interest.

References 1.

2.

3.

4.

5. 6. 7.

8.

9.

10. 11. 12.

13.

Moshirvaziri, M.; Li, C.; Trescases, O. A quasi-resonant bi-directional tri-mode DC-DC converter with limited valley current. In Proceedings of the Twenty-Seventh Annual IEEE Applied Power Electronics Conference and Exposition, Orlando, FL, USA, 5–9 February 2012. Du, Y.; Zhou, X.; Bai, S.; Lukic, S.; Huang, A. Review of non-isolated bi-directional DC-DC converters for plug-in hybrid electric vehicle charge station application at municipal parking decks. In Proceedings of the Twenty-Fifth Annual IEEE Applied Power Electronics Conference and Exposition, Palm Springs, CA, USA, 21–25 February 2010. Kong, Z.; Zhu, C.; Yang, S.; Cheng, S. Study of Bidirectional DC-DC Converter for Power Management in Electric Bus with Supercapacitors. In Proceedings of the IEEE Vehicle Power and Propulsion Conference, Windsor, UK, 6–8 September 2006. Kumar, B.V.; Singh, R.K.; Mahanty, R. A modified non-isolated bidirectional DC-DC converter for EV/HEV’s traction drive systems. In Proceedings of the 2016 IEEE International Conference on Power Electronics, Drives and Energy Systems, Trivandrum, India, 14–17 December 2016. Cao, J.; Emadi, A. A New Battery/UltraCapacitor Hybrid Energy Storage System for Electric, Hybrid, and Plug-In Hybrid Electric Vehicles. IEEE Trans. Power Electron. 2012, 27, 122–132. [CrossRef] Kouchachvili, L.; Yaïci, W.; Entchev, E. Hybrid battery/supercapacitor energy storage system for the electric vehicles. J. Power Sources 2018, 374, 237–248. [CrossRef] Capassoa, C.; Lauriab, D.; Veneria, O. Experimental evaluation of model-based control strategies of sodium-nickel chloride battery plus supercapacitor hybrid storage systems for urban electric vehicles. Appl. Energy 2018, 228, 2478–2489. [CrossRef] Veneria, O.; Capassoa, C.; Patalanob, S. Experimental investigation into the effectiveness of a super-capacitor based hybrid energy storage system for urban commercial vehicles. Appl. Energy 2018, 227, 312–323. [CrossRef] Tytelmaier, K.; Husev, O.; Veligorskyi, O.; Yershov, R. A review of non-isolated bidirectional dc-dc converters for energy storage systems. In Proceedings of the 2016 II International Young Scientists Forum on Applied Physics and Engineering (YSF), Kharkiv, Ukraine, 10–14 October 2016. Rodriguez, A.; Vazquez, A.; Rogina, M.R.; Briz, F. Synchronous Boost Converter with High Efficiency at Light Load using QSW-ZVS and SiC MOSFETs. IEEE Trans. Ind. Electron. 2018, 65, 386–393. [CrossRef] Mohammadi, M.R.; Farzanehfard, H. New Family of Zero-Voltage-Transition PWM Bidirectional Converters with Coupled Inductors. IEEE Trans. Ind. Electron. 2012, 59, 912–919. [CrossRef] Mohammadi, M.R.; Farzanehfard, H. Analysis of Diode Reverse Recovery Effect on the Improvement of Soft-Switching Range in Zero-Voltage-Transition Bidirectional Converters. IEEE Trans. Ind. Electron. 2015, 62, 1471–1479. [CrossRef] Mohammadi, M.R.; Farzanehfard, H. A New Family of Zero-Voltage-Transition Nonisolated Bidirectional Converters with Simple Auxiliary Circuit. IEEE Trans. Ind. Electron. 2016, 63, 1519–1527. [CrossRef]

Electronics 2018, 7, 221

14.

15.

16. 17. 18. 19. 20.

21. 22.

23.

15 of 15

Beltrame, R.C.; Zientarski, J.R.R.; Martins, M.L.D.S.; Pinheiro, J.R.; Hey, H.L. Simplified zero-voltagetransition circuits applied to bidirectional poles: concept and synthesis methodology. IEEE Trans. Power Electron. 2011, 26. [CrossRef] Chen, G.; Deng, Y.; Chen, L.; Hu, Y.; Jiang, L.; He, X.; Wang, Y. A Family of Zero-Voltage-Switching Magnetic Coupling Nonisolated Bidirectional DC–DC Converters. IEEE Trans. Ind. Electron. 2017, 64, 6223–6233. [CrossRef] Ahmadi, M.; Shenai, K. New, efficient, low-stress buck/boost bidirectional DC-DC converter. In Proceedings of the IEEE Energytech, Cleveland, OH, USA, 29–31 May 2012. Das, P.; Laan, B.; Mousavi, S.A.; Moschopoulos, G. A nonisolated bidirectional ZVS-PWM active clamped dc–dc converter. IEEE Trans. Power Electron. 2009, 24, 553–558. [CrossRef] Das, P.; Mousavi, S.A.; Moschopoulos, G. Analysis and Design of a Nonisolated Bidirectional ZVS-PWM DC–DC Converter with Coupled Inductors. IEEE Trans. Power Electron. 2010, 25, 2630–2641. [CrossRef] Lee, Y.S.; Cheng, G.T. Quasi-Resonant Zero-Current-Switching Bidirectional Converter for Battery Equalization Applications. IEEE Trans. Power Electron. 2006, 21, 1213–1224. [CrossRef] Broday, G.R.; Nascimento, C.B.; Lopes, L.A.C.; Agostini, E. Analysis and simulation of a buck-boost operation in a bidirectional ZVS DC-DC converter. In Proceedings of the International Conference on Electrical Systems for Aircraft, Railway, Ship Propulsion and Road Vehicles & International Transportation Electrification Conference, Toulouse, France, 2–4 November 2016. Zhang, Y.; Sen, P.C. A new soft switching technique for buck, boost and buck-boost converters. IEEE Trans. Ind. Appl. 2003, 39, 1775–1782. [CrossRef] Chen, G.; Deng, Y.; Tao, Y.; He, X.; Wang, Y.; Hu, Y. Topology derivation and generalized analysis of zero-voltage-switching synchronous dc–dc converters with coupled inductors. IEEE Trans. Ind. Electron. 2016, 63, 4805–4815. [CrossRef] Qiu, G.Y.; Luo, X.J. Circuit, 5th ed.; Higher Education Press: Beijing, China, 2006; pp. 126–131. © 2018 by the authors. Licensee MDPI, Basel, Switzerland. This article is an open access article distributed under the terms and conditions of the Creative Commons Attribution (CC BY) license (http://creativecommons.org/licenses/by/4.0/).