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packaging is currently in progress. C. Jia, J. Bardong, C. Gruber. A. Kenda, A. Binder, M. Kraft. CTR Carinthian Tech Research AG, Europastr. 4/1, 9524 Villach, ...
Wafer-Level Packaging for Harsh Environment Application C. Jia, J. Bardong, C. Gruber. A. Kenda, A. Binder, M. Kraft CTR Carinthian Tech Research AG, Europastr. 4/1, 9524 Villach, Austria

Abstract—A wafer-level chip-scale packaging scheme that can withstand ambient temperature of 600°C and above in long-term operation is proposed. The package comprises a SOI case and a cap wafer. In the device layer of the SOI wafer, flexible springs are formed to fix target chips inside the case, so that the influence of thermal stress can be minimized. The two components arejoined together through wafer bonding process under vacuum condition. Electric connection is established through Pt metallized via in SOI. Initial test results confirm the feasibility of the method.

I. INTRODUCTION AND BACKGROUND Semiconductor components for high temperature application are usually encapsulated in ceramic cases or metal housings. For MEMS devices, the development of a special ceramic packaging is expensive. Metal housing based on heat-resistant alloy provides a reliable and cost-effective packaging for devices running till 400°C. However, at higher temperature, the sealing glass that is commonly used to fix the metal pins in the metal case will gradually become soft and finally leads to packaging failure. Besides, with both methods, it is difficult to realize vacuum sealing that protect the sensitive devices from being attacked by reactive components in the air. On the other hand, for high temperature application, it is necessary to develop an effective method to fix the chips inside the housingwithout introducing too much mechanical stress. This poses another challenge to the packaging procedure. In order to solve these problems, an all-silicon packaging scheme is proposed. In this method, silicon substrate, a stable material which can withstand temperature of at least 800°C without significant oxidation, is used to construct the sensor housing. The housing comprises a sealing cap and a case that is made from SOI wafer. The two components are joined together by using standard wafer bonding process. Fig. 1 shows a cross sectional schematic view of the housing. Silicon is chosen also because both conductor and insulator can be easily formed in it through doping or oxidation processes. II. FABRICATION PROCESS A. SOI Housing Fabrication of the housing starts from a SOI wafer. Because the substrate itself acts as conductor along the electric path, highly doped wafers are used to improve the conductivity. First, a cavity and some micro clips are formed in the handle layer by using plasma or wet etching process. The cavity is used to accommodate the target chip, and the clips are used to fix the chip in the cavity in both lateral and vertical directions, so that the using of rigid connection can be avoided. For this reason, the position, size and shape of the clips are so designed that after insertion of the chip into the cavity, the clips will exert a small

force on the chip, which fix the chip, but does not introduce too much mechanical stress in it. In case of large temperature variation, the flexible clips also alleviate stress caused by mismatch of thermal expansion coefficients between case and chips. In the device layer of the SOI wafer, access holes are formed by using wet etching process. After removal of the mask layer, metallization is then performed to establish electric connections to individual micro clips, so that electric signals can be applied at different ports of the chip. In consideration of its excellent temperature stability, Pt with a thin Ti adhesion layer is used as contact metal.

Fig. 1. Schematic illustration of the all-silicon packaging scheme

B. Assembly and Sealing After the insertion of the chip into the cavity, a cap wafer is bonded on the chip holder to seal the chip into the package. The bonding is performed in a vacuum chamber so that the influence of reactive components in air at elevated temperature can be minimized. After bonding, the wafer is diced into chips for further testing. Two dummy packages without active chips inside were tested in an oven at normal air pressure at 600°C for 5 hours. After annealing, the packaging was investigated through different inspection tools. Both samples withstood the annealing process, which indicates that the packaging method is feasible for high temperature application. Electric characterization of the packaging is currently in progress.