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Effect Compact Modeling in MOS Devices. Gaspard Hiblot, Tapas Dutta, Quentin Rafhay, Joris Lacord, Madjid Akbal, Frédéric Boeuf, Member, IEEE, and Gérard ...
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IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 62, NO. 1, JANUARY 2015

Accurate Boundary Condition for Short-Channel Effect Compact Modeling in MOS Devices Gaspard Hiblot, Tapas Dutta, Quentin Rafhay, Joris Lacord, Madjid Akbal, Frédéric Boeuf, Member, IEEE, and Gérard Ghibaudo, Fellow, IEEE

Abstract— In this paper, the boundary conditions at the edges of the junctions are discussed, and their consequences on the compact modeling of short-channel effects (SCEs) in MOSFETs are investigated. It is first shown that the previous voltagedoping transform (VDT) potential model does not agree with the simulation results when the impact of lightly doped drain regions or thin spacers are considered. A solution is then proposed to correct the channel potential model using more accurate boundary conditions at the edges of the channel, which consist eff in calculating an accurate effective built-in potential value Vbi at the source and at the drain. The impact of these improved boundary conditions on compact models of SCEs is investigated. It is shown that the previous VDT models of drain-induced barrier lowering and subthreshold swing for all types of fully depleted devices can be very simply corrected to finely agree with the simulations without fitting parameters. These models finally allow to investigate the impact of the doping concentration of the junctions on the device performance. Index Terms— Compact model, double gate (DG), effective built-in potential, fully depleted, junctions, nanowire (NW), short-channel effects (SCEs).

I. I NTRODUCTION

O

VER the years, the subthreshold OFF-state current (IOFF ) has become a growing concern, to the point where it presently constitutes a severe limiting factor of the devices performance. It is therefore critical to accurately model the short-channel effects (SCEs) of modern MOSFETs, which are

Manuscript received July 17, 2014; revised October 3, 2014 and November 4, 2014; accepted November 5, 2014. Date of current version December 29, 2014. This work was supported in part by the NOODLES Project under Grant ANR-13-NANO-0009 and in part by the COMPOSE3 Project under Grant 619325. The review of this paper was arranged by Editor M. J. Kumar. G. Hiblot is with STMicroelectronics, Crolles 38926, France, and also with the Laboratoire d’Hyperfréquences et de Caractérisation, Institute of Microelectronics, Electromagnetism and Photonics, Grenoble 38016, France (e-mail: [email protected]). T. Dutta, Q. Rafhay, and G. Ghibaudo are with the Laboratoire d’Hyperfréquences et de Caractérisation, Institute of Microelectronics, Electromagnetism and Photonics, Grenoble 38016, France (e-mail: [email protected]; [email protected]; [email protected]). J. Lacord is with the Laboratoire d’Électronique des Technologies de l’Information, Commissariat à l’énergie Atomique, Grenoble 38000, France (e-mail: [email protected]). M. Akbal is with STMicroelectronics, Crolles 38926, France, and also with the Laboratory of Microelectronics Technology, Grenoble Institute of Technology, Grenoble 38031, France (e-mail: [email protected]). F. Boeuf is with STMicroelectronics, Crolles 38926, France (e-mail: [email protected]). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TED.2014.2368395

the main cause of IOFF increase, to carry out projections of the potential performances of emerging device options and architectures. Compact models of SCEs dedicated to this task have largely evolved from charge sharing [1] to polynomial potential models [2]. Many effects have been included, such as the boundary condition at the edge of the depletion region [2], [3], 3-D architectures [4], [5], influence of doping profile [6], and the role of the conductive path [7]. However, the question of the boundary conditions at the junctions has remained mostly unexplored. Indeed, several models have been reported [8]–[10], which have shown an excellent accuracy with simulations where the potentials at the edges of the channel are set to arbitrary values. Nevertheless, very few works include the impact of the depletion regions in the junctions. This point is empirically treated in [11] using an effective value of the drain to source voltage Vds . In [12], the depletion in the lightly doped drain (LDD) regions has also been considered, but using an iterative computation procedure. A new method has recently been introduced in [13] to correctly treat the voltage boundary condition at the junction ends of the channel. This approach has recently been used in [14] for junctionless MOS transistors and [15], [16] for tunneling fieldeffect transistors, where an accurate description of the field is mandatory. In MOSFET devices, [13] has shown that these voltage drops at the junction edges have a major impact on the value of the calculated drain-induced barrier lowering (DIBL) and the subthreshold swing (SS). It is demonstrated here that these voltage drops are the origins of the fitting parameter of the voltage-doping transform (VDT) model presented in [17] and required to match the simulation results. Therefore, it is necessary to correctly include these accurate boundary conditions in the VDT compact models of SCEs, which are used in the MASTAR [18] platform to estimate the performance of different device architectures and options. To achieve this, Section I presents the concept of Vbi,eff effect and its inclusion in the framework of the VDT models, discriminating two different approximations of the channel potential. In the following section, new VDT electrostatic models for SCEs will be derived with the Vbi,eff correction. The model is then extended to consider the spacer thickness, which has not been carried out before. The following section will be dedicated to the validation of these models with TCAD simulations. Finally, the consequences on device performance are described in Section VII.

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HIBLOT et al.: ACCURATE BOUNDARY CONDITION FOR SCE COMPACT MODELING

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According to the parabolic approximation, the potential expression can be cast in the following form: φ(y) = ν · (y − yv )2 + φv

(1)

where φv is the minimum of the potential in the channel, also defined as the virtual cathode potential, yv its position in the channel, and ν is a parameter specific to the VDT. Throughout this paper, the y-direction refers to the longitudinal source/drain direction, as shown in Fig. 5. The expression of the parameter ν in the potential equation (1) has been derived in [19] as ν=

Fig. 1. Electrostatic potential in a DG. The dashed lines represent the VDT potential obtained assuming no voltage drop at the junctions. The continuous lines represent the VDT potential corrected with the Vbi,eff .

II. E FFECTIVE B UILT-I N P OTENTIAL IN THE VOLTAGE -D OPING T RANSFORM A PPROACH A. Systematic Difference in Electrostatic Potential Between Simulations and Analytical Model Most of the SCEs models are deduced from the 2-D electrostatic potential φ(x, y), which is obtained by solving a simplified Poisson equation in the channel of a MOSFET, with potential boundary condition fixed at the source/channel and channel/drain interface. Most of these potential models use φ(y = 0) = Vbi and φ(y = L g ) = Vbi + Vds as boundary conditions [8], [9], [11], [19]. Unless the source and drain doping Nsd exceeds a few 1020 cm−3 , these potential values are generally not reached right at these interfaces, even if this doping concentration remains much larger than the one in the channel. The cause of these significant voltage drops at these positions (φ(y = 0) = Vbi and φ(y = L g ) = Vbi + Vds ) is that the usual p-n junction potential model is actually not valid in the channel of the MOSFET, as the gate electric field strongly controls the potential in the channel. This can result in important inaccuracies when the VDT potential is compared against the simulations made with TCAD Sentaurus, as shown in Fig. 1 for a double-gate (DG) MOSFET. It is, however, possible to correct the potential model by introducing effective S D and Vbi,eff using the values of the junctions potentials Vbi,eff same approach, as in [13]. As shown in Fig. 1, the corrected potential represented with a continuous line fits the simulation results when using effective built-in potentials. The computation of these effective built-in potentials in the framework of the VDT model will be described in the following section. B. Inadequacy of the Parabolic Expression Two approximations of the channel potential have been presented for the VDT model: the parabolic one [19] and the exponential one [20]. The exponential VDT is known to feature a higher accuracy than the parabolic one [21]. It will be shown here that the exponential formulation of the VDT is S D . and Vvi,eff also preferable to evaluate Vbi,eff

∗ Vds L 2g

∗ is equal to [19] where Vds 2   ∗ S D Vds = Vbi,eff − φv + Vbi,eff − φv

(2)

(3)

which highlights here the use of the effective built-in potentials. Using the same approach as in [13], the effective built-in potential is deduced from the continuity of the field induced by the depletion layer in the source and drain, and by the field resulting from the potential variation described by (1). For the sake of readability, the case where no bias is applied to the S D , = Vbi,eff drain (Vds = 0) is presented here. In that case, Vbi,eff S ν = 4 (Vbi,eff − φv )2 /L 2g , and yv = L g /2. The field induced by the depletion in the junction can be expressed as [13]   2q Nsd  S E dep (y = 0) = Vbi − Vbi,eff . (4) ch The electric field can also be computed by deriving (1) at y = 0. Equating the two expressions (field continuity) leads S to an equation in Vbi,eff whose solution is  S 2 Vbi,eff = φv + αpara + 2αpara (Vbi − φv ) − αpara (5) where αpara is a parameter specific to the Vbi,eff correction, homogeneous to a voltage. Its expression is: αpara = q Nsd L 2g /(4ch ). However, (5) shows that, according to the parabolic model, the depletion regions on both sides of the junctions should disappear when the gate length L g tends to infinity, although the simulations show that they are still present. This nonphysical behavior of (5) therefore suggests that the parabolic approximation of the potential is not suitable for the calculation of the effective built-in potential. The following section hence details the use of the exponential approximation to derive the fields at the junctions. C. Derivation of the Model Using the Exponential Approximation Instead of a parabolic potential, the VDT can also be applied with an exponential approximation of the potential [20]–[22]. In that case, the potential is expressed as φ =a+b·

sinh((L g − y)/λ) sinh(y/λ) +c· sinh(L g /λ) sinh((L g )/λ)

(6)

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where a, b, and c are unknown parameters, and λ is the electrostatic length. There is a variety of different expressions for λ [8], [10], [23], [24] depending on the approximation chosen to solve Poisson equation. This concept has experimentally been proven to be physically meaningful in [25] and [26]. In this paper, the value of λ is derived according to the VDT model (Appendix) to ensure a consistency of the modeling framework. The formula obtained  ch Ach (7) λ= Cox is equivalent to the ones from the literature. In (7), Cox is the oxide capacitance and Ach is the cross-sectional area of the channel, whose value hence changes with the device architecture. In planar devices, both Ah and Cox are proportional to the width W. Since only the ratio Ach /Cox matters for the computations presented here, W will be implicitly omitted in silicon-on-insulator (SoI) and DG MOS. As a result, Ach reduces to the channel thickness tch in that case. The values of b and c from (6) can be immediately obtained by applying the boundary conditions at the junctions edges  sinh((L g − y)/λ)  S −a · φ = a + Vbi,eff sinh(L g /λ)  sinh(y/λ)  D . (8) + Vbi,eff − a · sinh(L g /λ) Assuming that L g /λ is large enough (typically more than 5), the terms related to the junctions can be neglected near the virtual cathode position yv sinh((L g − yv )/λ) ≈0 sinh(L g /λ)

(9)

sinh(yv /λ) ≈ 0. sinh(L g /λ)

(10)

and

It can hence be deduced from φ(y = yv ) = φv that a is equal to the virtual cathode potential φv . Using the same approach as in Section II-B, the field continuity leads to  S Vbi,eff − φv  2q Nsd  S = Vbi − Vbi,eff . (11) λ ch The solution of (11) is thus the same as in the previous section, but with a modified α term, where L g is replaced by the electrostatic length λ  S 2 + 2α (V − φ ) − α . = φv + αexp (12) Vbi,eff exp bi v exp Similarly, at the drain, the effective built-in potential is  D 2 + 2α (V + V − φ ) − α Vbi,eff = φv + αex (13) exp bi ds v exp p where αexp is the new Vbi,eff parameter, deduced with the exponential approximation. Its expression is q Nsd λ2 . (14) ch Compared with αpara derived in Section II-B, the dependence in L g is replaced by a dependence on the electrostatic αexp =

length λ in (14), the physical inconsistency brought by the parabolic model in the long-channel case is hence solved. For the sake of clarity, αexp will be referenced as α, since αpara has been shown to be wrong in Section II-B. III. I MPLEMENTATION IN S HORT-C HANNEL E FFECTS MASTAR M ODEL Using the formula of effective built-in potential obtained in the previous section, new equations are derived in this section for the threshold voltage roll-off (SCE), the DIBL, and the SS. A. SCE and DIBL Following the approach of [17] and [27], the virtual cathode potential is assumed to be constant across the channel. In that ∗ is also constant. The reduction in threshold voltage case, Vds Vth induced by SCEs can then be deduced by applying Gauss law at the virtual cathode position, assuming full depletion [17], [27]

 d 2φ ∗A − ch 2ch Vds Ach d y2 ch =− . (15) Vth = Cox Cox L 2g Equation (15) can be solved using (3) in the case of weak Vds for the SCE and large Vds for the DIBL. For the SCE, Vds is negligible, which leads to the following expression [17], [27]:  ch Ach  S V − φsth Cox L 2g bi,eff

ch Ach 2 =8 α + 2α(V − φ ) − α . bi sth Cox L 2g

SCE(L g ) = 8

(16)

On the contrary, for the DIBL, Vds is supposed to be large enough to dominate the other terms and the corresponding equation is (using a few approximations) [17], [27]  ch Ach  D S Vbi,eff − Vbi,eff 2 Cox L g ch Ach 2 α + 2α(Vbi + Vds − φsth ) =2 Cox L 2g

− α 2 + 2α(Vbi − φsth ) .

DIBL(L g ) = 2

(17)

φsth is the value of φv near threshold, and given in [17]. B. Subthreshold Swing Model The inclusion of the Vbi,eff effect in the SS model is now presented. The SS can be expressed as [17], [28]   dφv −1 kT ln(10) SS = (18) q dv g where v g is the gate voltage. To find an expression for dφv /dv g , Gauss law is applied to deduce the following:   d 2φ q Nch − ch 2 . (19) Cox (v g − φs ) = dy Ach

HIBLOT et al.: ACCURATE BOUNDARY CONDITION FOR SCE COMPACT MODELING

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The relationship between v g and φv can be inferred from (2) and (19) Cox (v g − φv ) = q Nch Ach − 2 Ach ch

∗ Vds . L 2g

(20)

dφv /dv g can now be obtained by deriving (20), with the S D ∗ ) are now particularity that Vbi,eff and Vbi,eff (included in Vds functions of the virtual cathode potential, and must be derived with the other terms   dφv −1 dv g ⎛   D S D d Vbi,eff d Vbi,eff d Vbi,eff = 1 + ⎝2 − − + 1− dφv dφv dφv  ⎞    D S S Vbi,eff − φv Vbi,eff − φv d Vbi,eff ⎠ · + 1− · dφv D S Vbi,eff − φv Vbi,eff − φv ·

Ach ch . Cox L 2g

(21)

D /dφ and d V S An explicit expression of d Vbi,eff v bi,eff /dφv hence has to be found to obtain a closed-form expression of the SS. This is achieved by deriving (12) and (13) with respect to φv , which leads to S d Vbi,eff

dφv

=1− 

1 1+2·

(Vbi −φv ) α

.

Symmetrically at the drain D d Vbi,eff

dφv

=1− 

1 1+2·

(Vbi +Vds −φv ) α

.

The final expression of the SS is therefore SS =

kT ln(10) q ⎡ ⎛ × ⎣1 + ⎝ 

1 1+2·

(Vbi −φv ) α



+ 1+2·

1 (Vbi +Vds −φv ) α

Fig. 2. (a) Schematic of the electric field near the junction where the region D in function of spacer under the spacer is fully depleted. (b) Voltage Vbi,eff thickness for different doping concentrations.

the field at the contact border is not null and (4) does not hold anymore. As an extension of [13], this section presents the inclusion of the thin spacer case in the models previously derived. To solve this specific case, the fields at the edges of the spacers E sp,S/D [shown in Fig. 2(a) on the source side] have to be determined. To carry this out, it is at first necessary to reintegrate Poisson equation to obtain q Nsd dφ d 2 φ dφ q Nsd d 2φ = − ⇒ =− 2 2 dy ch dy dy d y ch

(23)

where Nsd of the n-type LDD is an absolute value. Integrating (23) over the spacer thickness tsp at the source yields −tsp −tsp dφ d 2 φ dφ q Nsd d y = − dy 2 dy dy d y ch 0 0 2 ⇒ E dep (y = 0)2 − E sp,S  2q Nsd  S Vbi − Vbi,eff . (24) = ch

As the field at the contact E sp,S/D is not necessarily zero, if the depletion regions in the source and drain extend through becomes an unknown that (22) the width of the spacer, E sp,S/D S/D must be eliminated to obtain Vbi,eff . This can be achieved by directly solving Poisson equation under the spacer, assuming that it is fully depleted, which leads to

D Vbi,eff − φv

q Nsd tsp ch S Vbi,eff − φv q Nsd − = tsp λ ch

E sp,S = E dep (y = 0) −

1 + · S ⇒ E sp,S (25) Vbi,eff − φv 1 + 2 · (Vbiα−φv )  ⎞ ⎤ S where the field continuity at the junction edge was applied to Vbi,eff − φv A  1 ⎠ · ch ch ⎦ . eliminate E dep (y = 0), as in Section II. E sp,S can hence be +  · Cox L 2g D S Vbi,eff − φv 1 + 2 · (Vbi +Vαds −φv ) removed using (24) and (25), to obtain an equation in Vbi,eff , whose solution is When the SS is evaluated using (22), φv is fixed at 2 + 2 tsp φ 2Vbi + qNchsd tsp φ f = (kT /q) ln(Na /n i ), to ensure that the channel is in v S

λ . V = (26) bi,eff depletion. tsp 2 λ +1 IV. T HIN S PACER C ASE In all the derivations presented above, it was implicitly considered that the spacers were sufficiently large to provide enough space for the depletion regions, so that the built-in potentials could reach their full values. However, if the spacers become thinner than the depletion layers in source and drain,

Note that all the above equations are valid only if tsp < tdep . tdep itself can be deduced from the value of the field given by (11)   Vbi − φv −1 . (27) tdep = λ 1+2 α

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Fig. 3. DIBL of DG MOS devices with a spacer thickness of tsp = 3 nm. (a) Nsd = 5 · 1018 cm −3 . (b) Nsd = 1 · 1019 cm −3 .

Fig. 4. SS of DG MOS with a spacer thickness tsp (a) Nsd = 5 · 1018 cm −3 . (b) Nsd = 1 · 1019 cm −3 .

= 3 nm.

S When tsp is replaced by tdep in (25), it is found that Vbi,eff follows (12), thus guaranteeing the continuity between the S large- and thin-spacer regime. The general equation for Vbi,eff can hence be expressed as ⎧ tsp q Nsd 2 φv ⎪ ⎪2Vbi +  ch tsp +2

λ ⎪ , if tsp < tdep ⎨ tsp 2 +1 S λ Vbi,eff = (28) ⎪ φv − α ⎪ ⎪ ⎩ + α 2 + 2α(Vbi − φv ), otherwise

and a similar expression can be deduced at the drain ⎧ tsp q Nsd 2 tsp +2 λ φv ⎪ ⎪2(Vbi +Vds )+ t ch

⎪ , if tsp < tdep ⎨ sp 2 λ +1 D Vbi,eff = (29) ⎪ φv − α ⎪ ⎪ ⎩+ α 2 + 2α(V + V − φ ), otherwise bi ds v D S (respectively, Vbi,eff ) thus depends on the the value of Vbi,eff spacer thickness tsp : when tsp reaches tdep , the expression D derived in Section II is valid. However, below tdep , Vbi,eff tends toward the value at the contact: Vbi + Vds , as shown in Fig. 2(b). To demonstrate the validity of the thin spacer model, simulation of only DG has been carried out, indeed it will be shown in Section V that the treatment of other architectures is similar. The results obtained with and without considering the thin spacer correction are shown in Fig. 3(a) and (b) (the oxide thickness tox is set to 1 nm, and tch to 5 nm). When the spacer thickness reduces, it can be observed that the S D corrected values of Vbi,eff and Vbi,eff improve the agreement of the DIBL calculated with the model and the one obtained with simulations. The new expression of the SS is deduced from (21), where S D /dφ are now given by (28) and (29), /dφv and d Vbi,eff dVbi,eff v which leads to S/D

d Vbi,eff dφv

tsp = . tsp + λ

Fig. 5. Schematics of the structure simulated. (a) DG MOS, (b) SoI MOS, and (c) cross section of the NW MOS simulated.

V. VALIDATION OF THE N EW M ODELS : C OMPARISON W ITH S IMULATIONS A. Description of the Simulations To validate the new models proposed in Sections III and IV, the classical drift-diffusion equation and Poisson equation are solved using TCAD Sentaurus. The channel doping has been chosen equal to 1016 cm−3 (this value will also be used for the other architectures). To illustrate the universality of the Vbi,eff approach, three different architectures were simulated: DG, SoI, and cylindrical nanowire (NW) MOS. Schematics of these three structures with their corresponding dimensions are shown in Fig. 5(a) for the DG MOS, Fig. 5(b) for the SoI MOS, and finally Fig. 5(c) shows a cross section of the NW MOS simulated. B. Double Gate

(30)

Once again, the corrected model obtained using (30) is more accurate, as shown in Fig. 4(a) and (b).

DG = t In the specific case of a DG device, Ach ch and = 2ox /tox . To demonstrate the necessity to include effective built-in potentials, the model from [17] used without fitting parameters and the new models with the Vbi,eff DG Cox

HIBLOT et al.: ACCURATE BOUNDARY CONDITION FOR SCE COMPACT MODELING

Fig. 6. (a) DIBL and (b) SS of a DG MOS with tch = 5 nm and tox = 1 nm as a function of the gate length.

Fig. 7. Threshold voltage roll-off (SCE) in function of the gate length for different junction doping concentrations. (a) DG. (b) NW.

corrections are compared with the simulations in Fig. 6. The junction doping concentration is 1019 cm−3 . The symbols represent the simulations and the lines represent the different models. The VDT model from [17] without fitting parameter, and the VDT model corrected with Vbieff. From this figure, it is clear that when the Vbi,eff correction is included in the model, no fitting parameters are needed. With the inclusion of the Vbi,eff correction in the VDT model, the SCE and DIBL are now analytical functions of the junctions doping. To confirm the validity of (16), (17), and (22), the models are compared against the simulations for the same device geometry (tox = 1 nm and tch = 5 nm), but with different values for Nsd . The results are plotted in Figs. 7(a), 8(a), and 9(a). It can be observed that the Vbi,eff correction allows the models to include explicitly the impact of junction doping, which was not correctly accounted for before. C. Cylindrical NW This case is very similar to the DG, except that the channel 2 cross section is now: ANW ch = π Rch , and the oxide capacitance NW = 2π / ln(1 + t /R ), R becomes: Cox ox ox ch ch being the channel radius. The NW MOS simulated here features a diameter (2Rch ) of 5 nm, and an oxide thickness tox of 2 nm. The models are compared for different junction dopings

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Fig. 8. DIBL in function of the gate length for different junction doping concentrations. (a) DG. (b) NW.

Fig. 9. SS in function of the gate length for different junction doping concentrations. (a) DG. (b) NW.

against the simulations shown in Figs. 7(b), 8(b), and 9(b), which confirm the validity of the model. D. SoI The channel cross section is the same as in a DG MOS, hence ASoI ch = tch . On the other hand, the oxide capacitance is SoI =  /t . For half the value of the one of the DG MOS: Cox ox ox the SoI model, additional terms due to the coupling with the Buried OXide (BOX) [27], [29] are included in the model, in addition to the equations presented in Section III. The geometrical parameters are the same as for the DG MOS (Section V-B), while the BOX thickness tbox is set to 25 nm, which is a standard industrial value. The models are compared against simulations shown in Fig. 10, considering three different junction doping levels as in Section V-B to investigate the validity of the Vbi,eff correction, which depends on Nsd . Once again, the simulations confirm the validity of the model, indeed the p-value obtained from Student test was found to be below 5% in all cases. Similar to the DG and NW cases, there remains nonetheless a noticeable difference for large and low values of Nsd , while the best fit appears at Nsd = 1020 cm−3 . The following two reasons may be invoked to explain this. 1) The electrostatic model employed here is rather simple, and therefore less accurate than other more sophisticated

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The curves shown in Fig. 11, which have been calculated using the MASTAR platform [31], have been obtained by varying the LDD doping from 1018 to 1021 cm−3 . The device chosen here is a DG with a gate length of 20 nm, an Equivalent Oxide Thickness of 1 nm, with tch taking values of 5, 7, and 10 nm. When the doping of the LDD regions increases, the access resistances decrease, enhancing the Ieff current, but also the IOFF due to the subsequent enhancement of SCEs. It can also be observed that the targeted IOFF of 10 pA/μm specified by the ITRS for low-power applications can be achieved by playing either on the LDD doping or the channel thickness. This result is expected as an LDD doping increase has the same effect as a tch increase, i.e., a decrease of the access resistances at the cost of an increase of SCEs. Finally, it is well known that the doping level of the junctions also influences the inner fringe capacitance [32]. Theoretically, the resulting difference in parasitic capacitance should be considered to evaluate the device performance, but it has been demonstrated in [33] that its impact on circuit performance was minor compared with the resulting difference in drivability. VII. C ONCLUSION Fig. 10. (a) SCE, (b) DIBL, and (c) SS of an SoI device with tbox = 25 nm, for different junction doping concentrations.

In this paper, it has been demonstrated that the Vbi,eff method allows to extend the validity of the VDT potential model, leading to better agreements with TCAD simulations, without any fitting procedure. The expression of Vbi,eff has been at first derived using the exponential VDT. The impact of Vbi,eff on SCEs was then discussed for DG, NW, and SoI MOS, and the resulting models have been fully validated against TCAD simulations. It has been demonstrated that the Vbi,eff model should be corrected if the doping is low and if the spacer is thin, for which a new model has been developed and presented. Finally, the consequences on Ieff /IOFF has been described using the MASTAR platform, which demonstrates that the doping level could be optimized using this metric. A PPENDIX D ERIVATION OF λ

Fig. 11. Ieff versus IOFF of a DG, obtained with MASTAR by letting the LDD doping move from 1018 to 1021 cm −3 .

models mentioned in the introduction. This may account for the loss of precision occurring at short channel lengths for Nsd = 1021 cm−3 , where SCEs are particularly strong. 2) For weak doping levels (Nsd = 1019 cm−3 ), the depletion depth in the junction may be large enough to be affected by the gate outer fringing field, which was not considered in the derivations presented here. In addition, the field in the junctions may not be perfectly horizontal, which limits the validity of (4). VI. I MPACT ON D EVICE P ERFORMANCE An insight into the resulting impact of the LDD doping on the performance of the device is provided by the Ieff (IOFF ) plot, Ieff being the effective current defined in [30].

Deriving the general expression of the exponential VDT potential, exposed in (6), yields c b sinh((L g − y)/λ) sinh(y/λ) d 2φ + 2 · = 2 · d y2 λ sinh(L g /λ) λ sinh(L g /λ) (φ − a) . (31) = λ2 ∗ , introduced in [19], can be cast The effective doping Nch under the following form using (31): ∗ q Nch q Nch d 2φ q Nch (φ − a) = − 2 = − . ch ch dy ch λ2

(32)

The effective depletion charge is obtained by integrating the effective doping over the channel thickness. Performing the exact integration of (32) is not trivial since the dependence of φ and a on x is not explicit. It is hence assumed that a and φ are constant along the channel, which is consistent with the approach used to derive the electrostatic models employed in

HIBLOT et al.: ACCURATE BOUNDARY CONDITION FOR SCE COMPACT MODELING

this paper [17]. The effective depletion charge Q ∗dep can then be expressed as ∗ q Nch (φ − a) = Q dep − ch Ach . (33) ch λ2 Gauss theorem is finally applied using the expression of the effective depletion charge previously obtained

Q ∗dep = ch Ach

Cox (v g − φ) = Q ∗dep = Q dep − ch Ach

(φ − a) . λ2

(34)

Equation (34) is derived with respect to y −Cox

ch Ach dφ dφ =− . dy λ2 d y

(35)

The lateral field dφ/dy is not zero along the whole channel, thus λ can be deduced from (35) as  ch Ach λ= . (36) Cox R EFERENCES [1] R. C. Varshney, “Simple theory for threshold-voltage modulation in short-channel m.o.s. transistors,” Electron. Lett., vol. 9, no. 25, pp. 600–602, Dec. 1973. [2] Q. Xie, J. Xu, and Y. Taur, “Review and critique of analytic models of MOSFET short-channel effects in subthreshold,” IEEE Trans. Electron Devices, vol. 59, no. 6, pp. 1569–1579, Jun. 2012. [3] R. R. Troutman, “Ion-implanted threshold tailoring for insulated gate field-effect transistors,” IEEE Trans. Electron Devices, vol. 24, no. 3, pp. 182–192, Mar. 1977. [4] A. Kloes, M. Weidemann, and B. Iniguez, “Analytical 3D approach for modeling the electrostatic potential in triple-gate SOI MOSFETs,” in Proc. IEEE Conf. Electron Devices Solid-State Circuits (EDSSC), Dec. 2007, pp. 103–106. [5] A. Tsormpatzoglou, D. H. Tassis, C. A. Dimitriadis, G. Ghibaudo, N. Collaert, and G. Pananakakis, “Analytical threshold voltage model for lightly doped short-channel tri-gate MOSFETs,” Solid-State Electron., vol. 57, no. 1, pp. 31–34, 2011. [6] T. Skotnicki and P. Bouillon, “Electrical performances of retrograde versus conventional profile MOSFETs,” in Symp. VLSI Technol., Dig. Tech. Papers, Jun. 1996, pp. 152–153. [7] Q. Chen, B. Agrawal, and J. D. Meindl, “A comprehensive analytical subthreshold swing (S) model for double-gate MOSFETs,” IEEE Trans. Electron Devices, vol. 49, no. 6, pp. 1086–1090, Jun. 2002. [8] A. Tsormpatzoglou, C. A. Dimitriadis, R. Clerc, Q. Rafhay, G. Pananakakis, and G. Ghibaudo, “Semi-analytical modeling of shortchannel effects in Si and Ge symmetrical double-gate MOSFETs,” IEEE Trans. Electron Devices, vol. 54, no. 8, pp. 1943–1952, Aug. 2007. [9] A. Klös and A. Kostka, “A new analytical method of solving 2D Poisson’s equation in MOS devices applied to threshold voltage and subthreshold modeling,” Solid-State Electron., vol. 39, no. 12, pp. 1761–1775, 1996. [10] D. J. Frank, Y. Taur, and H.-S. P. Wong, “Generalized scale length for two-dimensional effects in MOSFETs,” IEEE Electron Device Lett., vol. 19, no. 10, pp. 385–387, Oct. 1998. [11] Z.-H. Liu et al., “Threshold voltage model for deep-submicrometer MOSFETs,” IEEE Trans. Electron Devices, vol. 40, no. 1, pp. 86–95, Jan. 1993. [12] J. G. Fossum, P.-C. Yeh, and J.-Y. Choi, “Computer-aided performance assessment of fully depleted SOI CMOS VLSI circuits,” IEEE Trans. Electron Devices, vol. 40, no. 3, pp. 598–604, Mar. 1993. [13] T. Dutta, Q. Rafhay, G. Pananakakis, and G. Ghibaudo, “Modeling of the impact of source/drain regions on short channel effects in MOSFETs,” in Proc. 14th Int. Conf. Ultimate Integr. Silicon (ULIS), Mar. 2013, pp. 69–72.

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