PEDS2009
Achieving ZVS in Inductor-less Half-bridge Piezoelectric Transformer based Resonant Converters E. L. Horsley, N. Nguyen-Quang, M. P. Foster, D. A. Stone Department of Electronic & Electrical Engineering The University of Sheffield, UK Email:
[email protected] Abstract— Inductor-less half-bridge piezoelectric transformer based resonant converters can offer considerable reductions in mass and form factor over their discrete counterparts. This work presents an analytical model for calculating the load and frequency range over which such converters can achieve ZVS given the large input capacitance these transformers typically present.
Piezoelectric transformer
iL
Vdc
Cin
Keywords- Piezoelectric transformer, zero-voltage-switching, resonant power conversion.
I.
R1
L1
C1
1
N Cout
RL
Figure 1. Inductor-less PT-based resonant converter
Since the capacitance that must be charged prior to the high-side MOSFET turning on (and discharged prior to the low-side MOSFET turning on) is much larger than in a discrete converter, the power dissipation that occurs in the switches if a PT-based converter is hard switched is also greater. Therefore it is essential to soft-switch inductor-less PT-based converters if losses and heat dissipation are to be kept low.
INTRODUCTION
Piezoelectric transformers (PTs) allow many of the reactive components in several switch mode power supply (SMPS) topologies to be replaced with a single ceramic component [1]. Since the reactive components in a power electronic circuit are usually the largest and most expensive, the use of PTs in certain SMPS designs can yield significant savings in cost, size, and mass. When operated with a half-bridge inverter, PTbased converters usually take the form of a conventional LCC (series-parallel) converter, either with or without an additional inductor in series with the PT input. Since PTs usually have a relatively large input capacitance, the use of an additional series inductor allows zero voltage switching (ZVS) to be readily achieved, but with the disadvantage of introducing a wound magnetic component. Achieving ZVS without the use of an additional inductor has been demonstrated by several authors, but is dependant upon the size of the input capacitance and the load and frequency range required [2-5].
PTs are usually designed to operate with a load that is matched to the impedance of the output capacitance, the socalled matched load condition R L = 1 (ωC out ) . However, this load condition is also the most difficult with which to achieve ZVS because it tends to minimise the amplitude of the tank current. Reducing the size of the input capacitance allows ZVS to be achieved more easily, but decreases overall power density because it requires the PT to have a larger input section volume. Therefore to maximize the power density of an inductor-less PT, the input section should have the smallest volume (and therefore highest C in ) that still allows ZVS to be obtained over the required load and frequency range.
ZVS is readily achieved in discrete LCC converters because the output capacitance of the MOSFET switches is quite small (hundreds of pF). However, in the inductor-less PT-based converter topology shown in Figure 1, the MOSFET output capacitance is augmented by the large input capacitance of the PT (often several nF). Therefore the amount of charge that must be delivered by the tank current to this augmented capacitance during the dead-time in order to raise the voltage from 0V to the DC link voltage is much larger than in discrete converters. Furthermore, a much larger dead-time is required in order to provide sufficient time for this charge to be delivered. The maximum dead-time that can be used is dictated by the time between the low-side MOSFET turning off and the tank current crossing zero, which in turn is partially dictated by the phase angle at which the tank is operated. Therefore inductorless converters typically have to be operated much further above resonance than their with-inductor counterparts.
Whilst extensive SPICE simulation could be undertaken during the design phase of a PT to ensure that ZVS can be met over the required frequency and load range, the design and optimisation process will be made considerably faster if an analytical model of the ZVS condition is available. This paper describes the development of such a model, verifies it against SPICE simulations and experimental results, and shows how the complete ZVS profile of a PT can be obtained. II.
INDUCTOR-LESS PT-BASED CONVERTER OPERATION
Figure 2 shows the voltage and current waveforms for an inductor-less converter that is just achieving ZVS. The converter is operating with a matched load, and the input capacitance has been sized such that ZVS is only just achieved when operating at the optimum frequency and optimum dead-
446
PEDS2009 time for ZVS. In Figure 2, φ refers to the phase angle between the fundamental components of the input capacitance voltage and the tank current, and ω refers to angular frequency.
When achieving ZVS, the operation of the converter shown in Figure 1 can be split up into 6 modes of operation, 3 per half-cycle. When ZVS is not achieved, modes 2 and 5 are omitted. The voltages, current, and mode sequence for these two cases is shown in Figures 3 and 4 respectively. The deadtimes have been labelled t d . The analysis proceeds under the assumption that ZVS is not achieved because the mode times of the converter are well defined under this condition. Providing the converter is operated such that the dead-times and on-times of the two MOSFETs are equal, only two modes need be considered in order to obtain a steady-state solution for the tank current and input capacitance voltage during mode 1.
0.25 vCin
50
0.2
iL
45
High side vgs
0.15
Low side vgs
40
φ/ω
0.1 0.05
30 25
0
20
-0.05
Current (A)
Voltage (V)
35
15 M2
M3
M4
M5
M6
50
-0.15
45
5
2.994 Time (s)
2.996
2.998
35
0.1
30
0.05
25
0
20
-0.05
15
-0.1
10
-0.15
5
-0.2
0
-0.25
-3
x 10
Figure 2. Steady-state voltage and current waveforms for a converter that can only just achieve ZVS
It can be seen from Figure 2 that the dead-time required to achieve ZVS takes up a large proportion of the total switching period. As the tank current changes considerably during this time, the constant current assumption that is used to analyse discrete converters [6], and which has subsequently been applied to PTs [4, 5], is not accurate for this type of converter.
2.982
2.984
2.986
2.988 Time (s)
Low side vgs
2.99
2.992
2.994 -3
x 10
Figure 3. Steady-state voltage and current waveforms for a converter where ZVS is easily achieved
Whilst the relationship between the tank current and the fundamental component of the input capacitance voltage is immediately known through knowledge of the tank impedance, the time between the zero-crossing of the tank current and the MOSFET switching signals is not. Therefore it is difficult to ascertain the correct time limits over which to integrate the tank current in order to find the change in input capacitance voltage during the dead-time when using a frequency domain approach. In [3], the period over which to integrate was taken as twice the phase shift between the fundamental components of the input capacitance voltage and tank current, but as Figure 2 suggests, this is likely to give an overly optimistic result.
M1
M3
M4
M6
50
40
Voltage (V)
0.25
vCin
45
To address the aforementioned issues, we present a novel, largely time domain analysis of half-bridge inductor-less PTbased converters that allows the ZVS capability of a PT to be evaluated at any frequency, load, and dead-time, without recourse to SPICE simulation. Whilst the analysis will initially consider an AC output topology, the result is equally applicable to DC output topologies via RCFMA [7-9]. The analysis is made on the assumption that the PT behaviour will be dominated by the vibration mode that corresponds to the switching frequency. III.
0.15
-0.25 3
td
td
td
td
iL
0.2
High side vgs
0.15
Low side vgs
35
0.1
30
0.05
25
0
20
-0.05
15
-0.1
10
-0.15
5
-0.2
0
-0.25 2.952
2.954
2.956
2.958 Time (s)
2.96
2.962
Current (A)
2.992
0.2
High side vgs
40
Voltage (V)
2.99
iL
-0.2
0 2.988
0.25
vCin
Current (A)
M1
-0.1 10
2.964 -3
x 10
Figure 4. Steady-state voltage and current waveforms for a converter where ZVS is not achieved
Assuming the loaded quality factor of the converter is relatively high, the equivalent circuits for modes 1 and 3 are as shown in Figure 5, where
ANALYSIS
R x = R1 +
In order to achieve ZVS, the voltage across the input capacitance must reach the DC link voltage before the end of the dead-time period prior to the high-side MOSFET switching on. Therefore an expression to calculate this voltage as a function of converter specification ( Cin , C out , R1 , L1 , C1 , N ), operating frequency, load, and dead-time is developed.
Cx =
447
(
RL
)
N R L ω 2 C out 2 + 1 2
2
(
(1)
)
C1 N 2 R L 2ω 2 C out 2 + 1 2
C1 R L ω C out + N R L ω C out 2 + N 2 2
2
2
2
.
(2)
PEDS2009
vCin
where
Cx
L1
Rx
i
Cin (a) mode 1
L1
Rx
i
K1 =
(R x + α1 L1 )e β t − (R x + β1 L1 )eα t L1 (α 1 − β1 )
(10)
K2 =
e β1td − eα1td L1 (α 1 − β1 )
(11)
Cx
1d
(
1d
) )
(
)
⎛ R xα 1 + L1α 1 2 e β1t d − R x β1 + β1 2 L1 eα1t d ⎜ ⎜ + L β 2 − α 2 + R (β − α ) 1 1 1 x 1 1 K3 = ⎝ C x L1α 1 β1 (α 1 − β1 )
Vdc (b) mode 3
K4 =
Figure 5. Equivalent circuits for inductor-less PT-based converter operation during modes 1 and 3
(
(
) (
⎞ ⎟ ⎟ ⎠
)
α 1 e β1td − 1 − β1 e α1td − 1 + C x L1α 1 β1 (α 1 − β1 ) . C x L1α 1 β1 (α 1 − β1 )
(12)
(13)
B. Analysis of mode 3
Expressions for the tank current during modes 1 and 3 are derived in terms of the initial conditions of modes 1 and 3 respectively. Since the initial conditions for one mode are related to the final conditions of the other mode, the unknown initial conditions in the two modes can be solved to obtain an expression for the tank current during mode 1. Obtaining an expression for the voltage across the input capacitance during mode 1 is then relatively simple and allows the voltage at the end of the dead-time to be found.
With reference to Figure 4, mode 3 begins at t = t d and ends at t = T / 2 , where T is the switching period of the MOSFETs. The current during mode 3 can be expressed as i (t ) = C3eα 2 t + C4 e β 2 t
(14)
where
− C x R x + C x 2 R x 2 − 4C x L1
(15)
A. Analsyis of mode 1 With reference to Figure 4, mode 1 begins at t = 0 and ends at t = t d , where t d is the dead-time between one MOSFET turning off and the other turning on. The current during the first mode can be expressed as
α2 =
i (t ) = C1eα1t + C 2 e β1t
Again, the constants C 3 and C 4 can be found in terms of the initial voltages and currents at the start of mode 3,
β2 =
(3)
where α1 =
− C in C x R x + C in 2 C x 2 R x 2 − 4C in C x 2 L1 − 4C in 2 C x L1
β1 =
(4)
2C in C x L1 2
2
2
2
2C in C x L1
C4 =
2
− Cin C x R x − C in C x R x − 4Cin C x L1 − 4C in C x L1
C3 =
.
i (0)R x + i(0)α 1 L1 + vCx (0) . L1 (α 1 − β1 )
i (t d )R x + i (t d )β 2 L1 + vCx (t d ) + Vdc i(t d )R x + i (t d )α 2 L1 + vCx (t d ) + Vdc L1e β 2td (α 2 − β 2 )
The tank current and C x voltage at the end of mode 1 can then be found in terms of the initial conditions of mode 1 as
(9)
5
Cx
K5 =
vCx (t d ) = K 3i (0) + K 4 vCx (0)
.
(18)
( 2 ) = K i(t ) + K v (t ) + K V v (T ) = K i (t ) + K v (t ) + K V 2
where
(8)
(17)
L1eα 2td (β 2 − α 2 )
iT
(6)
i (t d ) = K1i (0) + K 2 vCx (0 )
(16)
2C x L1
The tank current and C x voltage at the end of mode 3 can then be found in terms of the initial conditions of mode 3 as
(7)
C2 =
− C x R x − C x 2 R x 2 − 4C x L1
(5)
The constants C1 and C2 can be found in terms of the initial voltages and currents in the circuit at the start of mode 1,
i(0)R x + i (0 )β1 L1 + vCx (0) C1 = L1 (β1 − α 1 )
2C x L1
7
448
6 Cx
d
d
8 Cx
(19)
6 dc
d
(20)
9 dc
T T (R x + L1α 2 )e β ( 2 −t ) − (R x + β 2 L1 )eα ( 2 −t ) L1 (α 2 − β 2 ) β (T 2 −t ) α (T 2 −t ) e −e 2
K6 =
d
d
2
d
2
d
L1 (α 2 − β 2 )
2
d
(21)
(22)
PEDS2009 β 2 (T 2 −td ) ⎛ 2 − R x (α 2 − β 2 ) ⎜ L1α 2 + R xα 2 e ⎜ ⎜ − β 2 L + R β e α 2 (T 2 −td ) − L α 2 − β 2 2 1 1 2 2 x 2 K7 = ⎝ C x L1α 2 β 2 (α 2 − β 2 )
(
K8 =
)
(
(
)
α (T −t ) ⎞ β (T −t ) ⎞ ⎞ ⎛ ⎛ ⎛ ⎜ β 2 ⎜1 − e 2 2 d ⎟ − α 2 ⎜ 1 − e 2 2 d ⎟ ⎟ ⎠ ⎝ ⎠⎟ ⎜ ⎝ ⎜ + C L α β (α − β ) ⎟ x 1 2 2 2 2 ⎝ ⎠
where vCin (0) is zero because the low side MOSFET has been on during mode 6. Substituting (3) into (32), followed by (6) and (7) allows the voltage across the input capacitance at the end of the dead-time to be found as
(23)
vCin (t d ) =
(
β2 ⎜ ⎝
)⎞ −α ⎟ ⎠
(
β T −t ⎛ 1− e 2 2 d
2⎜
⎝ C x L1α 2 β 2 (α 2 − β 2 )
( 2)
(25)
( 2)− V
dc
.
Substituting (19) into (26) and (20) into (27) provides a second set of equations that relate the initial conditions of the first mode to the final conditions of the first mode (28)
vCx (0) = − K 7 i (t d ) − K 8 vCx (t d ) − K 9Vdc − Vdc .
(29) IV.
Then, by eliminating i (t d ) and vCx (t d ) from the simultaneous equations (8), (9), (28), and (29), the initial conditions of the first mode are given by
⎛ K5 K 2 K9 + K5 K 2 + K 6 K 4 K9 + K6 K 4 ⎞ ⎟⎟ Vdc ⎜⎜ − K 6 − K 6 K 7 K 2 − K 6 K8 K 4 ⎝ ⎠ i(0 ) = 1 K K K K K K K K K K + + + + ⎛ 5 1 6 3 7 2 7 2 6 3⎞ ⎜ ⎟ K K K K K K K K + + − ⎜ ⎟ 8 4 8 4 5 1 5 2 K8 K3 ⎜− K K K K ⎟ 6 4 7 1 ⎝ ⎠
(30)
⎛ K 6 K 7 K1 + K 8 K 3 K 6 − K 9 − K 9 K 5 K1 ⎞ ⎟⎟ Vdc ⎜⎜ − K 9 K 6 K 3 − K 5 K1 − K 6 K 3 − 1 ⎝ ⎠ vCx (0 ) = ⎛1 + K 5 K 1 + K 6 K 3 + K 7 K 2 + K 7 K 2 K 6 K 3 ⎞ ⎜ ⎟ ⎜ + K 8 K 4 + K 8 K 4 K 5 K1 − K 5 K 2 K 8 K 3 ⎟ ⎜− K K K K ⎟ 6 4 7 1 ⎝ ⎠
(31)
1 Cin
∫
td
0
i (t )dt + vCin (0)
(34)
MODEL VERIFICATION
In order to verify the accuracy of the new model, comparisons were made with SPICE simulations and experimental results from a prototype converter running at constant frequency and constant dead-time. The SPICE model was an idealised one based around voltage controlled switches (without diodes) in place of MOSFETs since this allowed the estimates of vCin (t d ) provided by the model to be verified in cases where ZVS would be achieved. The prototype converter was based around a Transoner® T1-15W radial mode PT, the equivalent circuit component values of which were measured as Cin = 1.89 nF, C out = 1.28 nF, L1 = 10.70 mH, C1 = 166 pF, R1 = 8.54 Ω, and N = 0.934 . The MOSFETs used in the experimental converter were IRF510s, the combined parasitic output capacitance of which was estimated from the datasheet to be around 260pF when the DC link voltage was 50V. Since this capacitance appears in parallel with Cin during Mode 1, the value of Cin used in the model calculations and SPICE simulations was 2.15nF.
Since a complete solution for the current during mode 1 has now been obtained, the voltage across the input capacitance at the end of mode 1 can be found from vCin (t d ) =
(33)
Equation (33), together with (30), (31), (10-13), (21-25), (4-5), and (15-16) allows the voltage across the input capacitance at the end of the dead-time period to be found for a converter with a given set of equivalent circuit component values operating at a given frequency, load, and dead-time, assuming that the MOSFET body diodes do not conduct. Hence, in situations where vCin (t d ) does not exceed the DC link voltage, (33) gives a quantitative figure for the capacitance voltage. When vCin (t d ) is found by (33) to exceed the DC link voltage, then ZVS is achieved and modes 2 and 5 will be entered for some portion of the switching cycle. Therefore, in situations where ZVS is achieved, (33) provides a qualitative measure of the margin by which ZVS is achieved.
(27)
i(0) = − K 5 i(t d ) − K 6 vCx (t d ) − K 6Vdc
)
v (t ) ~ vCin (t d ) = Cin d . Vdc
(26)
vCx (0) = −vCx T
)
Finally, the voltage across the input capacitance at the end of the dead-time can be normalised with respect to the DC link voltage so that a value of 1 is obtained when ZVS is just achieved
C. Solution for the initial conditions of mode 1 Since the dead-times and on-times of the MOSFETs are equal, the initial conditions of the first mode are related to the final conditions of the third mode by i (0) = −i T
(
(
)⎞
⎟ ⎠.
i(0)R x + i (0)β 1 L1 + vCx (0) α1td e −1 L1Cinα 1 (β 1 − α 1 )
i(0)R x + i(0)α 1 L1 + vCx (0 ) β1td + e −1 L1Cin β1 (α 1 − β 1 )
(24)
C x L1α 2 β 2 (α 2 − β 2 )
α T −t ⎛ 1− e 2 2 d
K9 =
)
⎞ ⎟ ⎟ ⎟ ⎠
Figure 6 shows the normalised input capacitance voltage at the end of the dead-time as a function of load resistance when switching at 120.5kHz with dead-time intervals of 1.44μs and a DC link voltage of 50V. It can be seen that the model predictions agree very closely with the idealised SPICE model. Both the SPICE and model predictions are within 3.3% of the
(32)
449
PEDS2009 experimental results around ~ vCin (t d ) = 1 , and within 10.2% at ~ vCin (t d ) = 0.28 . The discrepancy between the simulated and experimental results is most likely due to the influence of spurious vibration modes and changes in the equivalent circuit component values. The equivalent circuit was measured at small signal levels with sinusoidal excitation. However, the excitation level in the converter is much larger, and this is likely to cause an increase in the mechanical loss resistance R1 . Furthermore, harmonics present in the voltage waveform across Cin will excite other modes of vibration within the PT, the effects of which are not included in the standard equivalent circuit. Since the harmonics become more pronounced as the margin by which ZVS is not obtained increases, it is to be expected that the accuracy of the model and SPICE predictions vCin (t d ) are obtained. becomes worse when low values of ~
concave when plotted against R L ; therefore R x increases from its minimum value as R L is increased from 0, reaches its peak value when R L = 1 (ωC out ) , then decreases again as R L is increased further. This in turn means that the amplitude of the tank current tends to be greatest either at short circuit load conditions or open circuit load conditions, and minimum at the matched load condition, R L = 1 (ωC out ) . Since it is the tank current that charges the input capacitance during the dead-time, vCin (t d ) are found at this explains why the highest values of ~ very small or very large load resistances, and why, as stated in [3], the matched load condition is the most difficult with which to obtain ZVS. To further illustrate that the matched load condition is the most difficult with which to achieve ZVS, Figure 8a shows a plot of ~ vCin (t d ) against frequency for the T1-15W device when R L is set to 5 different multiples of the matched load vCin (t d ) for each condition. By looking at the peak value of ~ load condition, it can be seen that of the 5 load conditions shown, the matched load is the most difficult with which to achieve ZVS, assuming a free choice of frequency is permitted. Figure 8b confirms this result by showing only the maximum ~ vCin (t d ) value that can be achieved against multiples of the matched load condition. The implication of this result is that if ZVS can be achieved at the matched load condition, then it will be possible at all values of R L . It should be noted that the optimum value of t d was found prior to each and every vCin (t d ) that was used in Figures 8a and 8b. calculation of ~
1.8 Proposed model SPICE (idealised) Experimental ZVS threshold
1.6
Normalised vCin(td)
1.4
1.2
1
0.8
0.6
0.4
0.2
50
100
150
200 250 Load resistance, RL (Ω)
300
350
400
Figure 6. Change in v~Cin (t d ) with load resistance for the T1-15W PT operating at 120.5kHz switching freqency with 1.44μs dead-time intevals Normalised vCin(td)
OBTAINING THE ZVS PROFILE OF A PT
When analysing the ZVS capabilities of an inductor-less PT-based converter, it is useful to know the input capacitance voltage at the end of the dead-time as a function only of load resistance and frequency. By substituting (30), (31), (10-13), and (21-25) into (33), differentiating with respect to t d , and numerically solving to find the stationary points over the range 0 < t d < T / 2 , the dead-time that yields the maximum value from (33) can be found for a given converter specification, load, and operating frequency. Thus, evaluating (33) over a range of load and frequency combinations using the optimal dead-time for each operating point allows a profile of the inductor-less ZVS capabilities of a PT to be built up.
2
1
0
0 2000
1.2 4000
1.25 6000
1.3
8000 1.35
Frequency (Hz)
5
x 10
10000 Load, RL (Ω)
Figure 7. ZVS profile of T1-15W 0.59
Normalised vCin(td)
0.58
Figure 7 shows the ZVS profile of the T1-15W PT sample, including the effect of the parasitic MOSFET output capacitances. In this figure, the regions where ZVS can be obtained are shown in red. It can be seen that the regions of operation where ZVS can be achieved are very small, with ZVS possible only at very small or very large load resistances. The shape of the R L / N 2 R L 2ω 2 C out 2 + 1 term in (1) is
( (
3
0.57 0.56 0.55 RL=0.75/(w.Cout) RL=0.875/(w.Cout) RL=1/(w.Cout) RL=1.125/(w.Cout) RL=1.25/(w.Cout)
0.54 0.53 0.52 1.25
))
1.26
1.27 1.28 Frequency (Hz)
1.29
1.3 5 x 10
Maximum normalised vCin(td)
V.
4
0.585
0.58
0.575
0.57
0.8
0.9
1 1.1 RL.ω.Cout
1.2
1.3
(a) (b) Figure 8. Variation in v~Cin (t d ) with load condition for the T1-15W PT
450
PEDS2009 The ZVS profile for another radial mode PT, termed T1PP0361, is shown in Figure 9. This PT has the following equivalent circuit component values: Cin = 4.93 nF, C out = 2.70 nF, L1 = 4.48 mH, C1 = 891 pF, R1 = 4.34 Ω, and N = 2.21 . The matched load resistance of this PT is approximately (since it is frequency dependant) 700Ω. From Figure 9 it can be seen that this PT can achieve ZVS at any load resistance, including the region where the load becomes matched to the impedance of the output capacitance.
VI.
A model has been presented for calculating the voltage across the input capacitance of an inductor-less half-bridge PTbased converter at the end of the dead-time preceding the highside MOSFET turning on, thereby providing an indication of whether or not zero-voltage-switching is achieved. The newly presented model has been shown to offer comparable accuracy to SPICE simulations, but takes a fraction of the time required for a SPICE simulation to reach steadystate. A method for calculating the optimum dead-time for a given converter specification at each frequency and load combination has been shown, facilitating the ZVS profile of a PT to be plotted over the required load and frequency ranges.
Comparing Figure 7 and Figure 9, the shape of the ZVS profiles of the two PTs are seen to be very different. Figure 7 indicates that the input capacitance of the T1-15W device is too high for ZVS to be obtained anywhere near the matched load. Since the efficiency of a PT is maximised when operating at the matched load, and since it is usually thermal considerations that limit the output power of a given PT, the maximum output power of the T1-15W PT will be much less in an inductor-less topology (where it has to operate well away from its matched load of around 1kΩ) than in a with-inductor topology (where it is free to operate at the matched load condition).
Since the model allows the optimum size of Cin for a particular PT to found such that ZVS is just obtained over the required operating regions but without compromising power density further than is necessary, it is envisaged that the model will prove to be a useful tool for maximising the power density of PTs that are designed for inductor-less operation. A future paper will develop the model further and show how a design criterion that ensures ZVS is possible over the entire range of load resistances can be derived.
On the other-hand, Figure 9 shows that the input capacitance of the T1-PP0361 device is possibly smaller than it needs to be because ZVS can be obtained over quite a wide range of frequencies, even when R L is selected to be the worst case from a ZVS perspective. Since adjusting the input capacitance of a radial mode PT without adjusting the force factors can only be achieved by adjusting the overall thickness of the input section [10], any increase in the input capacitance that could be made whilst still achieving ZVS across the required range of loads and frequencies is likely to increase the power density of the device. Conversely, to adjust the T1-15W design so that it could achieve ZVS at the matched load condition would require Cin to be decreased, which in turn would require the input section volume to be increased, which would decrease the power density of the device. In reality, modifying the T1-15W device to obtain ZVS at the matched load would also require the input section force factor to be altered, but this will be discussed in a future paper.
ACKNOWLEDGMENT The authors would like to thank the Innovative electronics Manufacturing Research Centre (IeMRC) for sponsoring this work, and Dr. Alfredo Carazo and Dr. Chris Bingham for the helpful discussions relating to this work. REFERENCES [1]
E. L. Horsley, M. P. Foster, and D. A. Stone, "State-of-the-art Piezoelectric Transformer Technology," presented at European Conference on Power Electronics and Applications, 2007. [2] R.-L. Lin, "Piezoelectric Transformer Characterisation and Application of Electronic Ballast," Ph.D. Thesis, Virginia Polytechnic Institute and State University, 2001. [3] K. S. Meyer, M. A. E. Andersen, and F. Jensen, "Parameterized analysis of Zero Voltage Switching in resonant converters for optimal electrode layout of Piezoelectric Transformers," presented at PESC 2008. [4] S. Bronstein and S. Ben-Yaakov, "Design considerations for achieving ZVS in a half bridge inverter that drives a piezoelectric transformer with no series inductor," presented at APEC, 2002. [5] R.-L. Lin, F. C. Lee, E. M. Baker, and D. Y. Chen, "Inductor-less piezoelectric transformer electronic ballast for linear fluorescent lamp," presented at APEC, 2001. [6] M. K. Kazimierczuk and D. Czarkowski, Resonant Power Converters: John Wiley & Sons Inc. , 1995. [7] M. P. Foster, H. I. Sewell, C. M. Bingham, D. A. Stone, and D. Howe, "Methodologies for the design of LCC voltage-output resonant converters," Electric Power Applications, IEE Proceedings -, vol. 153, pp. 559-567, 2006. [8] A. J. Forsyth and S. V. Mollov, "Simple equivalent circuit for the seriesloaded resonant converter with voltage boosting capacitor," Electric Power Applications, IEE Proceedings -, vol. 145, pp. 301-306, 1998. [9] J. G. Hayes and M. G. Egan, "Rectifier-compensated fundamental mode approximation analysis of the series parallel LCLC family of resonant converters with capacitive output filter and voltage-source load," presented at PESC 99, 1999. [10] E. L. Horsley, A. V. Carazo, M. P. Foster, and D. A. Stone, "A Lumped Equivalent Circuit Model for the Radial Mode Piezoelectric Transformer," presented at APEC, 2009.
5
Normalised vCin(td)
4
3
2
1
0 8 8.5 9 9.5 4000 3500 4
x 10
Frequency (Hz)
3000
2500
2000
1500
1000
500
CONCLUSIONS
0
Load, RL (Ω)
Figure 9. ZVS profile of T1-PP0361
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