Advanced Packaging, IEEE Transactio - koasas - kaist

IEEE TRANSACTIONS ON ADVANCED PACKAGING, VOL. 25, NO. 2, MAY 2002

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Microwave Frequency Crosstalk Model of Redistribution Line Patterns on Wafer Level Package Myunghee Sung, Student Member, IEEE, Namhoon Kim, Member, IEEE, Junwoo Lee, Hyungsoo Kim, Student Member, IEEE, Baek Kyu Choi, Jae-Myun Kim, Joon-Ki Hong, and Joungho Kim, Member, IEEE

Abstract—As the operating frequency of systems increases above the gigahertz frequency range, the electrical performance of a package becomes more critical. Wafer level package (WLP) is a promising solution for future high-speed packaging needs. Because the length of the interconnection lines on the WLP is limited to die size, the WLP has a minimum number of electrical parasitic elements. Because the crosstalk generates significant unwanted noise in nearby lines, causing problems of skew, delay, logic faults, and radiated emission, the crosstalk phenomena is drawing more attention than ever among the electrical characteristics of the WLP. Consequently, the modeling of the crosstalk parameters of the WLP is very important when used in high-speed systems. In this paper, we first report the crosstalk model parameters of the WLP, especially for the redistribution layer. These can be easily embedded into SPICE circuit simulation. The model is represented by the distributed lumped circuit elements, such as the mutual capacitance and the mutual inductance. The crosstalk model was extracted from two-step on-wafer -parameter measurements and was fitted to the measurements made at up to 5 GHz. The models were obtained as a function of the line spacing between the coupled lines of the WLP. Finally, the extracted crosstalk model was verified by comparing the far-end crosstalk waveform simulated from the extracted model parameters with the far-end crosstalk waveform measured by time domain transmission (TDT) measurement. Index Terms—Crosstalk, CSP, model,

-CSP, package, WLP.

I. INTRODUCTION

F

UTURE package solutions of small form factor, high-performance, and cost-effective process are strongly required to meet the demand for even smaller and faster future electronic products. As a solution for such high-speed packaging systems, chip scale package (CSP) was developed; examples include micro ball grid array chip scale package ( BGA CSP), micro ball grid array wire bonded ( BGA-W), and wafer level package (WLP). Recently the WLP of all the CSP package solutions has been more intensively investigated as one of the most promising solutions for high-speed and high-density packages [1]. Manuscript received February 21, 2002; revised July 1, 2002. M. Sung, J. Lee, H. Kim, and J. Kim are with Terahertz Media and System Laboratory, Department of Electrical Engineering and Computer Science, Korea Advanced Institute of Science and Technology, Taejon 305-701, Korea (e-mail: [email protected]; [email protected]; shamino@ eeinfo.kaist.ac.kr; [email protected]; [email protected]). N. Kim is with Silicon Image Inc., Sunnyvale, CA 94085 USA (e-mail: [email protected]). B. K. Choi is with Hyundai Syscom Company, Ltd., Ichon 467-701, Korea (e-mail: [email protected]). J.-M. Kim and J.-K. Hong are with Hynix Semiconductor Company, Ltd., Ichon 467-701, Korea (e-mail: [email protected]; [email protected]). Digital Object Identifier 10.1109/TADVP.2002.803306

First, the WLP has been developed as a cost-effective packaging method compared with the BGA package. In the fabrication of the WLP, the package is applied to the entire wafer and all the dices are packaged together at the wafer level. After the wafer is diced, each chip is in a packaged format, ready for the subsequent test and assembly process [2]. The WLP improves the concept of the die-size packaging by introducing economies of scale to the manufacturing process. Packages are fabricated while still at the wafer level, which has clear advantages over the traditional packages. The redistribution lines on the WLP connect the on-chip pads to the solder ball pads, which are used for placing solder balls in area array form by using the redistribution line patterns. The length of the redistribution patterns on the WLP is in a range of die size, hence enabling the minimum interconnection length on the package. Consequently, the interconnection length on the WLP is significantly reduced as compared with other package solutions, and the parasitic loading effect of the WLP package is also significantly reduced [2], [3]. In addition to the above advantages of the cost effectiveness of the WLP, another very significant advantage of the WLP is the capability of the WLP for high-speed applications such as Rambus dynamic random access memory (DRAM), double data rate dynamic random access memory (DDR DRAM), and flash memory [4]. Furthermore, the WLP can be applied as a package solution for above 1 GHz digital, differential signaling, and microwave devices. However, the WLP has a limitation on the fan-out structure, and therefore it is more suitable for smaller I/O package. It is important to obtain accurate electrical characteristics of high-performance packages such as WLP. In particular, a precise and reliable model of the WLP is essential in order to estimate the noise and delay problems associated with the parasitics of the WLP. Because crosstalk generates significant unwanted noise in nearby lines, causing problems of skew, delay, logic fault, and radiated emission, the crosstalk phenomenon, one of the electrical characteristics of the WLP, is attracting more attention than ever. The redistribution patterns on the WLP are placed densely on the surface of the WLP, which is a die size, and hence the crosstalk model is very important. Both the minimum line width and the minimum spacing of the redistribution pattern on a WLP are approximately 40 m, which is much smaller than those of other conventional packages [3]. In particular, the crosstalk problem is no longer a negligible design concern when having to ensure the proper operation of the circuits and systems that have clock rates of more than 400 MHz. The operating clock frequency and data transfer rate are expected to

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(a) (a)

(b)

(b) Fig. 1. (a) Cross-sectional structure of the WLP using the Omega CSP process. (b) Typical redistribution line patterns on the WLP.

Fig. 2. Test WLP package for the crosstalk modeling procedure. The test WLP is designed for the two-port S -parameter measurements, and a subsequent modeling process. In addition, the test WLP was used for the TDR measurements to verify the extracted model. (a) Cross-sectional structure on the WLP. Coupled lines placed on top of the metal plane on the WLP. (b) Layout pattern on the test WLP. On each end of the metal microstrip lines, G-S-G probe metal patterns are placed for the microprobing. Two coupled microstrip lines are designed to extract the crosstalk models (C m; Lm).

II. STRUCTURE OF THE TEST WLP increase to greater than the gigahertz frequency region in the near future. Consequently, a more precise crosstalk model of the redistribution pattern on the WLP is urgently required for system design in the frequency range above 1 GHz. Recently, interconnection line models of the WLP were reported [2], [5]. However, the crosstalk model was not included in the reported models. In this paper, we first report the crosstalk model of the redistribution pattern on a WLP. It is extracted based on two-port -parameter measurements and a subsequent parameter fitting method. The model is represented by the distributed circuit elements, and therefore it can be easily embedded into the SPICE circuit simulation. The crosstalk model is described as the mutual capacitance and the mutual inductance between the coupled interconnection lines on the WLP. The models were obtained for varying line spacing between the coupled lines on the WLP. During the modeling process, two-step Microprobe measurements were sufficient, including the de-embedding procedure for the probing pad. As a by-product of the modeling, the line models were also extracted, producing a complete set of the distributed model parameters for the coupled lines [2], [5]. Finally, the extracted crosstalk models were verified by comparing the far-end crosstalk waveforms simulated using the extracted model with the far-end crosstalk waveform measured by time domain transmission (TDT) measurement. The models can be applied to estimate of the noises caused by the crosstalk.

The Omega-CSP process, which is one of the WLP processes developed by Hynix Co. Ltd. (formerly, Hyundai Electronics), was used to fabricate the test WLP. Fig. 1 shows the cross-section of the WLP made by the Omega-CSP process, and the typical redistribution pattern of the WLP. The Omega-CSP also requires a redistribution layer structure. In the Omega-CSP process, a stress buffer layer (SBL) and copper metal are used for the passivation and the metallization, respectively. The redistribution lines extend the terminal pitch by rearranging the pads in an area array and interconnect on-chip pads to the pads for the solder ball. The on-chip pad is connected to the redistribution layer by via. A solder ball is placed on the solder ball pad, which is located on the redistribution layer, while the other side of the solder ball is located on a printed circuit board (PCB). The purpose of the study was to extract the mutual capacitance and the mutual inductance of the redistribution pattern of WLP, depending on the line spacing between the coupled lines. We designed and fabricated the test WLP for the on-wafer -parameter measurements and the subsequent modeling process. Fig. 2 illustrates the cross-section and the layout structure of the test WLP. The length of the coupled section is 0.997 cm. The 20 m) thickness of the dielectric layer in the test WLP ( is much smaller than the line spacing to the ground lines ( 110 m). Hence, the coupled line structure behaves as a coupled microstrip line structure rather than a coplanar waveguide. The maximum allowable thickness of the stress buffer layer is

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capacitance- and conductance-dominant component. We can de-embed the parasitic effect of the pad from the measured -parameters using the pad model (step 2). Nevertheless, the de-embedding effect for the test WLP is not clear, because the area of the line (40 m 9950 m) is larger than that of the pad (100 m 100 m). We derive the propagation constants ( and ) and the characteristic impedances ( and ) for each even mode and odd mode from the wave equation of the equivalent circuit of lossy-coupled lines. First, the derivation of the coupled transmission line equations and the wave equations for the lossy case is similar to that of the transmission line equation and the wave equation for each even-mode (same voltage and same current for two conductors) and odd-mode (opposite voltage and opposite current for two conductors) excitation of the coupled transmission line equations for the lossless case [7] (1) (2) (3)

Fig. 3. Modeling procedure for the crosstalk parameter extraction from the S -parameters on-wafer measurement.

limited to approximately 20 m, due to the limitation of the present spin-coating process technology. Hence, the thickness of the stress buffer layer in the test WLP is much less than that of the elastomer (175 m) used as a dielectric in conventional -BGA. Therefore, the input inductance of the WLP should be less than that of a -BGA, however, the input capacitance of the WLP is greater than that of the -BGA [2], [5]. The thickness of the BisbenzoCycloButene (BCB) layer (7 m) is less than that of the SBL, and therefore a homogeneous medium is impossible, regardless of the material’s properties. A two-step of a two-port G-S-G probing measurement is sufficient for the entire modeling procedure, in which one end of each coupled lines is terminated as a open circuit. The modeling procedure does not require any four-port measurements or special matched terminations. The test pattern has two open ends at the near-end of the quiet line and at the far-end of the active line [Fig. 2(b)]. Because this method is simple and requires fewer measurements, we utilized a parameter fitting process using even-mode and odd-mode analysis in the extraction procedure. III. CROSSTALK PARAMETER MODELING PROCEDURE Fig. 3 illustrates the extraction procedure for the crosstalk parameters by the -parameter measurement and the parameter fitting. The principle of the crosstalk modeling procedure and the demonstration for the crosstalk modeling will be reported in Section III-V. First, the two-port -parameter matrix for the far-end crosstalk was measured from the test pattern of Fig. 2(b) by the on-wafer -parameter measurement (step 1). of the probing pad without the The reflection coefficient lines was measured to extract the model of the probing pad for the subsequent de-embedding process. The probing pad is a

(4) The ABCD parameters of the transmission line with propagaare known, and tion constant and characteristic impedance the same derivation procedure can be applied to the ABCD parameters of lossy-coupled transmission lines for the even-mode and odd-mode propagation. Nevertheless, both currents are defined as the current in the direction of propagation. In order to derive the four-port -parameters, it is possible to derive the ABCD parameters of the coupled lines for evenand odd-mode excitation of the ports by considering the two left ports as an input, and the two right ports as an output [6]. In the two-port network converted from the four-port network, the , the even-mode even-mode voltage of the input becomes , and the odd-mode voltage of the output port becomes voltage is similar to the even-mode case (5) (6) These two sets of matrix ABCD parameters for each excitation mode define the four simultaneous equations describing the four-port -parameters (7); therefore, the -parameter of the coupled lines with the two-port open state (8) is obtained from the zero current boundary condition

(7)

(8)

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TABLE I EXTRACTED MODEL PARAMETERS OF THE REDISTRIBUTION LINE PATTERNS ON THE WLP (MUTUAL INDUCTANCE, MUTUAL CAPACITANCE, SELF-INDUCTANCE, SELF-CAPACITANCE, AND RESISTANCE), DEPENDING ON THE LINE SPACING

(a)

(b) Fig. 4. Comparison of the S -parameter (S ; S ) from the model and the S -parameter from measurement for 40 m spacing. The dotted line (model)

was calculated from the extracted crosstalk model parameters. In addition, the solid line was measured using the two-port S -parameter measurement.

Finally, the -parameters of the coupled lines with the two-port open state are obtained from the -parameters with the two-port open state by matrix manipulation (step 3). Next we compare the -parameters from the measurements with the -parameters from the model parameters by crosstalk parameter variation, and we obtain the crosstalk parameter for the desired frequency range; this requires several iterations (step 4). The SPICE simulation is obtained using the extracted model parameters (step 5) [8]. The far-end crosstalk waveform was measured by the on-wafer TDT measurement using a HP 54120B digital sampling oscilloscope with a HP 54121A TDR/T sampling head. We verified the quality of the extracted model by comparison and iteration (step 6), and obtained the extracted crosstalk parameter (step 7). IV. EXTRACTED CROSSTALK PARAMETERS Fig. 4 shows the -parameter comparison results for the test pattern with 40- m spacing between signal lines, 110- m spacing to coplanar ground, and 0.997-cm coupled line length. This result gives the best fit up to 5 GHz for the model param-

eter and the modeled -parameters and matches the measured results very well. The -parameter plot in the real and imaginary form shows the small differences more clearly than do the decibel and radian, or degree, forms. This crosstalk parameter can be derived from parameter fitting using the -parameters from the model and the -parameters from the measurements. Table I shows the extracted model parameter values of the redistribution patterns on the WLP (self-capacitance, self-inductance, resistance, mutual capacitance, and mutual inductance), for varying line spacing. The extracted self-capacitance and self-inductance also have similar values for the line parameter without adjacent lines [2]. In addition, it is possible to check the degree of homogeneity from a comparison of the ratio of mutual inductance to self-inductance with the ratio of mutual capacitance to self-capacitance [9]. The comparison shows the ratio is different but the difference is small. Fig. 5 illustrates the dependency of the extracted mutual capacitance and mutual inductance on line spacing. As the spacing between signal lines increases, the mutual capacitance and the mutual inductance decreases. The narrower the space between coupled lines, the greater the variance in both the crosstalk parameters. The extracted mutual capacitance and mutual inductance were found to be acceptable. The range of the mutual capacitance of the test vehicle is less than 98.2 fF/cm. In addition, the range of the mutual inductance of the test vehicle is less than 220 pH/cm. The maximum values of the mutual capacitance and the mutual inductance are obtained in the case of 40- m spacing, which is the minimum spacing. Usually, the distance between signal pattern and silicon substrate is smaller in WLP than in -BGA. Therefore, the input inductance in WLP is less than that in -BGA, but the input capacitance in WLP is greater than that in -BGA [2], [5]. However, the mutual capacitance in WLP is less than that in -BGA due to greater self-capacitance caused by the smaller distance. The input capacitance of the WLP is not free from the mutual capacitance of the redistribution layer of the WLP. Because the I/O number is fixed and the packaging size is similar to the chip size, the crosstalk problem is more critical in the case of die shrinkage. The smaller the die, the narrower the spacing between signal lines. The development of the finer pitch process exacerbates the crosstalk problem.


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(a) (a)

(b) Fig. 5. Extracted crosstalk model parameters as a function of the line spacing on the redistribution layer. (a) Mutual capacitance. (b) Mutual inductance.

(b)

V. VERIFICATION OF THE EXTRACTED CROSSTALK PARAMETERS

Fig. 6. Far-end crosstalk waveform of the redistribution pattern on the WLP. (a) Simulated far-end crosstalk waveforms using the extracted crosstalk parameters. (b) Measured far-end crosstalk waveforms by the TDT measurement with 80-ps rising time and 200-mV amplitude.

The validity of the extracted crosstalk model was examined by comparing the SPICE simulation using the extracted model parameters with the time-domain crosstalk pulse waveform using the TDT measurement [8]. The TDT measurement was conducted using a wide bandwidth digital sampling oscilloscope (HP 54 120B) with TDR/T option (54121A). The rise time of the input pulse in the TDT measurement was and the 80 ps. The extracted crosstalk parameters single line model parameters ( , , and ) were used for the SPICE simulation. In the SPICE simulation, the coupled lines with 0.997-cm length were divided into 30 sections, which correspond to a length of less than /20 of the 4-GHz signal in of the 80-ps rising time the distributed circuit model. The is 4 GHz. The input pulse was applied to the near-end active line and the crosstalk was measured at the far-end quiet line in the measurement and simulation. Fig. 6 clearly shows the close agreement of the amplitude and the pulse shape between the simulation [Fig. 6(a)] and the TDT measurement [Fig. 6(b)], demonstrating the reliability and the

usefulness of the extracted crosstalk model. This provides justification for the assumptions made in the formulations. In both the SPICE simulation and the TDT measurement, the crosstalk voltage for the narrower spacing was higher than that for the greater spacing. As can be found in the extracted mutual capacitance and mutual inductance in Fig. 5, the coupled line with the narrower spacing has a higher crosstalk voltage in both the simulation and measurement. The simulated crosstalk peak in Fig. 6(a) predicts voltages of approximately 95% of the crosstalk peak voltage measured by the TDT measurement in Fig. 6(b). However, the shape of the simulated waveform is sharp, while the shape of the measured waveform is flat at the top of the waveform. The maximum value of the far-end crosstalk is approximately 15 mV for a step source, with the 80-ps rise time and 200-mV amplitude for the redistribution pattern on the WLP with 0.995-cm coupled length, 20- m dielectric thickness, 40- m width, and 40- m spacing. In addition, the maximum

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value of the far-end crosstalk is approximately 15 mV for the Embedded Microstrip (EM) structure for the silicon chip with 2.2-mm coupled length, 0.7- m dielectric thickness, 2- m width, and 2- m spacing for the same step source [8]. Both have a similar peak value for the far-end crosstalk, and it means the crosstalk of the package should also be considered in high-speed applications where the crosstalk parameter modeling becomes more important. The modeling procedure remains accurate, provided the assumption of the quasi-TEM mode propagation is acceptable because the telegrapher’s equation implies the Quasi-TEM assumption. In addition, we assume that there is zero current for the open termination at the near-end of the quiet line and the far-end of the active line. However, fringing capacitance effects exist at high frequency. Finally, comparing the measured crosstalk pulse with the expected crosstalk pulse waveform using circuit simulation based on the extracted crosstalk models showed the accuracy and reliability of the extracted crosstalk models. VI. CONCLUSION The electrical performance of the package becomes the bottleneck in realizing high-speed systems. Because the WLP potentially has a minimum number of parasitic elements, it is becoming the most likely candidate for the high-speed package solution. Precise electrical models of the WLP are required. The model can be used for the evaluation of the data transmission bandwidth and the noise performance such as crosstalk and electromagnetic interference (EMI) when applying the WLP to high-speed systems with a data bandwidth of over 1 Gb/s. In this paper, first we reported the crosstalk model of the redistribution patterns on the WLP. The model was extracted based on -parameter measurements and a parameter fitting method using an even-mode and odd-mode analysis with frequencies of up to 5 GHz. The applied extraction method for the crosstalk model is found to be very simple and efficient. The model was extracted for varying spacing between lines. As a by-product of the modeling procedure, the single line model parameters were also deduced. Assumptions of the quasi-TEM mode propagation and zero-current at the open-termination were applied in the modeling procedure. If the frequency of the modeling becomes higher, these assumptions should be carefully reviewed. We also compared the crosstalk voltage on the WLP to the crosstalk voltage on the chip level interconnection, asserting that the crosstalk noise on the WLP needs more attention. It is found that the mutual inductance of the redistribution lines on WLP is in a range from 80 pH/cm to 230 pH/cm for line spacing from 40 m to 100 m, while the mutual capacitance is in the range of 30 fF/cm to 100 fF/cm. As can be expected, the crosstalk model parameters are strongly affected by the spacing between the lines. The narrower the spacing between the coupled lines the greater the variance in both of the crosstalk parameters. Finally, the extracted crosstalk model was verified by comparing the far-end crosstalk waveform simulated using the extracted model parameters with the far-end crosstalk waveform

measured by the on-wafer TDT measurement. Additionally, the model can be applied to the simulation of signal integrity and noise in high-speed systems containing the WLP. ACKNOWLEDGMENT The authors wish to thank the Members of the Package/Module Team, Hynix Semiconductor (formerly Hyundai Electronic Corporation, Ltd.), for their support and the test device fabrication. REFERENCES [1] P. Elenius, S. Barrett, and T. Goodman, “ULTRACSP ™—A wafer level package,” IEEE Trans. Adv. Packag., vol. 23, pp. 220–226, May 2000. [2] J. Lee, B. Choi, S. Ahn, W. Ryu, J. M. Kim, K. S. Choi, J-K. Hong, H-S. Chun, and J. Kim, “Microwave frequency model of wafer level package and increased loading effect on rambus memory module,” in Proc. IEEE 51st Electron. Comp. Technol. Conf., Orlando, FL, May 2001, pp. 128–131. [3] S. W. Park, J. M. Kim, H. G. Baik, S. H. Kim, J. K. Hong, and H. S. Chun, “Thermal and electrical performance for wafer level package,” in Proc. IEEE 50th Electron. Comp. Technol. Conf., Las Vegas, NV, May 2000, pp. 301–310. [4] P. Garrou, “Wafer level chip scale packaging (WL-CSP): An overview,” IEEE Trans. Adv. Packag., vol. 23, pp. 198–205, May 2000. [5] M. H. Ahn, D. H. Lee, and S. Y. Kang, “Optimal structure of wafer level package for the electrical performance,” in Proc. IEEE 50th Electron. Comp. Technol. Conf., Las Vegas, NV, May 2001, pp. 530–534. [6] G. I. Zysman and A. K. Johnson, “Coupled transmission line networks in an inhomogeneous dielectric medium,” IEEE Trans. Microwave Theory Tech., vol. 47, pp. 753–759, Oct. 1969. [7] D. H. Schrader, Microstrip Circuit Analysis. Englewood Cliffs, NJ: Prentice-Hall, 1995, pp. 143–147. [8] M. Sung, W. Ryu, H. Kim, J. Kim, and J. Kim, “An efficient crosstalk parameter extraction method for high-speed interconnection lines,” IEEE Trans. Adv. Packag., vol. 23, pp. 148–155, May 2000. [9] H. B. Bakoglu, Circuits, Interconnections, and Packaging for VLSI. Reading, MA: Addison-Wesley, 1990, pp. 291–298.

Myunghee Sung (S’98) received the B.S. and M.S. degrees in electrical engineering from the Korea Advanced Institute of Science and Technology (KAIST), Taejon, in 1997 and 1999, respectively, where she is currently pursuing the Ph.D. degree. She has been working with high-speed VLSI interconnection and crosstalk modeling on chip, PCB, and package (wafer level package). Her current research interest is the compensating crosstalk on chip, PCB, package, and connectors. Ms. Sung received the Korea Research Foundation (KRF) Grant Award in 2001.

Namhoon Kim (M’01) received the B.S. and M.S. degrees in electrical engineering from the Korea Advanced Institute of Science and Technology (KAIST), Taejon, in 1999 and 2001, respectively. He has been working on gigahertz systems signal integrity design, package modeling, and crosstalk modeling on PCB, package, and chip. He is currently with Silicon Image, Inc., Sunnyvale, CA, as a Signal Integrity Engineer. His work has included microwave device measurement, testing, modeling, and characterization.


Junwoo Lee received the B.S. and M.S. degrees in electrical engineering from the Korea Advanced Institute of Science and Technology (KAIST), Taejon, in 1999 and 2001, respectively, where he is currently pursuing the Ph.D. degree in electrical engineering. He has been working with high-speed VLSI interconnection, microwave package modeling and system level EMI reduction. His current research interest is the modeling of multilayer P/G on the chip package.

Hyungsoo Kim (S’97) received the B.S. and M.S. degrees in electrical engineering from the Korea Advanced Institute of Science and Technology (KAIST), in Taejon, in 1997 and 1999, respectively, where he is currently pursuing the Ph.D. degree. He has been working with high-speed VLSI interconnection, high-speed digital IC with minimized EMI radiation, adaptive output driver design, and PCB design for DRAM module. His current research interest is the establishing of the design methodology of a power/ground network for high-speed packages.

Baek Kyu Choi received the B.S. and M.S. degrees in electrical engineering from the Korea Advanced Institute of Science and Technology, Taejon, in 1999 and 2001, respectively. He joined Hyundai Syscomm, Korea, in 2001 and is currently engaged in research on RF system design of base station for wireless communication. His research interests include modeling and simulation of RF board and system level design of base station.

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Jae-Myun Kim received the B.S. degree in semiconductor engineering from Chung Ju University, Korea, in 1996. He joined the Packaging Research Team, Hynix Semiconductor Industry Co., Korea, in 1996. He has been involved in development of memory device packaging. He is now a Technical Engineer on contract manufacturing of electronic packaging.

Joon-Ki Hong received the B.S. degree from Inha University, Korea, in 1987. He joined the Packaging Research Team, Hynix Semiconductor Industry Co., Korea, in 1993. He has been involved in development of memory device packaging. He is now Member of Technical Staff, Advanced Package Development Team.

Joungho Kim (M’86) received the B.S. and M.S. degrees in electrical engineering from Seoul National University, Seoul, Korea, in 1984 and 1986, respectively, and the Ph.D. degree in electrical engineering from the University of Michigan, Ann Arbor, in 1993. His doctoral thesis was on the study of femtosecond time-domain optical measurement techniques for the testing of high-speed digital devices and millimeter-wave circuits. Next, he moved to Picometrix, Inc, Ann Arbor, MI, in 1993, as a Research Engineer, where he was responsible for the development of a picosecond sampling system and a 70-GHz photo-receiver. In 1994, he joined the Memory Division, Samsung Electronics, Kiheung, Korea, where he was engaged in a 1-Gbit DRAM design. In 1996, He moved to the Korea Advanced Institute of Science and Technology (KAIST), Taejon, where he is currently an Associate Professor with the Electrical Engineering and Computer Science Department. Since joining KAIST, his research interests center on the modeling, the design, and the testing of high-speed interconnections, packages, and connectors over GHz frequency range. Related research topics are signal integrity, crosstalk, SSN, and EMI problems. He was on sabbatical leave during the academic year 2001 to 2002 at Silicon Image Inc., Sunnyvale, CA, as a Staff Engineer. He has authored or co-authored over 100 technical articles and numerous patents.