Advantages of CMOS Photonics for Future Transceiver ... - IEEE Xplore

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Drew Guckenberger, Sherif Abdalla, Colin Bradbury, Jim Clymore, Peter De Dobbelaere, Dennis Foltz,. Steffen Gloeckner, Mark Harrison, Steve Jackson, Daniel ...
ECOC 2010, 19-23 September, 2010, Torino, Italy

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Advantages of CMOS Photonics for Future Transceiver Applications Drew Guckenberger, Sherif Abdalla, Colin Bradbury, Jim Clymore, Peter De Dobbelaere, Dennis Foltz, Steffen Gloeckner, Mark Harrison, Steve Jackson, Daniel Kucharski, Yi Liang, Carrie Lo, Michael Mack, Gianlorenzo Masini, Attila Mekis, Adithyaram Narasimha, Mark Peterson, Thierry Pinguet, John Redman, Subal Sahni, Brian Welch, Kosei Yokoyama, and Shuhuan Yu Luxtera, Inc., 2320 Camino Vida Roble, Carlsbad, CA 92011, USA ([email protected]) Abstract The advantages of CMOS photonics for next generation transceiver applications are outlined in terms of raw bandwidth, channel capacity, reach, power, cost, link performance and reliability. The advantages for future integration with host chips area also discussed. Introduction CMOS photonics is a silicon photonics technology platform developed by Luxtera that integrates passive and active optical components on the same SOI wafer with standard CMOS transistors1. A schematic representation of the cross section of devices implemented in this technology is presented in Fig. 1. The high level of photonic and electronic integration that is provided by this technology will allow many optical systems applications to be addressed in the future, including, but not limited to, transceivers, higher-level communication systems, signal conditioning and processing systems, filters and high 2 In this paper, performance oscillators . however, we will focus only on transceiver applications, since these represent the strongest segment of the forecasted optical components business through 20203. Areas of Importance for Future Data Communication Transceiver Applications Optical transceivers for next generation data communication systems will require significant improvements in many areas. They will require decreased cost and power and also require

increased raw bandwidth, bandwidth density, functionality and reliability. IBM has estimated that to support their future system requirements costs in terms of $/Gbps must decrease at a compound annual growth rate (CAGR) of 60%, power in terms of mW/Gbps must decrease at a CAGR of 45% and bandwidth must increase at a CAGR of 210%. This results in estimated requirements of 7 5mW/Gbps and $0.17/Gbps in 2016 when 4x10 optical links will be required per super computer, versus just 48000 in 2008.4 This large number of parallel channels will also require a commensurate increase in per channel reliability, in order to maintain overall system reliability levels. The ITRS roadmap5 also projects that on and off-chip aggregate bandwidth requirements for high performance multi-core architectures will hit ~10 TB/s by 2015, with corresponding interconnect energy per bit budgets on the order of 100 fJ/bit. Future high-performance commercial and military computing architectures are projected to require 10’s, and conceivably even 100’s, of TB/s of bandwidth to the chip. 6,7 Current component cost is $2-$2.5/Gbps and power consumption is ~20-25mW/Gbps.

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Fig. 1: Conceptual cross-section of a CMOS photonics technology (not to scale).

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Clearly a significant improvement is required at both the component and system level to meet these targets. CMOS photonics is uniquely positioned to address all of these requirements.

resistors, capacitors, inductors, diodes, and several types of CMOS transistors makes CMOS photonics ideal for implementing monolithic multi-channel optical transceivers.

CMOS Photonics Overview CMOS photonics provides unprecedented level of optoelectronic integration by integrating photonic elements in a low-cost commercial 130-nm SOI CMOS process using a standard CMOS fabrication tool set1. By integrating waveguides, optical modulators and photodetectors along side CMOS transistors, a single lithographic process can integrate hundreds of photonic components with millions of transistors, achieving similar yields to the base process. The passive waveguides integrated in this technology are implemented as ribbed structures etched into the active top silicon using a planar etch. Confinement of the optical mode in the silicon is obtained by the index contrast of the active silicon with the underlying buried oxide (BOX) and overlying dielectric layers. The waveguide serves as a low-loss (