Algorithm and Implementation of Digital Calibration of Fast Converging Radix-3 SAR ADC Manzur Rahman1,2, Long Chen2 and Nan Sun2 lOracle Microelectronics Group, Austin, TX, USA
2Department of ECE, The University of Texas at Austin, Austin, TX
78712, USA
Email:
[email protected]@utexas.edu,
[email protected]
Abstract-This paper presents a calibration technique for radix-3 successive approximation register (SAR) analog-to-digital converter ( ADC) that was proposed in [1]. The main advantage of radix-3 SAR ADC is it generates 1.6 bits per conversion cycle
and displays the behavioral simulation results. Section IV presents the implementation details and circuit based simu lation results. The conclusion is made in Section V.
which is 60% faster than the conventional radix-2 SAR. However
II. BRIEF DESCRIPTION OF PROPOSED R ADIX - 3 SAR
the performance largely depends on matching of capacitors in
Fig.
digital to analog converter (DAC). Effect of capacitor mismatches on signal-to-quantization-noise ratio (SQNR) is demonstrated and calibration technique is simulated in 180nm CMOS technology. This calibration technique does not require any extra capacitor
DAC and is programmable for any radix-3 SAR ADC. 7 bit Radix-3 ADC is designed which can achieve signal to noise and distortion ratio (SNDR) of 67 dB up to 10% capacitor mismatch.
1 shows the architecture of proposed N-ternary-bit
radix-3 SAR ADC containing N capacitors in each DAC
Gi
where capacitors
2 L:;:� Gj
=
where i
E
[1, N].
In
this architecture, two comparators and two capacitor DACs are used to perform the ternary search. For an N-ternary bit radix-3 SAR ADC, N comparison cycles are needed to generate the final digital output. We assume a full swing input ,----------------------- ,
I. INTRODUCTION
I 0 I -1
Successive approximation register (SAR) analog-to-digital
IVil+ I I
power consuming ADCs in literature because of minimum active analog circuit requirement [2], [3]. Improvements in ADCs for video applications, where sample frequencies of at
10 Msample/s are necessary [4]. The fundamental factor
I I I Vin
that limits SAR ADCs' speed is the number of comparison cycles needed to complete a full conversion process
[5]. For
."'+ "+ 1 1
SAR ADC was proposed that can resolve a ternary bit in
S�1
to [6]. For the same target resolution, the proposed architecture
requires 40% less comparison cycles compared to conventional radix-2 SAR ADCs and as a result, speed is increased by
tt,
II
Ci2 ='l Cil
G{N-l···:
tt
ttt
. 8il � 8io
I
I
I
I
Cio ;Vresnl - Campi I
tft
II
II
I
.1
cycle, the ratio of the adjacent capacitors needs to be exactly
II
I I I
[7].
method is presented for radix-3 SAR ADC which does not
' �Om .� t .t
I 1111 ,"
I
Ii : I 1 : : � c,, -� v"�� II .t t I :'-DAG2 I I JI
�..
821
822 ' C,N-"'
•••••••
tt,
ft'
I
I
II
I 0 I
In this paper, for the first time, a fully digital calibration
II
66,
82N 82N-1
lV;n+ : +1 1-1
capacitor size is usually much larger than that needed from
I I
,I
'''
820
Cn Te,"
mum size requirement of the capacitors to maintain linearity
V'in+
E
••••
•••••••
II
Fig. 1.
include any extra capacitor DAC. Also, it reduces the mini
tt
The paper is organized as follows: Section II explains briefly
on
GIN
II
I
Architecture of the proposed radix-3 SAR ADC.
[-1,1] and V'into
GlD
and
V'in- is sampled on
1336
d2
I I
t'
II
E
[-1,1], thus V'in
the sampling phase, the positive input signal
radix-3 SAR ADC, Section III describes calibration algorithm
Radix-3 SAR Logic
� C2� C21 C20 IIVresn2 C2N-l czN S::m2 S'2N S' s ' 2N-l 22 s'21 S'20 .
I
capacitor matching. To reduce capacitor mismatch, the DAC
.1
II
••• '
S ""
three times and the ADC performance is highly dependent on
978-1-4799-3432-4114/$31.00 ©2014 IEEE
••••••
8iN-l ·······8i2
II
o o -:
1.6 times. In order to get more binary bits per comparison
circuit.
GiN
8iN
1-1 1+1 :V;n
every comparison cycle with less complex circuits compared
and hence reduce the dynamic power and area of the whole
I I ,I :+DAGI Ii " + " :j: "1'fCw :V-'� II 1 1 t'II l : I I I II
I 0 --------------------- � I- --------------------- , I I 0
cycles to complete a full conversion. In [1], a new radix-3
sampling noise consideration
II
81N 81N-1 812 811 810 S , ' C>N C>N-, : C,, Cn .. ""
1+1 : -1
an N-bit conventional radix-2 ADC, it takes N comparison
I
II
I 0I 0
generations of technologies make it possible to use SAR least
I
:+1
converters (ADCs) are reported to be among the lowest
I I
G�N G�N
to to
G�o' G�o
E
[-2,2]. During
V'in+ is sampled
The negative input signal and
G2N
to
G20.
All top
Radix-3 SAR Logic
plates of the capacitors are initially connected to a common
Vem
mode voltage
SemI, S�ml' Sem2 and the switches SemI, S�ml'
through switches
S�m2. After the sampling phase, Sem2 and S�m2 are opened. In the first comparison cycle GIN, GiN' G2N and G�N are connected to O. GlD to G1N-1 and G20 to G2N-1 are connected to 1. Gio to GiN-l and G�o to G�N-1 are connected to -1. According to the charge
Vre/ Gnd Vern Fig. 2.
conservation, we get:
Vrespl - Vresnl
Therefore, output of comparatorl tor2
d1
d2 =
{
2/3 - \lin
=
d1
are given by 1
\lin < 2/3 \lin> 2/3
if
o
if
d2
=
{
(1)
and output of compara
From 1 o
if if
\lin> -2/3 \lin < -2/3
comparison cycle, DACI and DAC2 are doing the radix-3
\lin.
Depending on the outputs of two comparators,
the back-end SAR logic determines which region and generates a digital output Depending on the value of
d1
Di
and
\lin
N 2 2 �)3i- Ei) + El + 3Q-IERd i =2
The output voltage coded
d2, GIN
connected to
Region Vin E [2/3, 2] Vin E [-2/3, 2/3] Vin E [-2, -2/3] not Possible
d2 I 1 0 0
and
G�N
Di 1 0 -1
Vre.f(2:t'-2 GiDi + GRdDRd) Gtotal
From
V;
(6) we get that:
_
out -
-1,
the same way as first comparison cycle. Detailed operation is
Kef(2 2:�2 3
voltage will be:
V;
En
process variation, it is assumed that each capacitors has varied
E [8]: if n
=
1
Gunit
is the unit capacitor and can be defined in terms
of total capacitor
Gtot Gunit
as:
Ven
and for
-I Kef3Q ERdDRd 3N-1 + 3Q-1
(10)
(10) we get:
N
Verror
If number of LSB capacitors used for calibration is Q, then
where
3n-2En. 2 17 vref· - 3N-1 3Q-1' +
(3)
(4 )
0, then ideal output
VeRd
_
So, from (9) and if n> 1
=
Defining error voltage for n-th capacitor as redundant capacitor as
is required for calibration purpose. Due to
by a proportion of
ERd
Vout - Vout,ideal i-2 Vref(2 2:�2 3 EiDi + 3Q-1ERdDRd) (9) N 3 -1 + 3Q-1
ANALYSIS
GRd
=
So, the error voltage is:
Verror
side of the DAC for simplicity of calculation. A redundant
Ei
Vout,ideal
[ 1].
1. It just shows one
i-2 (1 + Ei)Di + 3Q-I(1 + ERd)DRd) (7) 3N -1 + 3Q-l
if there is no mismatch, i.e
III. CALIBRATION ALGORITHM AND THEORETICAL
capacitor
(6)
- (2 2:�2 3i-2Ei + El + 3Q-1ERd)(1 + 2 2:� 3i-2 + 3Q-1) 2
GiN -3 to Gio and qN-3 and G�o connected to -1. For rest of N - 2 comparison cycles, proposed radix-3 SAR operates
Fig. 2 is a simplified version of Fig.
0
Vout can be found in terms of digital output DRd:
will be
1,0 or -1 and GiN and G2N are connected
=
where i E [2, N] and
is in
o or 1. GIN-I, G2N-I, GiN-I and G�N-I will be connected to 0, GIN -3 to GlD and G2N -3 and G20 connected to 1 and
explained in
Di
as explained in Table I.
TABLE I THE RADIx-3 SAR OUTPUT REPRESENTATIONS
dl 0 1 1 0
Gunit(2 2:�2 3i-2Ei + El + 3Q-1ERd) (5) 3N-I + 3Q-l
(5) it is found that:
(2)
Based on the above analysis, it is evident that in the first search for
Gumt. - Gumt. +
Simplified Radix-3 DAC
L VeiDi + VeRdDRd
(1)
i=2
In the current ADC architecture, N-th capacitor, equal to twice the sum of the LSB capacitors i
E
[1, N - 1]. LSB capacitors
Gi,
i
E
Gi,
Gi,
is
where
[1, Q] do not
require calibration as their mismatch error is negligible calibration is performed on MSB capacitors
GN
[8]. So,
i E [Q+ 1, N].
Calibration is started by finding the mismatch of N-th MSB capacitor.
1337
V;·ef
is sampled across bottom plate of the MSB
Radix-3 SAR Logic
ifq=N
if N > q:::: Q+ 1
Vrej Gnd Vern Fig. 3.
(18)
Precharging phase of calibration
Finish
Radix-3 SAR Logic
Cj_Vref; jE[Q+1,Cnt-1]; Ccnt,Ci- Gnd ;i� [Q+1,Cnt-1]
V"f--'+i-----'++--+i+--'+-''+-"'+--' Gnd --�--�r---�--��+-�� Vcm -----'--�--+---'-� Fig. 4.
Quantize residue voltage Vxn using Ci; iE [1,Q] Yes
Charge distribution phase of calibration
Digitized error voltage Yo.
capacitor GN and rest of the bottom plates of capacitors are connected to Vcm as shown in Fig. 3. T hen V;'eJ is sampled on the bottom plate of all the capacitors except GN and Gi, i E [1, Q] which will be connected to ground as shown in Fig. 4. So, according to charge conservation, the residual charge at the top plate of the capacitors:
N-1
L
1
QXresN = VreJ(- GN 2"
=
i=Q+l
Gi - GRd)
N-l Ni- - 3Q-1c vreJ Gunit (3 2EN - 2 '""' � 3 2c, '-0 '-Rd) (12) i = Q+ 1
TT
As explained earlier, assuming mismatch errors of LSB ca pacitors are negligible, i.e Ei 0, i E [ 1, Q]. From (6):
a(DVz• 2
=
N+M
- L
'-9+1
Fig. 5.
DV.. )
Steps for proposed calibration
Fig. 5 shows the calibration steps for radix-3 SAR. During normal conversion cycles, the calibration logic is de-activated and converter works in the same way as regular radix-3. Finally the error correction voltages are added based on DAC digital input code of the first N - Q MSB capacitors. If i th bit is assigned as VreJ, Vcm or Gnd, then corresponding error voltage DVci will be DVci, ( 1 / 2 ) DVci or 0 respectively. Gi, i E [1, Q] can be used for digitizing error terms using radix-3 algorithm. Quantizing the error voltage does not affect the calibration performance much as quatized values closely follow the original error voltages.
=
2·
3N-2EN = -2
N-l
L
i=Q+l
3i-2Ei - 3Q-1ERd
....-_--_-...,
70r--
(13)
....-__-_-...,
70r--
68
So, from (12) and (13): 64
(14) Hence, residual voltage:
v:
XN =
66
62
2·
QXresN � . VreJ EN3N-2 = 2 (3N-1 + 3Q-1) Gtotal
(15)
58
From (10) and (15)
62
- e - SI\f])R After Calibration ...... SI\f{)R Before Calibration
(16) Similarly, it can be shown that, the relationship between residual voltage Vxn and error voltage Vcn, n E [Q+ 1,N - 1 ] :
. _....i._---' 50 "__...._..i... 0 Capacitor mismatch (%) (a)
N
- L
Vc J
...... i .
. . . . .
"i,......
�: O_q - 1V '0.......�. '. 't/ .' � .......- . .
.
.
.
- �
60
. . . . . . . . . . . • • . . .
- e - SNDR Calibratcd in Circuit ...... SNDR Calibrated in Matlab
. _....i._---' 58 "__...._..i... 0 Capacitor mismatcb (%) (b)
(17)
Fig. 6. (a) SNDR of radix-3 SAR before and after calibration (b) Comparison of calibration results based on schematic and Matlab
After quatizing the error, digitized error voltages DVcq and quantized residue voltage, DVxqare:
To verify the calibration algorithm, capacitor ratio error was varied for 0.5% to 8% and each time SNDR was calculated.
Vcn = (V xn 3
i=n+l
.
, , , • • • ,", • • • • • • r • • • • • • • � • • • • • •
56
2
......
1338
TABLE II COMPARISON OF CALIBRATION OF ADCs'.
Fig. 6(a) shows SNDR of raidx-3 before and after calibration from matlab based simulation. With the increment of statistical variation of capacitors, SNDR falls sharply without calibration, but with calibration, the SNDR is held around 67 dB. IV.
To verify proposed idea, the calibration of a 7-bit radix3 SAR ADC is implemented in 180nm CMOS technology with 1.8Y power supply. Capacitance mismatch is modeled by the standard deviation. The amplitude of the sine wave input signal is 1.7 Y peak to peak. SNDR found from circuit based calibration and SNDR from matlab based simulation are plotted in Fig. 6(b). The results match well with the theoretical analysis. The plot shows that circuit based result closely follows Matlab simulation result and verifies the calibration idea, when a standard DAC capacitance deviation is taken up to 8%. The comparator structure is shown in Fig. 8 [9]. The comparator has a pre-amp with a gain of 7. It contains a dynamic latch which does not consume any DC power. M3 and M4 are used to reduce the kick-back noise. The total power of the comparator is 0.28mW. Also, comparator offset can be cancelled using the techniques dicussed in [10]. The 128 points OFT plot of 7-ternary-bit SAR ADC simulating with sampling frequency 25 MHz and with 5% mismatch is shown in Fig. 7. The SQNR is 53.47 dB before calibration and 67.46 dB after calibration. From circuit, up to 10% mismatch, SNDR of around 67dB was found which ver ifies proposed calibration algorithm. The proposed calibration performance is compared with other techniques in Table II. The main advantage of this work is that it does not require any extra capacitor DAC and can help achieve ENOB which will be close to resolution. CONCLUSION
In this paper, digital calibration technique is presented for radix-3 SAR ADC. The main advantage of this architecture is that it does not need any extra capacitor DAC array and calibration circuit is programmable for any size of DAC array with a small overhead of digital circuit. Theoretical analysis and circuit based simulation also verified proposed idea. REFERENCES [I] L. Chen et al.,"A fast radix-3 SAR analog-to-digital converter", IEEE MWSCAS, pp. 1148-1151 A!lL2013. [2] K. Hadidl et al., " 8-b 1 .3-MHz successive- approximation AID con-
verter" IEEE JSSC, vol. 25 no. 6, pp. 880, Jun. 1990. [3] 1. Sauerbrey et al., " 0.5-V 1- W successive approximation ADC," IEEE JSSC, vol. 38 no. 7, 126.1, luI. 2003. [4] F. Kuttner, " 1 .2 V 1 b 20 lVlSample/s non-binany successive approximation ADC in 0.13 m CMOS," IEEE ISSCC , 2002, pp. 136.
gP.
e
0
�
CIRCUIT IMPLEMENTATION
V.
§
50 40 30 20 to
�iQ -10 � -20 ""
Q..
o
0.1
0.2
0.3
Frequency(flfs) (a)
0.4
0.1
0.2
0.3
Frequency(f/fs) (b)
0.4
Fig. 7. DFT of radix-3 SAR with 5% mismatch (a) before calibration (b)after calibration.
Vi�
Fig. 8.
Comparator with pre-amp.
[5] J. L. McCreary et al., "All-MOS charge redistribution analog-to-digital conversion techniques," IEEE JSSC,voi. 10, no. 6, pp. 371-379, December 1975. [6] S. Thirwlakkarasu et aI., "A Radix-3 SAR Analog-to-Digital Converter," IEEE ISCAS, pp.1460-1463, May 2010. [7] R. Schreier et a/., "Understanding Delta-Sigma Data Converters" John Wil;;y and Sons, 2005. [8] H.-S. Lee et ai., "A Self-Calibrating 15 Bit CMOS AID Converter," IEEE JSSC, vol. 19, no. 6, pp. 813-819, Oct. 1984. [9] L. G. Brooks, "Circuits and Algorithms for Pipelined ADCs in Scaled CMOS Technologies," MIT PhD Thesis Jun. 2008. [10] E. Alpman et al., "A 1.1 V 50 mW 2.5 GS/s 7 b time-interleaved C - 2C SAR ADC in 45 nm LP digital CMOS," IEEE ISSCC, Feb. 2009, pp. 76-77. [11] Y. Kuramochi et al., "A 0.05-mm2 110-mW IO-b self-calibrating successive approximation ADC core in 0. 18 /-Lm CMOS," IEEE ASSCC, Nov. 12-14,2007, pp. 224-227. [12] Y. Chen et ai., "Split capacitor DAC mismatch calibration in suc cessive approximation ADC," IEEE CICC, Sep. 2009, pp. 279-282 [13] M. Yoshioka et ai.,"10 b 50 MS/s 820 /-LW SAR ADC with on-chip digital calibration," IEEE TBCAS, vol. 4, no. 6, pp. 410-416, Dec. 2010 [l4] Wei Li et ai., "Digital Foreground Calibration Methods for SAR ADCs," IEEE ISCAS, Feb. 2012, pp. 1054-1057. [l5] R. Xu et ai., " Digitally calibrated 758-kS/s IO-b min- imum-size SAR ADC array with dithering, IEEE JSSC, vol. 47, no. 9, pp. 2129-2140, Sep. 2012.
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