AlN/GaN MOS-HEMTs With Thermally Grown Al2O3 ... - IEEE Xplore

1418

IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 58, NO. 5, MAY 2011

AlN/GaN MOS-HEMTs With Thermally Grown Al2O3 Passivation Sanna Taking, Student Member, IEEE, Douglas MacFarlane, and Edward Wasige, Member, IEEE

Abstract—This paper reports on the processing and characterization of AlN/GaN metal–oxide–semiconductor high-electron mobility transistors (MOS-HEMTs). The devices employ thermally grown Al2 O3 as a gate dielectric and surface protection and passivation, which is an approach that provides an opportunity to define the ohmic contact areas by wet etching of Al (and optimization of this processing step) prior to the formation of Al2 O3 and ohmic metal deposition. The devices also employ a new process technique that significantly suppresses leakage currents on the mesa sidewalls. Fabricated devices exhibited good direct current and radio frequency performance. A high peak current, i.e., ∼1.5 A/mm, at VGS = +3 V and a current-gain cutoff frequency fT and maximum oscillation frequency fMAX of 50 and 40 GHz, respectively, were obtained for a device with 0.2-μm gate length and 100-μm gate width. Additionally, a robust method for the extraction of the small-signal equivalent circuit suitable for process optimization is described. It relies on intimate process knowledge and device geometry to determine equivalent circuit elements of the fabricated AlN/GaN MOS-HEMTs. Index Terms—AlGaN/GaN, AlN/GaN, Al2 O3 , equivalent circuit, high-electron mobility transistor (HEMT), metal–oxide– semiconductor (MOS)-HEMT, small-signal model, thermal oxidation, wet etching.

I. I NTRODUCTION

T

O DATE, GaN-based high-electron mobility transistors (HEMTs), particularly AlGaN/GaN devices have demonstrated state-of-the-art performance in terms of power density and cutoff frequency [1], [2]. With the impressive achievements on the device level, high-power amplifier monolithic microwave integrated circuits up to Ka-band have been also realized [3], [4]. Today, the demand for higher power devices at higher frequencies is very strong. Therefore, the performance of GaNbased HEMTs is being pushed to achieve maximum power and speed levels possible. In order to increase further the twodimensional electron gas (2-DEG) density and the breakdown field in the AlGaN/GaN structure, high Al mole fraction is desirable to increase the strength of polarization. However, from a growth perspective, it is difficult to grow high-quality Alx Ga1−x N layers with high-Al content, which results in poor transport properties of Alx Ga1−x N/GaN structures with x >

Manuscript received November 16, 2010; revised January 28, 2011; accepted February 4, 2011. Date of publication March 3, 2011; date of current version April 22, 2011. The review of this paper was arranged by Editor A. Haque. The authors are with the High Frequency Electronics Research Group, School of Engineering, University of Glasgow, G12 8LT Glasgow, U.K. (e-mail: [email protected]). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TED.2011.2114665

0.5 [5]. To overcome this problem, the ultrathin all-binaryAlN/GaN material system, which can be reliably grown, has become an alternative candidate for future high-frequency power applications. Due to the large difference in spontaneous and piezoelectric polarizations between the GaN and AlN layers, the 2-DEG that forms near the AlN/GaN interface can reach over 3 × 1013 cm−2 for an extremely thin AlN barrier layer thickness (d < 5 nm), along with high mobility (> 1000 cm2 /V · s) and very low sheet resistance (Rsh < 150 Ω/sq) [6], [7]. In addition, AlN with its relatively high dielectric constant (8.5) and wide band gap (6.2 eV), provides better carrier confinement and has the potential to be an excellent choice for the gate dielectric. Compared with the AlGaN/GaN structure, the AlN/GaN structure offers a big reduction in alloy disorder scattering and roughness scattering (by removing Ga from the barrier) [8]. Having these superior properties potentially makes this material system have the highest performance HEMTs in the III–V nitrides. Indeed, outstanding record performances have been demonstrated for the AlN/GaN device family such as drain current densities of 2.9 A/mm [9], transconductance of 480 mS/mm [10], a current gain cutoff frequency fT of 107 GHz, and a maximum oscillation frequency fMAX of 171 GHz [11]. The record current density in [9] and the transconductance in [10] that were reported were, however, for very narrow devices, i.e., 0.15 μm × 10 μm and 0.25 μm × 12.5 μm gate sizes, respectively, and therefore, the device performance was not limited, for instance, by heating effects. Despite the excellent progress of AlN/GaN devices to date, there are still significant challenges to be overcome before the potential of this material system can be fully realized. Apart from the difficulty of realizing good ohmic contacts on the wide-band-gap AlN barrier layer, devices suffer from surface sensitivity and high leakage currents if the epilayers are not protected during processing. The AlN layer is well known to be very sensitive because it is very thin [12], [13]. Additionally, unlike other nitrides, AlN is easily attacked/etched by common processing solutions, e.g., AZ 400K photoresist developer [14]. Therefore, the gate dielectric and surface passivation play an important role in AlN/GaN devices, suppressing gate leakage currents and protecting the epitaxial layers during device processing. However, in the presence of the protective/ passivation layers such as Al2 O3 or Si3 N4 , formation of low ohmic resistance source and drain contacts can be challenging. These protective/passivation layers need to be removed or etched prior to ohmic metallization. The etching of Al2 O3 is difficult, and only very well optimized processes such as using a timed low-power inductively coupled plasma (ICP) to etch

0018-9383/$26.00 © 2011 IEEE

TAKING et al.: AlN/GaN MOS-HEMTs WITH THERMALLY GROWN AL2 O3 PASSIVATION

the atomic layer deposited (ALD) Al2 O3 layer prior to ohmic metallization produces low resistance ohmic contacts [13]. On the other hand, for patterning of Si3 N4 , either HF acid or buffered oxide etch (BOE) may be used or dry etching with SF6 . Both HF and BOE easily attack AlN [15], and therefore because of this, many reports using Si3 N4 , the ohmic metallization is deposited directly on the Si3 N4 , thereby resulting in high contact resistances [11], [16]. This paper describes the processing and direct current (dc) and radio frequency (RF) characteristics of high-power high-frequency AlN/GaN metal–oxide–semiconductor (MOS)HEMT devices that employ thermally grown Al2 O3 as a gate dielectric and for surface passivation [12]. This approach provides an opportunity to define the ohmic contact areas by the wet etching of Al using 16H3 PO4 : HNO3 : 2H2 O solution [17]. The results from the optimization of wet etching prior to Al2 O3 formation and ohmic metallization will be reported. For RF devices (which employ mesa isolation), the leakage currents are not confined on the active area region but also along the mesa sidewalls, particularly in the region where the gate metallization overlaps with the exposed channel edge [18]. A process technique to suppress these currents will be described. In addition, the small-signal model values for a two-finger 0.2 × 200 μm AlN/GaN MOS-HEMT will be discussed as they also provide feedback for process optimization.

1419

Fig. 1. Top-view SEM micrograph of completed device with protected mesa sidewall edge. Device gate length is 0.2 μm.

using photolithography. DC and RF measurements were made at room temperature using Agilent’s B1500A Semiconductor Device Analyzer and E8361A PNA Network Analyzer, respectively. Fig. 1 shows the top-view scanning electron microscope (SEM) micrograph of completed device with a gate length of 0.2 μm. A summary of the processing steps, including sidewall protection, is shown in Fig. 2. As will be detailed in Section III, devices without mesa sidewall protection were initially fabricated, but their poor performance led to the development of the sidewall passivation process.

II. D EVICE S TRUCTURE AND FABRICATION The AlN/GaN HEMT structures used in this paper were grown by SVT Associates, USA, using molecular beam epitaxy on sapphire substrate (0001) with 2-DEG concentration of 2.2 × 1013 cm−2 and a mobility of 1250 cm2 /V · s. The electrical properties of the heterostructure were characterized by Hall measurements at room temperature. The epitaxial wafer consists of (from top to bottom), a 1-nm GaN cap layer, 3-nm AlN, 3.8-μm GaN, and a very thin AlN buffer layer. All of the layers were undoped (unintentionally doped). Device fabrication starts with sample cleaning and deoxidation using HCl : 4H2 O solution. Al of 2 nm was then deposited on the sample surface using electron beam evaporation. Next, mesa isolation was performed by reactive ion etching using SiCl4 gas with chamber conditions of 75 W, 30 sccm, and 30 mT. The mesa etch depth was measured using the Dektak profilometer and gave an average value of ∼120 nm. Al of 2 nm was then deposited on the mesa sidewall using a liftoff process. The 2 nm of Al in the source and drain regions was etched using 16H3 PO4 : HNO3 : 2H2 O solution, followed by oxidation of the remaining Al layer using rapid thermal annealing at 550 ◦ C for 10 min in an O2 environment to form the Al2 O3 [19]. The extracted thickness of the thermally grown Al2 O3 from capacitance–voltage (C–V ) measurements is ∼3 nm [12]. Ohmic metal contacts were formed by evaporation of Ti/Al/Ni/Au, followed by a liftoff process then annealed at 800 ◦ C for 30 s. Gate metal contacts were formed by evaporation of Ni/Au. Finally, the bondpad metal, i.e., NiCr/Au, was deposited for device characterization. Ohmic and gate contacts steps were defined using electron beam lithography for patterning accuracy. All other fabrication steps were defined

III. O HMIC C ONTACTS O PTIMIZATION In our earlier work [12], we found that the AlN/GaN structures are very sensitive to processing liquids, confirming earlier reports [13], [15], and therefore, thermally grown Al2 O3 was used to protect the epistructure. Al2 O3 is also expected to act as a passivation layer [20]. Fig. 3 shows the transistor output characteristics of the device made without the Al/Al2 O3 layer. The device showing very high leakage currents did not pinch off, and the drain current was low. Exposure to developer solutions or solvents such as acetone and isopropanol during processing seems to degrade the quality of the epilayer structure, resulting in the poor device performance. For the Al-protected samples, Al in the ohmic contact regions is etched with 16H3 PO4 : HNO3 : 2H2 O solution prior to oxidation of the Al covering the rest of the device. The Al etching time was optimized, and Fig. 4(a) shows the measured I–V characteristics on 5-μm transmission line method (TLM) gap spacing of annealed ohmic contacts for different Al etch times. A 20-s etch resulted in the lowest contact resistance of 0.49 Ω · mm, which is also one of the lowest contact resistance values for this material system. If the sample was left longer in the etchant, the contact resistance rose, indicating that further undesirable reactions may be taking place. Unlike other techniques for AlN epilayer protection, the thermally grown Al2 O3 technique described here allows for a simple and effective wet etching optimization technique for the ohmic contact resistance. For the comparable ALD grown Al2 O3 , a more complicated, expensive dry etch is required to optimize the ohmic contacts [13]. The summary results of the TLM measurements for both protected and unprotected

1420


Fig. 2. Device processing summary: (a) mesa etch for device isolation; (b) 2-nm Al deposition on mesa sidewall edge; (c) 2-nm of Al covers the sample surface; (d) etch ohmic regions and thermal oxidation of Al, then, ohmic metallization and annealing, followed by gate metallization; and (e) cross section (X–Y) of completed device with protected mesa sidewall edge (refer to Fig. 1).

Fig. 3. IDS –VDS characteristics of fabricated unprotected AlN/GaN HEMT device.

samples are shown in Fig. 4(b). The details of the optimized processing on ohmic contacts experiments were reported in [17]. Unprotected samples had a lower ohmic contact resistance of 0.31 Ω · mm, compared with 0.49 Ω · mm for the protected samples. A possible explanation to this reduced contact resistance is that the chemicals have thinned the AlN layer, and therefore, the ohmic contact is formed closer to the 2-DEG, resulting in a lower contact resistance. Similar or better results are expected for devices protected with thermally grown Al2 O3 samples after further optimization. A comparison between the measured contact resistance RC with other published work for AlN/GaN-based devices is shown in Fig. 4(c). Devices without mesa isolation were initially made using the gate wrap-around technique [23], which is a simple twolevel lithography process for fabricating dc devices. Typical IDS –VDS characteristics of the fabricated 3 μm × 100 μm gate AlN/GaN MOS-HEMT devices for two different etching times prior to ohmic metallization are shown in Fig. 4(d). It is clear that a 20-s Al etch has a significant impact on the device performance with the drain current at zero gate voltage IDSS more than double that of a device in which the etching time was 10 s, corroborating the TLM results given in Fig. 4(a). The devices (using optimized processes) exhibited excellent dc characteristics, and therefore, based on this, the process was extended to realize the RF devices employing mesa isolation and thermally grown Al2 O3 passivation.

IV. E XPERIMENTAL D EVICE R ESULTS Fig. 4. (a) Current–voltage (I–V ) characteristics on 5-μm TLM gap spacing of annealed ohmic contacts for different Al etch times; (b) results of the TLM measurements. For the protected (MOS-HEMT) sample, the measured value of RC and Rsh is 0.49 Ω · mm and 159 Ω/sq, whereas for the unprotected sample, the measured value of RC and Rsh is 0.31 Ω · mm and 450 Ω/sq, (c) Comparison of the ohmic contact resistance RC on AlN/GaN-based devices as a function of annealing temperatures from various publications and (d) the IDS –VDS characteristics of fabricated AlN/GaN MOS-HEMT devices with different etching times using the simplified gate wrap-around method. The devices are biased from VGS = +3 to − 4 V with step size of 1 V.

Initially, the RF devices were fabricated without the mesa sidewall protection and with an unoptimized ohmic contact process. These devices exhibited high knee voltages (high ohmic contact resistance) and did not fully pinch off. The reason for the high leakage currents seemed to be the contact between the gate metal and the exposed mesa sidewalls. Fig. 5(a) shows the IDS –VDS characteristics for both unprotected and protected mesa sidewall devices.


Fig. 5. (a) IDS –VDS characteristics of fabricated two-finger 3-μm gate length AlN/GaN MOS-HEMT devices with unprotected mesa sidewall and unoptimized etching time (10 s). In addition, shown is a device with protected mesa sidewall and with an optimized etching time (20 s). The devices are biased from VGS = +3 to − 4 V, with step size of 1 V and (b) the measured leakage current of unprotected and protected devices.

Fig. 6. DC characteristics of the fabricated two-finger 0.2-μm gate length AlN/GaN MOS-HEMT (a) ∼ IDS –VDS characteristics and (b) ∼ Gm − VGS characteristics at VDS = 4 V.

Devices were therefore insulated with an additional layer of thermally grown Al2 O3 on the mesa sidewall edge, as shown in Fig. 2(e). The protected device suppresses the leakage current by about 1order of magnitude, as compared with the unprotected device, as shown in Fig. 5(b). The leakage current at VGS = −4 V and VDS = 10 V was 0.3 and 0.06 mA/mm for the unprotected and protected devices, respectively. Two-finger 3 μm × 100 μm devices biased at VDS = 4 V and VGS = −1 V exhibited a unity current gain cutoff frequency fT and power gain cutoff frequency fMAX of 2.8 and 7.9 GHz, respectively, which is a good RF performance for these long gate devices. Devices with a shorter gate length of 0.2 μm and gate widths of 100 and 200 μm were also fabricated using the process with mesa sidewall protection. The measured drain current and the transconductance characteristics of the devices are shown in Fig. 6 and are observed to decrease for the larger gate width devices. This is attributed to more pronounced self-heating effects in the wider devices. fT and fMAX of 50 and 40 GHz, respectively, were achieved for the 2 × 100 μm wide devices, and of 45 and 21 GHz, respectively, for the 2 × 200 μm wide devices (see Fig. 7). The present devices demonstrate comparable cutoff frequencies and current capabilities to AlGaN/GaN HEMT technology for similar gate lengths and will surpass this technology once better ohmic contacts are developed. Pulse measurements were carried out to investigate the trapping effects in the devices. Fig. 8(a) shows the pulse I–V characteristics of a two-finger 0.5-μm gate length AlN/GaN MOS-HEMT with different pulsewidth conditions. The selfheating effects were observed during the 1-μs pulses and were suppressed by shortening the pulsewidth to 200 ns. However, a current collapse up to 20% was observed for 200-ns pulses.

1421

Fig. 7. Small-signal RF performances of fabricated two-finger 0.2-μm gate length AlN/GaN MOS-HEMT with different gate widths. The devices are biased at VGS = −3 V and VDS = 10 V.

Fig. 8. (a) Pulse I–V characteristics of two-finger AlN/GaN MOS-HEMT (quiescent bias point: VDS = 0 V and VGS = 0 V) and (b) the OFF-state breakdown-voltage characteristics.

This indicates the presence of bulk-defect-related traps and/or surface-related traps. The OFF-state breakdown voltage characteristics are shown in Fig. 8(b). The breakdown voltage VBR of a two-finger MOS-HEMT with 0.5-μm gate length was 58 V. The total source–drain distance of the device was 3.5 μm, resulting in an associated electric field of 17 V/μm (170 kV/cm). For an AlGaN/GaN HEMT, of similar device dimensions, the measured breakdown voltage was 42 V, giving a lower electric field of 14 V/μm (140 kV/cm) [24]. The higher breakdown field for AlN/GaN structure is consistent with the wider band-gap barrier layer, but in both cases, this can be further enhanced by the inclusion of a field plate [1]. V. S MALL -S IGNAL E QUIVALENT C IRCUIT E XTRACTION To further investigate the AlN/GaN device characteristics, small-signal equivalent circuit model values were extracted for a two-finger device with gate length of 0.2 μm and gate width of 200 μm. The small-signal equivalent circuit model used in this paper is shown in Fig. 9 and is based on that used in previous GaN-based HEMT small-signal models [25]. The extrinsic elements include the pad capacitances Cpg , Cpgd , and Cpd ; the pad inductances Lg , Ld , and Ls ; and the gate and access resistances Rg , Rd , and Rs . They are bias independent, except for the source resistance Rs [26]. The other parameters are intrinsic elements and are bias dependent. The small-signal equivalent circuit modeling approach used here takes advantage of the known device geometry and processing information. All equivalent circuit elements can be estimated fairly accurately on this basis and then optimized against the measured S-parameters to get the actual element

1422


TABLE I SMALL-SIGNAL EQUIVALENT CIRCUIT EXTRINSIC ELEMENTS AT VGS = −3 V AND VDS = 10 V

Fig. 9. HEMT small-signal equivalent circuit model.

values. This is a well-known approach in multivariable optimization problems, where a starting vector close to the actual solution leads to quick convergence and determination of the correct optimized solution [27]. Agilent’s Momentum software (a 3-D electromagnetic simulator used for passive circuit modeling and analysis [28]) was used to model the transistor pads from which an estimate of the values for the extrinsic capacitances Cpg , Cpgd , and Cpd and inductances Lg , Ls , and Ld was made. The capacitances were extracted from simulated S-parameters of the pads without the transistor (open circuit in place of transistor) and modeled as a π-network consisting of Cpg , Cpgd , and Cpd . The inductances were extracted from the shorted pad structure (transistor replaced by a short circuit) modeled by a T-network consisting of Lg , Ls , and Ld [29]. The source and drain resistances, on the other hand, are estimated from the TLM measurements (contact and sheet resistances) and the transistor geometry. By knowing the ohmic contact resistance RC (in Ω · mm), and the width of the active device W , the resistance of each contact area Rt can be estimated using the equation RC = Rt · W . From the device geometry, the drain and source resistances were estimated to be 2.5 and 3.5 Ω, respectively. The gate resistance was estimated by knowing the dimensions and resistivity of the metals used. An estimate of 38 Ω was made. The estimated extrinsic elements are de-embedded from the measured S-parameters, and the resulting parameters, when expressed as Y-parameters, are uniquely related to the intrinsic elements, which can then be analytically calculated [30]. With all the element values known, the complete model was simulated in Agilent’s Advanced Design System software, and a comparison between the modeled and measured S-parameters was made. Optimization of the estimated element values to fit the measured S-parameters is necessary since uncertainties such as fabrication tolerances (line widths, spacing), probe tip placement, and variation in the epilayers across a wafer mean that the computed extrinsic (and therefore also intrinsic element values) are only estimates (albeit quite close to the actual values). The gradient optimization routine was used. Tables I and II give details on the values of the extracted model elements. All element values required some degree of optimization; however, it should be noted that the values do

TABLE II SMALL-SIGNAL EQUIVALENT CIRCUIT INTRINSIC ELEMENTS AT VGS = −3 V AND VDS = 10 V

Fig. 10. Modelled and measured S-parameters of AlN/GaN MOS-HEMTs at the frequency range of 1–20 GHz: (a) S11 , S12 , and S22 ; (b) S21 dB versus frequency; and (c) S21 phase versus frequency.

not vary so much that initial estimations could be completely disregarded. Fig. 10 shows a good fit between the measured and modeled S-parameters from 1–20 GHz, suggesting that the model topology and approach for determining element values is justified. The extracted gate resistance is very high, i.e., ∼ 37 Ω, probably explaining the lower value of fMAX , compared with fT . This high resistance is due to the gate having a vertical structure (adopted because of simpler processing).


Therefore, a T-gate structure will be used in future devices. Contact resistances also need further reducing. VI. C ONCLUSION The use of thermally grown Al2 O3 as a gate dielectric and device passivation for AlN/GaN MOS-HEMTs has been described and discussed. The developed approach provides an opportunity to define the ohmic regions using wet etching technique. Significant improvement in device performance was observed using the following techniques: 1) ohmic contact optimization using Al wet etch prior to ohmic metal deposition and 2) mesa sidewall protection. As the technology matures, the bulk-related traps would reduce, thereby improving the device performance. The extracted small-signal equivalent circuit model values showed good agreement with the measured S-parameters data up to 20 GHz and importantly provided feedback for further device process optimization. The achieved results indicate the potential of thermally grown Al2 O3 for AlN/GaN-based MOS-HEMT technology for future high-frequency power applications.

[11] [12]

[13]

[14] [15]

[16] [17]

[18]

ACKNOWLEDGMENT The authors would like to thank staff at the James Watt Nanofabrication Centre, University of Glasgow, for supporting and assisting this work and Dr. A. Dabiran of SVT Associates for the growth of the epitaxial wafers used in this work. R EFERENCES [1] Y.-F. Wu, A. Saxler, M. Moore, R. P. Smith, S. Sheppard, P. M. Chavarkar, T. Wisleder, U. K. Mishra, and P. Parikh, “30-W/mm GaN HEMTs by field plate optimization,” IEEE Electron Device Lett., vol. 25, no. 3, pp. 117– 119, Mar. 2004. [2] M. Higashiwaki, T. Mimura, and T. Matsui, “AlGaN/GaN heterostructure field-effect transistors on 4H-SiC substrates with current-gain cutoff frequency of 190 GHz,” Appl. Phys. Express, vol. 1, no. 2, p. 021 103, 2008. [3] M. van Heijningen, F. E. van Vliet, R. Quay, F. van Raay, R. Kiefer, S. Muller, D. Krausse, M. Seelmann-Eggebert, M. Mikulla, and M. Schlechtweg, “Ka-band AlGaN/GaN HEMT high power and driver amplifier MMICs,” in Proc. EGAAS, 2005, pp. 237–240. [4] A. M. Darwish, K. Boutros, B. Luo, B. Huebschman, E. Viveiros, and H. A. Hung, “AlGaN/GaN Ka-Band MMIC 5-W amplifier,” IEEE Trans. Microw. Theory Tech., vol. 54, no. 12, pp. 4456–4463, Dec. 2006. [5] F. Nakamura, S. Hashimoto, M. Hara, S. Imanaga, M. Ikeda, and H. Kawai, “AlN and AlGaN growth using low-pressure metalorganic chemical vapor deposition,” J. Cryst. Growth, vol. 195, no. 1–4, pp. 280– 285, Dec. 1998. [6] H. Xing, D. Deen, Y. Cao, T. Zimmermann, P. Fay, and D. Jena, “MBEgrown ultra-shallow AlN/GaN HFET technology,” ECS Trans., vol. 11, no. 5, pp. 233–237, 2007. [7] A. M. Dabiran, A. M. Wowchak, A. Osinsky, J. Xie, B. Hertog, B. Cui, D. C. Look, and P. P. Chow, “Very high channel conductivity in low-defect AlN/GaN high electron mobility transistor structures,” Appl. Phys. Lett., vol. 93, no. 8, pp. 082 111-1–082 111-3, Aug. 2008. [8] Z. Bougrioua, J.-L. Farvacque, I. Moerman, and F. Carosella, “2DEG mobility in AlGaN-GaN structures grown by LP-MOVPE,” Phys. Stat. Sol. (B), vol. 228, pp. 625–628, 2001. [9] Y. Cao, T. Zimmermann, D. Deen, J. Simon, J. Bean, N. Su, J. Zhang, P. Fay, H. Xing, and D. Jena, “Ultrathin MBE-grown AlN/GaN HEMTs with record high current densities,” in Proc. Int. Semicond. Device Res. Symp., College Park, MD, 2007, vol. 1/2, pp. 407–408. [10] T. Zimmermann, D. Deen, Y. Cao, J. Simon, P. Fay, D. Jena, and H. G. Xing, “AlN/GaN insulated-gate HEMTs with 2.3 A/mm output

[19]

[20]

[21]

[22]

[23]

[24] [25]

[26]

[27] [28] [29]

[30]

1423

current and 480 mS/mm transconductance,” IEEE Electron Device Lett., vol. 29, no. 7, pp. 661–664, Jul. 2008. M. Higashiwaki, T. Mimura, and T. Matsui, “AlN/GaN insulated-gate HFETs using Cat-CVD SiN,” IEEE Electron Device Lett., vol. 27, no. 9, pp. 719–721, Sep. 2006. S. Taking, A. Banerjee, H. Zhou, X. Li, A. Z. Khokhar, R. Oxland, I. McGregor, S. Bentley, F. Rahman, I. Thayne, A. M. Dabiran, A. M. Wowchak, B. Cui, and E. Wasige, “Surface passivation of AlN/GaN MOS-HEMTs using ultra-thin Al2 O3 formed by thermal oxidation of evaporated aluminium,” Electron. Lett., vol. 46, no. 4, pp. 301–302, Feb. 2010. K. Chabak, A. Crespo, D. Tomich, D. Langley, V. Miller, M. Trejo, J. K. Gillespie, and G. D. Via, “Processing methods for low Ohmic contact resistance in AlN/GaN MOSHEMTs,” in Proc. CS MANTECH Conf., Tampa, FL, May 18–21, 2009. S. Seo, G. Y. Zhao, and D. Pavlidis, “Power characteristics of AlN/GaN MISFETs on sapphire substrate,” Electron. Lett., vol. 44, no. 3, pp. 244– 245, Jan. 2008. C. Y. Chang, T. J. Anderson, F. Ren, S. J. Pearton, A. M. Dabiran, A. M. Wowchak, B. Cui, and P. P. Chow, “Very low sheet resistance AlN/GaN high electron mobility transistors,” in Proc. CS MANTECH Conf., Tampa, FL, May 18–21, 2009. S. Seo, E. Cho, and D. Pavlidis, “Improvements of AlN/GaN MISFET DC and RF characteristics with in situ deposited Si3 N4 ,” Electron. Lett., vol. 44, no. 24, pp. 1428–1429, Nov. 2008. S. Taking, A. Z. Khokhar, D. MacFarlane, S. Sharabi, A. M. Dabiran, and E. Wasige, “New process for low sheet and Ohmic contact resistance of AlN/GaN MOS-HEMTs,” in Proc. 5th EuMIC, Paris, France, 2010, pp. 306–309. M. Marso, K. Schimpf, A. Fox, A. van der Hart, H. Hardtdegen, M. Hollfelder, P. Kordos, and H. Luth, “Novel HEMT layout: The roundHEMT,” Electron. Lett., vol. 31, no. 7, pp. 589–591, Mar. 1995. H. Chen, J. Wang, C. Xu, M. Yu, Y. Fu, Z. Dong, F. Xu, Y. Hao, and C. P. Wen, “Enhanced device performance of AlGaN/GaN HEMTs using thermal oxidation of electron-beam deposited aluminum for gate oxide,” in Proc. 9th ICSICT, 2008, pp. 1443–1446. T. Hashizume, S. Ootomo, and H. Hasegawa, “Suppression of current collapse in insulated gate AlGaN/GaN heterostructure field-effect transistors using ultrathin Al2 O3 dielectric,” Appl. Phys. Lett., vol. 83, no. 14, pp. 2952–2954, Oct. 2003. T. Ide, M. Shimizu, A. Suzuki, X.-Q. Shen, H. Okumura, and T. Nemoto, “AlN/GaN Metal insulator semiconductor field effect transistor using wet chemical etching with hot phosphoric acid,” Phy. Stat. Sol. (A), vol. 188, no. 1, pp. 351–354, Nov. 2001. D. A. Deen, D. F. Storm, D. S. Katzer, D. J. Meyer, and S. C. Binari, “Dependence of Ohmic contact resistance on barrier thickness of AlN/GaN HEMT structures,” Solid State Electron., vol. 54, no. 6, pp. 613–615, Jun. 2010. R. J. W. Hill, D. A. J. Moran, X. Li, H. Zhou, D. Macintyre, S. Thoms, A. Asenov, P. Zurcher, K. Rajagopalan, J. Abrokwah, R. Droopad, M. Passlack, and I. G. Thayne, “Enhancement-mode GaAs MOSFETs with an In0.3 Ga0.7 As channel, a mobility of over 5000 cm2 /V.s, and transconductance of over 475 μS/μm,” IEEE Electron Device Lett., vol. 28, no. 12, pp. 1080–1082, Dec. 2007. A. Vertiatchikh, W. J. Schaff, L. F. Eastman, and A. Matulionis, “Frequency and breakdown properties of AlGaN/GaN HEMTs,” in Proc. Int. Symp. Compd. Semicond.: Post-Conf. Proc., 2003, pp. 132–137. F. Qian, J. H. Leach, and H. Morkoc, “Small signal equivalent circuit modeling for AlGaN/GaN HFET: Hybrid extraction method for determining circuit elements of AlGaN/GaN HFET,” Proc. IEEE, vol. 98, no. 7, pp. 1140–1150, Jul. 2010. T. Palacios, S. Rajan, A. Chakraborty, S. Heikman, S. Keller, and S. P. DenBaars, “Influence of the dynamic access resistance in the gm and ft linearity of AlGaN/GaN HEMTs,” IEEE Trans. Electron Devices, vol. 52, no. 10, pp. 2117–2123, Oct. 2005. A. Jarndal and G. Kompa, “A new small signal modeling approach applied to GaN devices,” IEEE Trans. Microw. Theory Tech., vol. 53, no. 11, pp. 3440–3448, Nov. 2005. Agilent, Genesys 2008.01 Documentation Set, Jan. 1, 2008. [Online]. Available: http://www.home.agilent.com B. Sheinman, E. Wasige, M. Rudolph, R. Doerner, V. Sidorov, S. Cohen, and D. Ritter, “A peeling algorithm for extraction of the HBT small signal equivalent circuit,” IEEE Trans. Microw. Theory Tech., vol. 50, no. 12, pp. 2804–2810, Dec. 2002. M. Berroth and R. Bosch, “Broad-band determination of the FET small signal equivalent circuit,” IEEE Trans. Microw. Theory Tech., vol. 38, no. 7, pp. 891–895, Jul. 1990.

1424


Sanna Taking (S’11) graduated with the B.Eng. degree in electrical, electronic, and systems engineering in 2001 and the M.Sc.(Eng.) degree in microelectronics in 2003 from the Universiti Kebangsaan Malaysia, Bangi, Selangor, Malaysia. She is on study leave from the Universiti Malaysia Perlis, Kangar, Malaysia, and is currently working toward the Ph.D. degree in the area of GaN-based technology at the University of Glasgow, Glasgow, U.K. Her research interests include high-frequency power device fabrication, characterization, and modeling for microwave applications.

Douglas MacFarlane received the B.Eng. degree in electronics and electrical engineering from the University of Glasgow, Glasgow, U.K., in 2009, where he is currently working toward the Ph.D. degree. His research interests include small-signal modeling, high-frequency power amplifier design, and thermal management issues, all associated with GaN-based devices.

Edward Wasige (S’97–M’02) received the B.Sc.(Eng.) degree in electrical engineering from the University of Nairobi, Nairobi, Kenya, in 1988, the M.Sc.(Eng.) degree in microelectronic systems and telecommunications from the University of Liverpool, Liverpool, U.K., in 1990, and the Dr.-Ing. degree in electrical engineering from the University of Kassel, Kassel, Germany, in 1999. His doctoral research involved the development of a Si–GaAs quasi-monolithic hybrid technology for microwave and millimeter-wave applications. He was a Lecturer with Moi University, Eldoret, Kenya, and was a United Nations Educational, Scientific and Cultural Organization Postdoctoral Fellow at the Technion–Israel Institute of Technology, Haifa, Israel. Since 2002, he has been with the University of Glasgow, Glasgow, U.K. His current research interests include the reliable design of resonant tunneling diode microwave and millimeter-wave oscillators, and the development of new types of gallium nitride-based heterojunction field-effect transistors for power electronics and high-power microwave applications.