An All-Digital Fast-Locking Programmable DLL-Based Clock Generator

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Abstract—An all-digital fast-locking programmable DLL-based clock generator is presented. By resetting the output clock every two input clock periods, the initial ...
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 55, NO. 1, FEBRUARY 2008

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An All-Digital Fast-Locking Programmable DLL-Based Clock Generator Chuan-Kang Liang, Student Member, IEEE, Rong-Jyi Yang, Member, IEEE, and Shen-Iuan Liu, Senior Member, IEEE

Abstract—An all-digital fast-locking programmable DLL-based clock generator is presented. By resetting the output clock every two input clock periods, the initial minimal delay constraint in the conventional architecture is eliminated. Compared with the previous work, the short locking time is also achieved. The proposed circuit has been fabricated in 0.35- m CMOS process and occupies the active area of 0.216 mm2 . The clock multiplication ratio is programmed from 2 to 15. The frequency ranges of the input and output clocks are 4 200 MHz and 60 450 MHz, respectively. It dissipates less than 17 mW at all operating frequencies from a 3.3-V supply. Index Terms—All-digital delay-locked loop (DLL), clock generator, clock multiplier, fast-locking, frequency synthesizer.

I. INTRODUCTION

Fig. 1. Proposed all-digital clock generator.

M

ANY ON-CHIP clock generators in high-performance systems utilize phase-locked loops (PLLs) to achieve high frequencies and programmable clock multiplications. However, a PLL is a higher order system and it may have stable problems. Process, voltage, and temperature (PVT) variations may influence the loop characteristics and hence increase the design difficulties. In addition, the voltage-controlled oscillators (VCOs) in the PLLs will accumulate the jitter. On the contrary, the jitter is corrected when a clean reference arrives at the delay-locked loops (DLLs). Also, a DLL is a first-order system without stability considerations. Therefore, the DLL-based clock generator is attractive in noisy environments. Two kinds of DLL-based clock generators have been presented by using the multiphase clock mixing [1]–[3] and the cyclic wave generations [4]–[8]. Although the former [1]–[3] combines the multiphase clocks in the delay lines to achieve the frequency multipliers, the multiplication ratio is usually correlated with the number of delay cells in the delay lines, and it is difficult to program. Moreover, it suffers from duty cycle error caused by the delay cell mismatch. It also needs to avoid the false lock or harmonic lock to obtain the multiphase clocks uniformly distributed with one period. The latter [4]–[8], called a multiplying delay-locked loop (MDLL), uses the cyclic wave to multiply the clock. The delay elements form a ring oscillator and transform into a delay line every reference cycle. Hence, the MDLL behaves like a DLL and has the capability to multiply the clock frequency like a PLL [4]. Since the output clock is generated through the same delay line, it avoids duty cycle

inaccuracy. However, there are some problems in an MDLL. First, an MDLL has a locking initial constraint that it has to operate from the shortest delay line. Environmental variations resulting in a longer delay line may make an MDLL reset to prevent the locking failure. If the variation disappears quickly, resetting the system to lock wastes time. If the variation is periodic, the system would reset again and again and lose the ability to lock. Second, unlike a PLL-based clock generator, an MDLL cannot switch the clock frequency from low to high. Third, the approach takes a long time to lock since it is an analog feedback system. In this paper, an all-digital fast-locking programmable DLLbased clock generator is presented. To resolve the initial delay constraint in the conventional MDLL, a new locking method is adopted, and the digital phase-frequency detector is proposed. Moreover, the modified successive approximation register-controlled (MSAR) circuit is used to achieve a short locking time and tracks the environmental variations. In addition, this all-digital clock generator releases the effects of PVT variations and prevails in scaling down technology. This paper is organized as follows. Section II shows the system architecture and Section III is the circuit description. Section IV gives the performance analysis of the proposed circuit. Section V shows the experimental results, and Section VI gives the conclusions. II. SYSTEM ARCHITECTURE

Manuscript received October 3, 2006; revised March 3, 2007. This paper was recommended by Associate Editor P. Heydari. The authors are with Graduate Institute of Electronics Engineering and the Department of Electrical Engineering, National Taiwan University, Taipei, Taiwan 10617, R.O.C. (e-mail: [email protected]). Digital Object Identifier 10.1109/TCSI.2007.913612

Fig. 1 shows the proposed DLL-based clock generator. It is mainly composed of the MSAR circuit, a timing control circuit, a digital phase-frequency detector (PFD), and a digitalcontrolled delay line. According to the different operations in

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Fig. 2. Timing diagram of the clock generator with the multiplication ratio of 4.

the MSAR circuit, this clock generator is divided into two operating modes. One is the binary-search mode and the other is the sequential-search mode. Each mode has two execution cycles in turn, i.e., the refresh cycle and the compare cycle. Differing from the conventional MDLL, refreshed every reference cycle, using two execution cycles to refresh the output clock could eliminate the initial constraint since the detection time and refresh time are separated. Therefore, the longer delay line could be detected without violating the refresh time. The timing diagram is shown in Fig. 2 with the external divisor of 4. The binary-search algorithm cannot be applied to the conventional MDLL, since the initial minimum delay constraint exits. The proposed two-cycle refreshing technique can solve the initial delay constraint and achieve the fast-locking time by using the MSAR circuit. However, the disadvantages of the proposed MDLL exist. The doubled accumulated jitter and a half-loop bandwidth are achieved, compared with the conventional architecture having the same loop parameters. When the signal “Start” is enabled, the MSAR circuit performs the binary search. This clock generator is in the binarysearch mode. In the refresh cycle, the signal “Select” goes high, and the rising edge of the internal clock (In_Clk) passes through the multiplexer and the digital-controlled delay line to correct the jitter accumulation in the output clock (Out_Clk). After the internal clock goes high, “Select” goes down immediately, and hence the multiplexer converters the delay line into a ring oscillator. The counter counts how many output clocks have been generated in the refresh cycle. The internal clock is divided by two to generate the signal “Reset_Counter.” At the beginning of the compare cycle, the falling edge of “Reset_Counter” stops the counter to assure that only the output clocks in the refresh cycle are counted. The counted number stored in the counter is compared with the external divisor by the PFD. In the compare cycle, the MSAR circuit adjusts the digital-controlled delay line according to the signal, “SAR_Clk” and “Compare” by using the binary search method. If the counted number is smaller than the desired one, “Compare” is low, and the digital-controlled delay line is shortened to

increase the output frequency and vice versa. When the next “Select” rises, the clock generator enters the refresh cycle again. The ring oscillator is disconnected and the process is repeated until the binary-search mode finishes. Because “Compare” is generated every two reference cycles, this 8-b MSAR circuit takes 16 cycles to lock. When the binary-search mode is complete, “Stop” goes high and then it causes the signal “En_Counter” to rise. The frequency acquisition is finished, and the clock generator enters the sequential-search mode. The MSAR circuit is converted into a counter. It allows this clock generator to operate in a closed loop to track the PVT variations and compensate for the undealt phase error in the binary-search mode. Once the clock generator enters the sequential-search mode, it will not go back to the binary-search mode unless the system is reset. Fig. 3 shows the timing diagram in the sequential-search mode. Since the proposed MDLL is a digital system, the digital-controlled code of the MSAR circuit in a closed loop may jump back and forth due to the finite quantization error even in the locked situation. In order to avoid this problem, a detection window is used. If the last desired output clock rises within the detection window, “En_Counter” is low and the code in the MSAR circuit sustains; otherwise, “En_Counter” is high and the code in the MSAR circuit is adjusted according to “Compare.” Consequently, the clock generator could track the environment variations and the phase error is corrected by sequentially increasing or decreasing the codes in the MSAR circuit. The detection window size directly influences the output clock jitter and the steady-state phase error. The small detection window may cause the loop behavior to vary by the jitter and the large one will result in a steady-state phase error. In this is determined by the study, the detection window size delay time between the reference clock (Ref_Clk) and the postponed clock (Post_Clk). The detection window size is chosen as a 1-LSB delay of the digital-controlled delay line and is shown in Fig. 4. If Out_Clk leads In_Clk by more than , the controlled code for the digital-controlled delay line

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Fig. 3. Timing diagram of the proposed clock generator in the sequential-search mode.

Fig. 4. Detection window.

(a)

increases by one. If Out_Clk lags In_Clk by more than , the controlled code decreases by one. Once the phase error , i.e., Out_Clk between In_Clk and Out_Clk is within is within the detection window, the controlled code is held. The detailed circuits are discussed in the next section. III. CIRCUIT DESCRIPTION A. MSAR Circuit The conventional SAR circuit stops the operation after the last bit is decided. So, the clock generator operates in an open loop and fails to track the PVT variations. The proposed MSAR circuit resolves this problem without an extra counter. The MSAR circuit performs the conventional binary search. Once the binary search is completed, the additional logics will enable the function of the counter to execute the closed loop tracking. Fig. 5(a) shows a one-bit cell for the MSAR circuit. In the dashed-line area of Fig. 5(a), two Exclusive-OR gates, an inverter, and a NOR gate are added to allow the sequential search. The remaining logic gates perform the binary search as in [9]. Fig. 5(b) shows the 8-b MSAR circuit. Since the carry-in signal “C_in” comes from the lower bit cell as shown in Fig. 5(b), “En_Counter” decides whether the sequential search is executed or not. When “En_Counter” is high, the carry-out signal “C_out” and the least significant bit (LSB), B7, propagate to the next stage and hence a counter is formed. When “En_Counter” is low, the carry-in signals in other cells keep low and the code of MSAR also holds. B. Timing Control Circuit In the timing control circuit, two important controlling signals are generated: “Select” and “SAR_Clk.” Since the sufficient operation time is needed to compare and adjust the delay line in a

(b) Fig. 5. (a) One-bit MSAR circuit. (b) Eight-bit MSAR circuit.

binary-search circuit [10], it is important to choose the proper clock, SAR_Clk, for the MSAR circuit. To guarantee that all signals in the MSAR circuit work properly, “SAR_Clk” should be sufficiently long, e.g., at least two input clocks. Fortunately, this two-cycle refreshing technique provides the clock SAR_Clk by dividing Ref_Clk by two with additional D-flip-flops to adjust its duty cycle as shown in Fig. 2. The SAR_Clk has the sufficient time to allow the MSAR circuit to complete its operation. To correct the jitter accumulations in the digital-controlled delay line, the signal “Select” is needed. In this study, “Select” is generated by the reference clock divided by 2 and the internal clock as shown in Fig. 6. Since the reference clock leads the internal clock, “Select” can always catch the rising edge of the internal clock correctly. However, in [4], “Select” is generated by the output clock and the delay time in a delay line affects the operation. Once the delay time is sufficiently long, “Select” in [4] disappears and the system does not sustain the locking process. The limitation of the new selection method is that the signal “Select” is no longer the appropriate window for the internal and the multiplied output clocks to compare. Hence, a new PFD is required to deal with the problem.

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Fig. 6. Circuit to generate the signal “Select.”

(a)

(a)

(b) (b) Fig. 7. (a) Proposed digital PFD. (b) detailed circuits of the SAR comparator and counter comparator.

C. Digital PFD This digital PFD consists of a SAR comparator, a counter comparator, and a multiplexer. Fig. 7(a) shows its sketch diagram and Fig. 7(b) is the detailed circuits of the two comparators. The SAR comparator is used in the binary-search mode when “En_Counter” is low. The counter comparator is adopted in the sequential-search mode when “En_Counter” is high. Fig. 8(a) and (b) shows the signal flow graphs for the proposed digital PFD in the binary-search and sequential-search modes, respectively. In the binary-search mode, the frequency acquisition is realized by comparing the counted number in the counter and the external divisor. If the counted number is less than the external divisor, the output signal (SAR_Comp) of the SAR comparator is low or else it is high.

Fig. 8. (a) Signal flow for the PFD in the binary-search mode. (b) Signal flow for the PFD in the sequential-search mode.

After the frequency acquisition is complete, this clock generator enters the sequential-search mode. The output signal of the counter comparator (Counter_Comp) is generated according to the phase relations among the last desired output clock (Out_Clk), the reference clock (Ref_Clk), and the postponed clock (Post_Clk). The two clocks realize the detection window by the DFFs, D and G, as shown in Fig. 7(b). The external divisor subtracts one to compare with the counted number in the counter. This produces the signal “Enable” to allow the DFFs, D and G, to detect the position of the last desired output clock. If the last desired output clock rises after this detection window, “Counter_Comp” is low and vice versa. This signal “Enable” is reset after the last desired output clock rises by the DFFs, B and C. In the sequential-search mode, the phase acquisition is achieved by detecting whether the last desired output clock

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(a)

Fig. 9. Digital-controlled delay cell.

Fig. 10. Linear Z -domain model for the proposed DLL-based clock generator.

(b)

rises within the detection window or not. The frequency acquisition is achieved by comparing the counted number in the counter with the external divisor. It realizes the digital phasefrequency detection. D. Digital-Controlled Delay Line The digital-controlled delay line is composed of three inverter-type delay cells with an 8-b controlled code. The digital-controlled delay cell is shown in Fig. 9 with a binaryweighted switched-capacitor array. The capacitive loads are increased when the code in the MSAR circuit becomes larger and vice versa. In Fig. 9, two kinds of connections are adopted for the switched capacitors. To prevent too large parasitic capacitances to limit the system speed, larger capacitances are connected to the output through switches to reduce parasitic capacitance. Smaller capacitances are connected to the output directly and the switches are connected to ground. Although this method may result in linear and monotonic problems, it is overcome by the careful design and layout. IV. PERFORMANCE ANALYSIS The linear model of the proposed all-digital DLL-based clock is the output phase, generator is shown in Fig. 10, where is the input phase, and D is the delay time of the digitalcontrolled delay line. The delay time in the digital-controlled delay line is given as

(c) Fig. 11. (a) Simulated delay time of the digital-controlled delay line under the input jitters with peak-to-peak amplitudes of 30 and 60 ps and frequencies of 2 and 20 MHz. The period of the input clock is 20 ns. (b) Simulated delay time of the digital-controlled delay line under the input jitter with the peak-to-peak amplitude of 60 ps and the frequency of 20 MHz. (c) Simulated delay time of the digital-controlled delay line with the detection window method under the input jitters with peak-to-peak amplitudes of 30 and 60 ps and frequencies of 2 and 20 MHz.

the total delay would be amplified by a factor of . Although this PFD works every two input cycles, the output of the PFD is still based on the comparison between the present input phase and the previous output phase as in [6]. Although the result is calculated every two input cycles, it does not violate how the input jitters affect the delay line variations and the long-term average phase error. The relation between the input and output phases can be expressed as

(1)

(2)

where is the external divisor and represents the adjusted delay step once the digital-controlled delay line is updated. When is the minimum adjusted delay the clock generator is locked, step . Since this delay line is connected as a ring oscillator,

Assume and this clock genmay be negative or poserator is locked. The polarity of itive alternatively due to the quantization errors. This situation , occurs only when the input phase deviation

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(a)

Fig. 12. Die photograph.

(b) Fig. 13. Measured transient response at 360 MHz.

caused by the input jitters, is small and the quantization errors and satisfy the of the delay line following inequality:

(3) is the period of the input clock. Then, the following where equation can be obtained: (4) According to (1) and (4), the delay time in the digital-controlled delay line is

(c) Fig. 14. (a) Input frequency is 30 MHz, and the external divisor is 2. (b) Input frequency is 30 MHz, and the external divisor is 15. (c) Input frequency is 4 MHz, and the external divisor is 14.

(5) Using (2) and (5), the input and output phases can be expressed as (6) Equation (6) implies that the input jitter and the quantization error will directly contribute to the output jitter. The smaller the external divisor and the higher the resolution of the digitalcontrolled delay line are, the smaller the output jitter and the

phase error are. Fig. 11(a)-(c) gives the simulated delay time of the digital-controlled delay line under the input jitters with peak-to-peak amplitudes of 30 and 60 ps and frequencies of 2 ns ; the and 20 MHz. The input clock is 50 MHz is 30 ps and is 2. minimum adjusted delay step If the peak-to-peak amplitude of the input jitter is larger than or , two the quantization errors, different cases may occur. When the jitter’s frequency is slow, is small enough the input phase deviation not to exceed the quantization errors. The condition of (3) is

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(a)

Fig. 16. Measured jitters at different output frequencies.

(b)

Hence, if the quantization error is small, even slight input jitters can cause multiple controlled code transitions, and therefore the jitters of the output clock become large. If the quantization error is large, the large static phase error would result in a large frequency offset of the output. The proposed detection window method allows small quantization error and prevents the multiple controlled code transitions from the small quantization errors. By using the detection window method, Fig. 11(c) gives the simulated delay time of the digital-controlled delay line with the same input conditions of Fig. 11(a) and (b). V. EXPERIMENTAL RESULTS

(c) Fig. 15. (a) Measured open-loop peak-peak jitter at 450 MHz. (b) Measured closed-loop peak-peak jitter at 450 MHz. (c) Measured jitter at 450 MHz when the detection window is disabled.

still held. Two controlled codes change alternatively as shown in Fig. 11(a). The simulated quantization errors are 40 and 80 ps. This means that this clock generator can track the low-frequency input jitters. However, when the jitter’s frequency is fast enough to violate (3), the multiple controlled codes may change instead of two codes. Fig. 11(b) gives the simulated delay time of the digitalcontrolled delay line under the input jitter with a peak-to-peak amplitude of 60 ps and frequency of 20 MHz. The quantization errors are 160, 40, and 80 ps, respectively. This means that the output clock cannot track the input clock immediately and its output jitter becomes large.

The proposed DLL-based clock generator has been fabricated in a 0.35- m CMOS process. Its die photograph is shown in 400 m. The clock Fig. 12 and the active area is 540 m multiplication ratio is from 2 to 15. The frequency ranges of the input and output clocks are 4 200 MHz and 60 450 MHz, respectively. Fig. 13 shows the measured transient response at 360 MHz. As “Start” goes high, the most significant bit B0 is set to one and others are set to zero. In the binary-search mode, the 8-b MSAR circuit takes 16 input clocks to lock. In the sequential-search mode, the MSAR circuit will track the environmental variations in a closed loop. Fig. 14(a) and (b) show the measured output clocks for the multiplication ratios of 2 and 15, respectively, at an input frequency of 30 MHz. Fig. 14(c) shows the measured output clock for the multiplication ratio of 14 at an input frequency of 4 MHz. A 4-b counter is used, and therefore the system can multiply the input clock from 2 to 15, which can be extended easily. Fig. 15 shows the measured peak-to-peak jitter of the output clock at 450 MHz. In Fig. 15(a), the peak-to-peak jitter is 33.3 ps when the MSAR circuit operates as a conventional SAR circuit. In Fig. 15(b), the peak-to-peak jitter is 37.8 ps when the MSAR circuit tracks the environmental variations in a closed loop. If the detection window is disabled, the measured peak-to-peak jitter in the closed loop increases to 127.8 ps, as shown in Fig. 15(c). Fig. 16 summarizes the measured jitters at different frequencies. The performance comparisons with the previous works are listed in Table I.

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TABLE I PERFORMANCE COMPARISONS

VI. CONCLUSION An all-digital DLL-based clock generator is presented in this paper. First, it succeeds the advantage of the conventional MDLL, the low jitter performance, but eliminates its initial minimal delay constraint and achieves better stability after being locked. Second, it could switch the clock frequency from low to high and program the multiplication ratios by the external divisor as can a PLL-based clock generator. Third, the modified SAR circuit not only achieves fast-locking, but also sustains the closed-loop characteristics to track the PVT variations. ACKNOWLEDGMENT The authors would like to thank National Chip Implementation Center (CIC), Taiwan, R.O.C., for fabricating this chip. REFERENCES [1] G. Chien and P. R. Gray, “A 900-MHz local oscillator using a DLLbased frequency multiplier technique for PCS applications,” IEEE J. Solid-State Circuits, vol. 35, no. 12, pp. 1996–1999, Dec. 2000. [2] C. Kim, I. C. Hwang, and S. M. Kang, “Low-power small-area 7.28-ps-jitter 1-GHz DLL-based clock generator,” in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, Feb. 2002, pp. 142–453. [3] C. C. Wang, Y. L. Tseng, H. C. She, and R. Hu, “A 1.2 GHz programmable DLL-based frequency multiplier for wireless applications,” IEEE Trans. Very Large-Scale Integr. (VLSI) Syst., vol. 12, no. 12, pp. 1404–1408, Dec. 2004. [4] R. Farjad-Rad, W. Dally, H. T. Ng, R. Senthinathan, M.-J. E. Lee, R. Rathi, and J. Poulton, “A low-power multiplying DLL for low-jitter multigigahertz clock generation in highly integrated digital chips,” IEEE J. Solid-State Circuits, vol. 37, no. 12, pp. 1804–1812, Dec. 2002. [5] C. S. Hwang, P. Chen, and H. W. Tsao, “A wide-range and fast-locking clock synthesizer IP based on delay-locked loop,” in Proc. Int. Symp. Circuits Syst., May 2004, vol. I, pp. 785–788.

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[6] M.-J. E. Lee, W. Dally, T. Greer, H. T. Ng, R. Farjad-Rad, J. Poulton, and R. Senthinathan, “Jitter transfer characteristics of delay-locked loops—Theories and design techniques,” IEEE J. Solid-State Circuits, vol. 38, no. 4, pp. 614–621, Apr. 2003. [7] G. Y. Wei, J. T. Stonick, D. Weinlader, J. Sonntag, and S. Searles, “A 500 MHz MP/DLL clock generator for a 5 Gb/s backplane transceiver in 0.25 um CMOS,” in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, Feb. 2003, pp. 464–465. [8] M. Combes, K. Dioury, and A. Greiner, “A portable clock multiplier generator using digital CMOS standard cells,” IEEE J. Solid-State Circuits, vol. 31, no. 7, pp. 958–965, Jul. 1996. [9] A. Rossi and G. Fucilli, “Nonredundant successive approximation register for A/D converters,” Electron. Lett., vol. 32, no. 12, pp. 1055–1057, Jun. 1996. [10] G.-K. Dehng, J.-W. Lin, and S.-I. Liu, “A fast-lock mixed-mode DLL using a 2-b SAR algorithm,” IEEE J. Solid-State Circuits, vol. 36, no. 10, pp. 1464–1471, Oct. 2001. [11] J. Lin et al., “A PVT-tolerant 0.18 MHz to 600 MHz self-calibrated digital PLL in 90 nm CMOS process,” in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, Feb. 2004, pp. 488–541. [12] T. D. Chiueh, J. B. Yang, and J. S. Wu, “Design and implementation of a low-voltage fast-switching mixed-signal-controlled frequency synthesizer,” IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process., vol. 48, no. 10, pp. 961–971, Oct. 2001. [13] R. B. Staszewski, D. Leipold, K. Muhammad, and P. T. Balsara, “Digitally controlled oscillator (DCO)-based architecture for RF frequency synthesis in a deep-submicrometer CMOS process,” IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process., vol. 50, no. 11, pp. 815–828, Nov. 2003.

Chuan-Kang Liang (S’06) received the B.S. and M.S. degrees from the Department of Electrical Engineering and Graduate Institute of Electronics Engineering, National Taiwan University (NTU), Taipei, Taiwan, R.O.C., in 2004 and 2006, respectively. She is currently working toward the Ph.D. degree at the University of California, Los Angeles. Her research interests include the architecture and system design of high-speed transceivers and RFICs for wireless communications.

LIANG et al.: ALL-DIGITAL FAST-LOCKING PROGRAMMABLE DLL-BASED CLOCK GENERATOR

Rong-Jyi Yang (S’03–M’06) was born in Taipei, Taiwan, R.O.C., in 1973. He received the B.S. degree in electrical engineering from National Central University, Jhongli, Taiwan, R.O.C., in 1998, and the M.S./Ph.D. degree from National Taiwan University, Taipei, Taiwan, R.O.C., in 2006. Since August 2006, he has been an Assistant Professor with the Department of Electrical Engineering, Chung Gung University, Tao-Yuan, Taiwan, R.O.C. His research interests include both analog and digital approaches of phase-locked loops, delay-locked loops, and high-speed CMOS data-communication circuits for multiple gigabit applications.

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Shen-Iuan Liu (S’88–M’93–SM’03) was born in Keelung, Taiwan, R.O.C., in 1965. He received the B.S. and Ph.D. degrees in electrical engineering from National Taiwan University (NTU), Taipei, Taiwan, R.O.C., in 1987 and 1991, respectively. From 1991 to 1993, he served as a second lieutenant in the Chinese Air Force. From 1991 to 1994, he was an Associate Professor with the Department of Electronic Engineering, National Taiwan Institute of Technology. He joined in the Department of Electrical Engineering, NTU, in 1994, and he has been a Professor since 1998. His research interests are in analog and digital integrated circuits and systems. Dr. Liu is a member of the Institute of Electrical, Information and Communication Engineers. He has served as a Chair for the IEEE Solid-State Circuits Society Taipei Chapter from 2004. He has served as a General Chair for the 15th VLSI Design/CAD symposium, Taiwan, 2004 and a Program Co-chair on the Fourth IEEE Asia-Pacific Conference on Advanced System Integrated Circuits, Japan, 2004. He was the recipient of the Engineering Paper Award from the Chinese Institute of Engineers in 2003, the Young Professor Teaching Award from MXIC Inc., the Research Achievement Award from NTU, and the Outstanding Research Award from National Science Council in 2004. He has served as a Technical Program Committee member for A-SSCC since 2005 and ISSCC since 2006, respectively. He was an Associate Editor of the IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: EXPRESS BRIEFS in 2006–2007. Since 2006, he has been the Associate Editor of the IEEE JOURNAL OF SOLID-STATE CIRCUITS and since 2008, an Associate Editor of IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS. He is a member of IEICE.