An Automated Methodology to Diagnose Geometric Defect in the EEPROM Cell 1
J.M. Portal
1&2
L.Forli
1
ICF/L2MP-UMR CNRS 6137 IMT - Technopôle de Château Gombert 13451 Marseille Cedex 20, France
[email protected] Abstract The objective of this paper is to present an Automated Geometric defect Diagnosis methodology for EEPROM cell (AGDE). This method focuses on speeding up the diagnosis process of geometric defect. It is based on a mathematical model generated with a “Design Of Simulation” (DOS) technique. The DOS technique takes as input, simulations results of a floating gate transistor with different given geometries and produces, as output, a polynomial equation of the threshold voltage in function of the cell’s geometric parameters. The diagnosis process is realized in comparing the measured threshold voltages of an EEPROM cell with the dynamically computed ones. From this comparison, the potentially defective geometric parameters are automatically extracted.
1. Introduction The evolution of the market of portable devices such as smart card or mobile communication media has a straight impact on the use of EEPROM. Indeed, EEPROM have become over the last few years’ very relevant choices for any application requiring non-volatile semiconductor memory. The core element of the EEPROM memory cell is a Floating Gate Transistor (FGT). The threshold voltage of a FGT can be shifted repetitively from a high to a low state corresponding to the two logical values of the memory cell. The VT of a FGT is shifted when the cell is programmed by a write or an erase operation. When a negative charge is stored on the floating gate node, the VT increases, the cell is then said erased. Respectively, when the charge on the floating gate node is positive, the VT decreases, the cell is then said written. In the EEPROM industry-standard “Flotox”, the charge transfer from the drain node to the floating gate node is due to Fowler-Nordheim tunneling [1]. This tunneling
1&2
H.Aziza
D.Née
2
ST-Microelectronics ZI de Rousset BP 2 F-13106 Rousset CEDEX,France
[email protected] mechanism is completely dependent of the geometry of the cell [2], inducing critical problems of process control. Any small variations of any geometric parameters among the cells in a memory array leads directly to a spread threshold voltage distribution, limiting the overall performance of the memory. Moreover, the sensibility of EEPROM memory to process variations has a straight impact on yield improvement. Indeed, it is extremely complex and time consuming to diagnose the roots of any threshold voltage failure. Knowing that, yield improvement is a key factor to determine the success of a fabrication unit, product specific as well as general speed up techniques for diagnosis are absolutely necessary. From these facts and knowing that memories offers specific properties of regularity, failure analysis methods were proposed. AFA in [3] from D.Y.Lepejian focuses on repeated structure and is linked to an IFA program CARAFE [4]. Other methods used to enhance yield are based on memory bitmap, as the ones proposed in [5] by J.Segal. Those methods have a general scope and so can be used successfully with Non Volatile Memory, but they do not address specific defect, such as the EEPROM cell geometric ones. The fundamental discussion of this paper is to show the efficiency of an Automated Geometric defect Diagnosis methodology for EEPROM cell (AGDE). This method is based on the comparison of measured threshold voltage values with mathematically generated ones. In order to get a polynomial threshold voltage model, a set of simulations is performed. So, first of all, section 2 gives an overview of the ELDO simulation [6] context, including a description of the floating gate transistor model used in the EEPROM memory netlist. The purpose of the section 3 is to detailed the automatic generation of a polynomial threshold voltage model. In this aim, a specific technique based on “Design Of Experiment - DOE” is used; here the experiments are a set of simulations, so the technique is defined as a “Design Of Simulation – DOS”. The section 4 is dedicated to the
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2
Paper 2.1 31
description of the different phases of our automated diagnosis method. In section 5, the validity of the method is illustrated through an example from production data. Finally, Section 6 gives some concluding remarks.
cells on the bit line. The EEPROM circuit is described as a netlist for the simulator ELDO [6], based on a F6SDP7.7µm² technology from ST-Microelectronic (Rousset–France).
2. Simulation context
CRD
CSA
Read Decoder
Sense Amplifier
To generate a polynomial model of EEPROM cell threshold voltages, simulations are first performed for different cell geometries. This section is devoted to the presentation of the simulation context. This context is defined by the different circuit elements surrounding the memory cell and by the description of the core element of the cell itself i.e. the Floating Gate Transistor (FGT). In order to be as close as possible of the product working conditions, the simulations are performed with all the circuit elements used to program and to read the memory cell. Figure 1 illustrates the different parts of the circuit netlist. This circuit can be divided in 4 different parts: - the high voltage VPP routing circuit, - the read decoder, - the sense amplifier, - the memory cell.
Tpp
Lpp
Tox
Ttun Ltun
Leff
Wpp
Weff
VPP Routing Logic BL
VPP
SD
WL
CRL
D CG
CG SG Memory Cell
Vout
FGT S
Figure 1 : Memory circuit block diagram The VPP routing logic allows to apply the high voltage on the nodes of the memory cell to perform the different program operations i.e. write and erase. This logic part is control by different signal called CRL. The read decoder selects a specific cell during read operation depending on the control signals CRD. The sense amplifier gives on its output VOUT the logical value of the addressed cell. The central part is the memory cell, composed of 2 select transistors SD and SG and of a FGT as core element of the memorization. A single cell is used because our method focuses on geometric defect of the FGT. A capacitance of 1pF is connected between the bit line BL and the ground, to simulate the capacitive charge introduced by the other Paper 2.1 32
Figure 2 : Cross section of a FGT with geometric parameters. A new model of FGT is developed based on a Mos Model 9 description [7]. This MM9 based FGT model is a compact charge sheet model written in HDLA [8]. This model takes into account static and dynamic behaviors. The approach used to develop this model is based on a charge neutrality formulation coupled with a MOS Model 9. In this approach, the charge neutrality, including the charge stored on the floating-gate, is applied to determine the floating gate potential from which all the variables can be calculated in the MM9 model formulation as well as in the Fowler-Nordheim tunnel current equation.
The structure of the FGT is depicted Figure 2, with all the geometric parameters taken into account in our model (length, thickness and width) with: - Leff, the effective length of the channel, - Ltun, the length of the tunnel oxide window, - Spp=Wpp.Lpp, the area of the inter-polysilicon oxide, - Ttun, the thickness of the tunnel oxide window, - Tpp, the thickness of the inter-polysilicon oxide, - Weff, the effective width of the channel, - Tox, the thickness of the oxide over the channel.
In our FGT model, the MM9 is the transistor that appears between the drain node, the source node and the floating gate node, with all the potential referenced to the bulk. In order to validate the MM9 based FGT model, a test structure has been used for measurements and simulations. The transistors of the test structure are simulated with MM9 parameters provided by ST Microelectronics (Rousset–France). The EEPROM specific geometric parameters are extracted with physical characterizations using scanning electron microscopy (SEM) and electrical characterizations. 6
Th resho ld v oltage (V )
5 4 3 2 1 0 -1 -2 -3 -4 13 ,8
14
14 ,2
14 ,4
14 ,6
14 ,8
15
15 ,2
15 ,4
15 ,6
Sign al p ro gr a m m i n g (V )
Figure 3 : Variation of the window programming simulation (___), measure () The Figure 3 gives the threshold voltages obtained with different programming voltages. The comparison between the simulated values, with nominal geometric data, and the measured ones shows the good accuracy of the MM9 based FGT model.
3. Threshold Voltage polynomial model Geometric defect diagnosis of an EEPROM cell implies to be able to link the different measured threshold voltages (VTerase, VTwrite and VTvirgin) to geometric parameters. To do so, any possible variations of all the 7 selected geometric parameters must be considered. Probability
-0.01
0.00
0.01
With those information, the map of simulations is build around 57 different FGT values of geometries. Therefore, 57 ELDO simulations of the circuit are automatically performed. From the result of these simulations, a multiregression algorithm extracts the polynomial model of each considered threshold voltage (VTerase, VTwrite and VTvirgin). This model allows to have a simple relation between the threshold voltage values and the geometric parameters. The threshold voltage equation (VT) is given in a general manner as follows: VT b0
Residual -0.02
It clearly appears that a classical approach based on changing one parameter at a time for all other possible values of parameter is intractable in number of experiment to be performed. For example, considering 100 possible values for each parameter, such a method would lead to perform 1007 simulations to build a database. To pass over this limitation, a technique based on “Design Of Experiment - DOE” is used. Our experiments are a set of simulations, thus this technique is here called “Design Of Simulation - DOS ”. This technique allows to have a complete knowledge of the selected answers (threshold voltages) in the domain of variation of the 7 geometric parameters from a limited number of simulations. This domain of variation is defined as a sphere of knowledge. More concretely, a Doehlert matrix [9] is selected to define all the geometric configurations that have to be simulated. The selected answers are generated from a Surface Response analysis. In this approach each geometric parameter is associated to a factor, thus 7 factors are necessary. The levels chosen for this factors, according to the Doehlert matrix, are given as follow: - Leff is affected to factor X3 with 7 levels, - Ltun is affected to factor X5 with 7 levels, - Spp is affected to factor X7 with 3 levels, - Ttun is affected to factor X2 with 7 levels, - Tpp is affected to factor X1 with 5 levels, - Weff is affected to factor X4 with 7 levels, - Tox is affected to factor X6 with 7 levels.
0.02
Figure 4 : Normal Plot of the VTvirgin
¦i biXi ¦i bii XiXi ¦ij bij XiX j
The confidence on the three VT equations is given by the study of the residual, i.e. the difference between the values obtained from the equations and the ones obtained from the simulations. The maximal differences are 15mV for a virgin cell, 170mV for an erased cell and 130mV for a written cell, it is important to note that this values are obtained with corners cases at the limit of the sphere of knowledge. They represent less than respectively 2%, 5% and 8% of error compare to the nominal values of threshold voltage. These results are confirmed by rectilinear normal plot, the Figure 4 gives as an example of Paper 2.1 33
the one of the virgin cell. The Figure 5 summarizes the different steps of the automated model generation technique, which represents the pre-processing phase of our diagnosis methodology. Geometric parameters domains
Simulations Map & Results
calculation module. The dynamic model calculation module generates a list of all the possible cell geometry that meet all the three targeted threshold voltages with a given variation window, as illustrated Figure 7. The windows variations for the targeted threshold voltages as well as the step of computation for the different geometric parameters can be set in line in function of the wanted accuracy. DUT Measured Threshold Voltages
Doehlert Matrix Dynamic Model Calculation
Threshold Volatge Models (Vtvirgin, Vterase,Vtwrite)
Figure 5 : Block diagram of the model generation Finally, the numerous advantages offered by the polynomial model are listed below: - A simple polynomial expression allows fast computation time, consequently dynamic signature computation is preferred, instead of searching in large database. - Only 57 simulations are necessary, allowing a short generation time. This property can be used to automatically fast calibrate the model to switch from one technology to another or from one production unit to another. - The precision of the threshold voltage values as well as the one of the geometric parameters can be set in line and that compare to the one adjust once to generate database.
4. Diagnosis Methodology Knowing that any small variations of the cell geometry may change critically its different threshold voltages, leading to spread threshold voltage distribution. It clearly appears that the process steps impacting on the memory cell geometry are a key factor to control EEPROM performance and yield. This last point shows the necessity to use speed up technique to diagnose the roots of the VTvirgin, VTerase and VTwrite failures in term of geometric parameters variations. Our methodology AGDE is developed in this aim. Figure 6 outlines the different steps of the automated geometric defect extraction. The diagnosis process starts with the measurement of the different threshold voltages of a DUT. These threshold voltages are defined as Target Threshold Voltages. They are the input data to be treated by the dynamic model Paper 2.1 34
Post-processing = Defect statistics generation
Figure 6 : Block diagram of the diagnosis methodology Vterase = Etarget r deltaE Vtwrite = Wtarget r deltaW Vtvirgin = Vtarget r deltaV
Dynamic Model Calculation
G1: Tpp1 ,ttun1 ,leff1 ,weff1 ,ltun1 ,tox1 ,spp1 G2: Tpp2 ,ttun2 ,leff2 ,weff2 ,ltun2 ,tox2 ,spp2 G3: Tpp3 ,ttun3 ,leff3 ,weff3 ,ltun3 ,tox3 ,spp3 G4: Tpp4 ,ttun4 ,leff4 ,weff4 ,ltun4 ,tox4 ,spp4 •••
Figure 7 : Candidate geometries generation The last step of the method is a post-processing phase. During this last phase, a geometric defect statistic is generated in order to point out the most potential defective parameter. This post-processing phase generated two different informations. The first one, is a rating in percentage of the most potential defective parameter to the less one. Figure 8 presents an example of this postprocessing output standard. The second one is a statistic distribution of each geometric parameter, as illustrated Figure 9 for the oxide tunnel window thickness “ttun”. This second information leads to a better knowledge of the potential roots of defect for each parameter. Indeed, the distribution shows if a process failure has induced an over-
dimensioned or under-dimensioned parameter. The accepted variation window around the nominal value of each geometric parameter can be set in line before the post-processing defect statistic generation, depending on the accepted process variation. All those information’s are linked to all process steps involved in the defective parameters fabrication in order to diagnose the root of the failure. From a working time point of view, the sum of computation and post-processing times is included between a few seconds and a few minutes, in order of magnitude, depending on: - the computation step used for the geometric parameters, - the variations window of the targeted threshold voltages, - the variations window for each geometric parameter.
Pttun(%): Pspp(%): Ptpp(%): Pweff(%): Pltun(%): Pleff(%): Ptox(%):
98.90 65.06 62.36 57.87 46.85 42.26 36.75
is identified as the most potentially defective one. The second output gives the distributions of every parameters. In the Figure 12, for space reason, only the distributions of two potentially most defective parameters are given. From the distribution given Figure 12, the parameter “Weff” appears to be statistically under-dimensioned. From all this output, the root of the threshold voltage failure seems to be related to any process steps belonging to the “Weff” determination. Id
Vg Id
Figure 8 : Example of post-processing result Dttun(%) 25
20
15
10
5
Variation window
0
ttun ref
Values in Å
Figure 9 : Distribution Dttun (%) of ttun values
5. Example of application The validity of the method is demonstrated through a fabrication data example from ST-Microelectronics (Rousset – France). The targeted threshold voltages are extracted from static curve of the drain current in function of the control gate potential. The Figure 10 illustrates the threshold voltage extraction. The targeted threshold voltages are then taken as inputs in the Automated Geometric defect Diagnosis methodology for EEPROM cell (AGDE) tool. The generated outputs are first the standard output given Figure 11. From this first output, the geometric parameter “Weff”
Vg
Figure 10: Targeted threshold voltage extraction Using cross-section and TEM analysis, the physical root of failure is validated as belonging to the “Weff” parameter as illustrated Figure 13. A too large growing of the field oxide had for consequence to reduce the effective width of the FGT. This example shows how our Automated Geometric defect Diagnosis methodology for EEPROM cell (AGDE) can clearly speed up the diagnosis process of threshold voltage failure related to geometric defect in the EEPROM cell.
Paper 2.1 35
Pweff(%): Pltun(%): Ptpp(%): Pspp(%): Pleff(%): Pttun(%): Ptox(%):
information on the potential defective parameters and on their statistic distributions to enhance the diagnosis of the defects root through the processes steps. The working steps of the method are described with a production data example of defect diagnosis. It is important to note, that in the case of EEPROM memories, this method is an essential complement of usual failure analysis method such as bitmapping.
100 31.98 30.23 29.65 25.58 0 0
Figure 11 : Identification of Weff as potentially most defective
Field Oxide
Dweff (%) 70 60
Short Weff
50 40 30 20
Variation window
10
7. Reference
0
weffref
Values in µm Dltun (%) 35 30 25 20 15 10 5
Variation window
0
ltunref
Values in µm
Figure 12 : Distribution of Weff and Ltun values
6. Conclusion In this paper, an Automated Geometric defect Diagnosis methodology for EEPROM cell (AGDE) is presented. Knowing, that EEPROM performances as well as yield are strongly dependant of the geometry of the cell, this method is very useful to speed up the geometric defect diagnosis. The pre-processing phase of the method is based on a threshold voltage polynomial model that offers in line setting capabilities. The post-processing phase gives Paper 2.1 36
Figure 13 : Short Weff defect due to field oxide growing.
[1] M. Lenzlinger et al., “Fowler-Nordheim tunneling into thermally grown SiO2”, Journal of Applied Physics, vol. 40 (1969) 278. >2@ P.Pavan et al., “Flash Memory Cells – An Overview”, Proc. IEEE, vol. 85, n° 8, pp.1248-1271, August 1997. [3] D.Lepejian et al., ”An Automated Failure Analysis (AFA) Methodology for Repeated Structures”, Proc. 12th IEEE VLSI Test Symp., IEEE Computer Society Press, Los Alamitos, Calif, pp.319-324., 1994. [4] A.Jee et al., “Carafe: A Software Tool for Failure Analysis”, Proc. Of Int’l Symp. On Testing and Failure Analysis, pp.143149, 1993. [5] J.Segal et al., “Using Electrical Bitmap Results from Embedded Memory to Enhance Yield”, IEEE Design&Test of Computer, Vol.18, N°3, pp.28-39, May-June 2001. [6] “ELDO User’s Manual”, Mentor Graphics Corp., 1998. [7] R. Velghe, D. Klaassen and F. Klaassen, “MOS Model 9”, Unclassified Report NL-UR 003/94, Philips Electronics N.V. (1994). [8] J.M.Portal et al., “Floating-Gate EEPROM Cell Model Based on MOS Model 9”, IEEE Int’l Symp. on Circuits and Systems, to appear, 2002 [9] D.H. Doehlert, ”Uniform Shell Designs”, Applied Statistics, 19,pp.231-239.(1978). Acknowledgement: This work has been partially supported
by the French Ministry of Economy Finance and Industry through contract STSI. The authors would like to thanks Michèle Sergent from LPRAI for her advices on DOE techniques.
