An Efficient Power over Ethernet (PoE) Interface with ... - IEEE Xplore

This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TIE.2017.2739693, IEEE Transactions on Industrial Electronics

IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS

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An Efficient Power over Ethernet (PoE) Interface with Current-Balancing and Hot-Swapping Control Zhiming Xiao, Member, IEEE

Abstract—This paper presents an energy efficient Power over Ethernet (PoE) interface for applications that require higher power delivery than that of IEEE 802.3af and 802.3at standards allow. The proposed architecture increases the power delivered to the Powered-Device (PD) by utilizing all four pairs of the CAT5 cable. Maximum power is guaranteed by a current-balancing control block which equalizes the currents in the CAT5 cable. The current-balancing control is implemented in an efficient way of regulating the pass PMOSFETs in the diode bridge stage. The proposed interface also includes a hot-swapping control block that protects the devices in the power conduction path by limiting both the maximum load current and the maximum voltage ramping rate. The voltage and current-limiting functions are controlled by two separated regulation loops. To reduce the power loss, a single pass NMOSFET is inserted in the ground current path and is shared by both regulation loops. The experimental result of the assembled prototype showed balanced currents among all four pairs in the CAT5 cable. In cases of hot-plugging, the proposed prototype exhibited both well-controlled inrush current and limited voltage-ramping rate under various load capacitance conditions. Index Terms—Power over Ethernet, PoE, Current Sharing, Current-Balancing, Hot-Swapping, Hot-Plugging.

I. INTRODUCTION

P

ower Over Ethernet (PoE) has consistently been a popular technique deployed in high volume applications in industry and our daily life [1]-[4] Due to its low installation cost and the compatibility to the existing networks, PoE is among the best compelling options for supplying modest amounts of power to Internet protocol (IP) devices. However, the power delivered to the Powered Device (PD) is constrained by the existing PoE standards [5] of IEEE 802.3af with 12.95 Watts power limit and IEEE 802.3at with 25.5 Watts power limit, which confine its penetration into wider applications. Some PD examples that are powered through the CAT5 cable are shown in Fig. 1. As more and more complicated and powerful systems show their potential utilization in PoE systems, achieving higher power delivery Manuscript received April 06, 2017; revised July 02, 2017; accepted July 23, 2017. Z. Xiao was with the Department of Electrical Engineering, University of Florida, Gainesville, FL, 32611. He is now with Analog Devices, Inc., Colorado Springs, CO 80920 USA.

Fig. 1. Example PoE applications

in a PoE system continues to be demanded. To achieve higher power delivery through the PoE interface, non-IEEE-standard implementations have been published, such as UPOE by CISCO [6], LTPOE++ by Linear Technology [7], and the 802.3bt (under development) by IEEE [8]. Among those potential implementations, utilizing all four pairs of the CAT5 cable instead of two for doubling the power availability is a common and attractive approach, which transmits power through both the data transmission pair and the spare pair. Although the maximum achievable power is doubled by using all four pairs, the mismatches between the two power conduction paths in a CAT5 cable need be addressed [9], otherwise the maximum available power will be derated, or the current may flow reversely from one pair to the other. The simplest method for balancing the current is the voltage-droop way [10] [11], which can be used on Power Source Equipment (PSE) side design at the expenses of sacrificed voltage accuracy. The design in [12] equalize the current in PoE cable by adding two additional control chips and the final solution turns out to be complicated and costly. Another PoE design in [13] adds an extra loop to balance the current, which has its loop-stability hard to achieve under a varying load condition. This paper proposed a current-sharing strategy that balances the two power conduction paths in the CAT5 cable by re-using the active PMOSFETs in the diode bridge stage for current regulation. The proposed architecture shows a simpler and more efficient way of current control compared with the methods that

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Fig. 2. The block diagram of the proposed PD interface

need extra pass device [10] [12] or additional control loop [13]. Another concern during PoE design is the hot-swapping issue [14] [15] happens when either the PD or the PSE is hot-plugged to the system [16]. In the event of hot-plugging, potential damages may happen due to the inrush current or the fast-ramping supply voltage [17]. The proposed architecture includes a hotswapping control block [18] that protects the system from overvoltage or over-current stress by two separate regulation loops. A single pass NMOSFET is inserted in the ground path with its gate controlled by both regulation loops for energy efficiency. II. THE PROPOSED PD INTERFACE ARCHITECTURE

The block diagram of the proposed PD interface is shown in Fig. 2 which consists of a RJ45 header attached to two transformers, an active diode-bridge stage, a signature and classification block, a current-balancing control block, and a hot-swapping control block. For the simplicity of description, the power path through the TX and RX pairs is called channel one (CH1), while the other path through the spare pairs is called channel two (CH2). The detailed schematic of the diode-bridge block is shown in Fig. 3(b), which uses active MOSFETs in place of the diodes [13] in order for less power loss. The inherent body diodes (shown by the dashed lines in Fig. 2) of those active MOSFETs are placed with the same direction as a conventional diode bridge [19] so initial startup is guaranteed. The gate voltages of the PMOSFETs are under regulation and their channel resistance are tunable by the current-balancing block. Therefore, the active PMOSFETs in the diode bridge block are modeled by adjustable resistors and body diodes in parallel in Fig. 2. The biasing and voltage monitoring block provides both a regulated supply and a current reference. This block also monitors the PSE output voltage to identify the modes [20] of operation, such as PD-detection, power-level-classification, or PDoperation. The signature and classification functions are built in accordance with the IEEE 802.3at standard [5] and will not be presented in this paper. The biasing block detects the power supply polarities in both channels, which is an essential information required by the current-balancing block.

Both CH1 and CH2 in the CAT5 cable are capable of delivering a power limit of 25.5 Watts according to the 802.3at standard, therefore the maximum available power will be doubled if both channels are utilized for power delivery. However, if there is mismatch between those two channels in terms of cable resistance, pass device on-resistance, or the transformer parasitic resistance, the maximum power available at PD side will be derated [12]. Even seriously, power may be reversely conducted from one pair to the other if the cable resistance is small enough. Therefore, the current-balancing block is introduced to compensate those non-idealities by adjusting the channel resistance of the pass PMOSFETs in the diode bridge stage. The ground current path for the PD device is isolated by a NMOSFET (MN0) shown in Fig. 2 which has its gate controlled by the hot-swapping control block. To protect the PSE from over current damages [21], the current drawn by PD is sensed and limited by regulating the gate-source voltage (VGS) of MN0. When a PD is connected to the PoE system, the voltage ramping rate on the PD supply is confined to a safety level by controlling the VGS of MN0 as well. Depending on the size of the decoupling capacitor (CPD) on the supply of the PD, either the load current or the supply voltage limiting function is enabled for protection, as will be described in more detail in subsection III-C. III. CIRCUIT DESCRIPTION A. The Front End of the PD Interface The front end of the proposed PD interface is shown in Fig. 3, which consists of a RJ45 header, two transformers, two active diode bridges, and a current biasing block. The RJ45 header terminates the CAT5 cable and delivers power through two channels. In channel one (CH1) where the network data is also transmitted, the power flows as the common mode voltage, so two six-terminal transformers are used to split the differential data from the DC power voltage. In channel two (CH2), only power is transmitted in the spare pairs which can therefore be directly fed into the diode bridge stage. Since the PoE interface must handle power received in both polarities from CH1 and CH2, the input diode bridges are necessary for both channels. The schematic of the biasing and the active-bridge control circuit is shown in Fig. 3(a). A Zener diode (DZ1) with a break




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(b) Fig. 3. The schematic of the front end of the PD interface. (a) Biasing and voltage monitor circuit. (b) The active diode bridge stage.

down voltage of ~ 5.6 V provides a stable reference voltage. A pass NMOSFET (MN9) with its gate tied to the Zener reference generates a buffered voltage of ~5V (VDD5V) that serves as the supply for the rest of the control system. A reference current generator [22] comprised of MN6, MN7 and R1 provides a bias reference (VBIASN) for other blocks. Source degeneration resistors (R3A-3D, R6A,6B, R5A,5B) are used to determine the ratios among the current mirrors for better matching and less sensitivity to thermal gradient on board compared with the one without source degeneration resistors. In order not to affect the function of the 25 kΩ signature-resistor for PD detection [5], the resistive loads on the supply (R2, R4, and R14) are all sized much higher than 25 kΩ. Likewise, in order not to affect the classification current in the range of tens of mA which defines the power limit of the PD [5], the current loads on the supply in the interface are all limited to sub-mA range. As mentioned in section II, the conventional diode bridge rectifier is replaced by active MOSFETs (pass FETs) that have their body diodes (shown as the dashed lines) in the same direction as the diodes in a conventional diode bridge, as shown in Fig. 3(b). Once the pass FETs are turned on to short the voltage drop of their body diodes, their power loss is reduced and the efficiency is improved [13]. Only the PMOS on the high voltage side and the NMOS on the low voltage side should be turned

on, so the polarity sensing circuit (shown in the left bottom corner) is required to choose the right pass devices. For instance, if VTX_COM and VSPARE+ provide positive supplies while VRX_COM and VSPARE- are negative supplies, MP1, MP3, MN2, and MN4 are turned on while all other pass devices and their body diodes are in off state. During startup or when the supply voltage is low, the default or the initial state of those pass FETs remain off by the resistors (RP1-RP4 and RN1-RN4) tied from their respective gate to source. The selected pass NMOS are turned on by sourcing current into their gates, while the selected pass PMOS are turned on by sinking current from their gates. The bias current flowing in or out of those gates are generated by the biasing block in Fig. 3(a), so the VGS of those pass devices are set as ⁄ ∙ (1a) _ _ (1b) ⁄ ∙ _ _ , ∙ Where _ and represent the gate-source volt_ age of the pass NMOS and the pass PMOS, respectively. Both and have a value of 3.5 MΩ as shown in Fig. 3(b). term is the regulated current from the current-balThe , ancing block. The voltage of (1a) and the first term of (1b) are high enough to turn the pass device on fully and is in ratio with the gate-source voltage of MN6. Therefore, the turn on threshold




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(b) Fig. 4. The current-balancing structure. (a) The simplified regulation loop. (b) The schematic of the transconductance stage (GM0).

of the pass device will track the one of MN6 and thus is not sensitive to temperature movement. The second term of (1b) is the output of the current-balancing block which is generated to adjust the of the PMOS pass devices for current equalization in the two power channels, as will be described in detail in subsection III-B. Even set by the resistor ratios, the value may still exceeds the FETs ABSMAX ratings due of _ to noise coupling or ESD spikes [23], so Zener diodes (DZ1-4) with 10 V reverse clamping voltage are placed between the gate-source terminals for protection. To achieve enough attenuation of the noise that is coupled from the TX/RX signals to the biasing circuit, attentions are paid while choosing the transformers (T1,2) and the Zener diode (DZ1). First, the transformers chosen [24] in this design have high differential to common mode rejection which helps reject the TX/RX signal coupled to the VDD supply. Second, the Zener diode chosen has a narrow clamp-voltage range which further attenuate the VDD noise coupled to the local supply of VDD5V. B. Current-Balancing Control In the proposed PoE system, the current imbalance between the two power channels can be resulted from the mismatch of the cable, the variation of the pass devices, and the voltage tolerance at the PSE output, etc. The maximum available power will be derated due to those mismatches and, even worse, current may flow reversely from one channel to the other if the cable resistance is small enough. According to the IEEE standard for PoE [5], the tolerance of the cable resistance is ±3%, the maximum cable length is 100 meters, and the current limit of each channel is ~0.6 A. Therefore, the maximum cable resistance can be calculated to be 12.5 Ω for a standard CAT5 type and the voltage mismatch due to the cable variations can be as high as ±225 mV at the input of diode bridge stage. As for

the power MOSFETs, the channel on-resistance may vary from several mΩ to hundreds of mΩ which can cause tens of mV of VDS mismatch. Assuming the voltage tolerance at the PSE output is ±100 mV or ±0.2%, the overall offset voltage will be as high as ±0.4 V with all errors adds together. The proposed ar(the body dichitecture therefore has a tuning range of ode drop) of around of ±0.7 V to correct the mismatches in the two channels. As mentioned in the previous section, the voltage polarities of both channels are random, so only one of the four pass PMOSFETs (MP1-4) is chosen for current-balancing regulation. A simplified block diagram is shown in Fig. 4(a) to help illustrate the current-balancing loop. Assuming VTX_COM is the positive supply and the mismatch in the two channels causes the input voltage of the diode bridge stage in CH1 to be higher. Without any current-balancing control, the current flows in CH1 will be higher than CH2. Therefore, the system chooses regulated to a value so that the currents in MP1 to have its both channels are equal. In the meantime, the pass device MP3 in CH2 is turned on fully and operates in deep triode region to drop. The remaining two pass devices (MP2 minimize its and MP4) are kept off due to their reverse input polarity. As shown in Fig. 4(a), the current difference (∆ ) in the two channels is sensed by RSNS1 and RSNS2, which yield a differential voltage to be further gained by a transconductance stage (GM0) with detailed schematic shown in Fig. 4(b). The differential current ∆ , between Q3 ( ) and Q4 ( ) at the input stage of GM0 can be calculated as ∆ , ∆ ∙ (2) , ⁄ , The converted differential current is mirrored and then is subtracted from each other on nets VN1 and VN2. Therefore, the current in MP7A or MP8A may increase or decrease, depending on




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the polarity of ∆ . As for the example in Fig. 4(a) where mismatch causes ICH1 to be higher than ICH2, the net current flowing through MP8A and MP7A will be increased and decreased, respectively. The sensed currents in MP7A and MP8A are mirrored with a ratio of 5 and then are fed into the ‘VBN1’ and ‘VBN2’ nets in Fig. 3(a), respectively. As a result, the GM0 stage outputs a current flowing into RP1 to decrease the gate-source voltage of MP1 , as illustrated in Fig. 4(a). The decreased gateby ∆ _ source voltage leads to an increased voltage drop in CH1 which makes the currents in the two channels to shift towards equilibrium. The small signal relationship between the gate-source voltage and the drain-source voltage of MP1 is as below: ∆

_

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_

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∙

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where _ and are the transconductance due to _ gate-source voltage and body-source voltage, respectively. The and _ refer to the inverse of the chanvalues of _ nel resistance and body diode resistance, respectively. MP1 may either work in triode or in saturation trigon, depending on the required drop !∆ _ " for balancing. While MP1 is under regulation, its body diode is shorted by the channel resistor, so term is much smaller compared with other terms. the _ in (3) generates a current shift of ∆ # beThe resulted ∆ _ tween the two channels as below to counteract the original current mismatch, 2∙% _ (4) ∆ # &'

&'

By incorporating (2), (3) and (4), the overall loop gain can be expressed as: ∆ # 10 ∙ ∙ , _ (5) () ∙ ! &' " ∆ ∙ , / &' , _ -._ ⁄, _ the second factor _ / has non-linear -._ relationship with drain-source or gate-source voltages, but its value can be extracted from the datasheet [25] and is in the range of 0.15 to 0.5. The value of () depends on the resistance and transconductance ratios and thus is not sensitive to temperature shift by first order approximation. The loop is compensated for stability by four capacitors CCP1-CCP4 that serve as the dominant pole in the frequency response. Depending on the

Fig. 6. The simulated stability results for the current-balancing loop, the current-limiting loop, and the slew-rate limiting loop.

polarity of ∆ , only one of the four pass PMOS is in regulation for current-balancing, so only one of CCP1-CCP4 is in charge of frequency compensation. The simulated stability waveform for the current-balancing loop in Fig. 6 is the result under the worst condition of 0.4 V offset between the two channels and a channel resistance ( &' , ) of ~0.5 Ω in both channels. When the loop is closed, the current mismatch can be calculated as !∆ 4 0.5∆ &' ∙ ) ∆ "⁄ &' , (6) ∆ &01.23 1 () where ∆ 4 refers to the PSE output voltage difference between the two channels, ∆ &' is the cable resistance difference, represents the pass devices drain-to-source voltage and ∆ drop difference. Therefore, the current-balancing regulation loop helps attenuate the current mismatch due to those non-idealities by a factor of !1 () ". The loop gain in (5) depends on the cable resistance (RCH1 and RCH2) which is variable in different applications, so , can be adjusted accordingly to acquire a required loop gain. Higher loop gain helps achieve smaller closed-loop current mismatch between the two channels but at the expenses of larger compensation capacitors (CCP1-CCP4) needed and a slower startup speed. The power loss in the diode bridge is related to the mismatch between the two channels. If the two channels are perfectly matched, the selected pass PMOSs are turned on fully and operate in deep triode region, therefore the loss is minimized. However, in practical conditions, the of the PMOS is adjusted by the current-balancing block to counteract the mismatch in the two channels. As a result, the power loss in the channels will be increased due to increased . The larger mismatch or offset in the two channels, the higher of the PMOS will be regulated to, and thus higher loss will be resulted. The of the pass PMOS is clamped by its body diode, maximum therefore the maximum power consumption of the pass PMOS is also limited. Moreover, the active PMOS chosen [25] has good thermal conductive footprint for heat sinking, so the




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PMOS is self-protected under regulation. Assuming all mismatch sources are referred to the input of the diode bridge stage, the regulated channel resistance and the loss of the pass PMOS can be calculated based on the parameters in Fig. 3 and Fig. 4(b). The calculated results as a function of the load current are plotted in Fig. 5. The four curves represent the offset (mismatch) voltages of 50mV, 100mV, 150mV and 200mV at the input of diode bridge stage. The four points along the load current (x-axis) are chosen to be the four maximum power ratings of the IEEE802.3at classes. As the load current increases, the RDSON of the pass PMOS is regulated to the required resistance to balance the currents between the two channels. The results also show that the power loss of the pass PMOS increases as either the load current or the channel mismatches increases. C. Hot-Swapping Control When either the PSE or the PD is hot-plugged to the PoE system, potential damage may happen due to over-current stress in the power conduction path or due to the fast ramping voltage stress on the PD supply. The tense of stress is related to the size of the decoupling capacitor (CPD) on the PD supply. When a PD with a charge-depleted CPD is connected to the PoE interface, maximum current is drawn from PSE to charge CPD. Therefore, all components in the power conducting path may suffer over current and over heat damages if CPD is too large. On the other hand, too small CPD size may cause failures due to fast ramping of the PD supply voltage (VLOAD). The fast ramping VLOAD may result in unexpected current shoot-through or over-voltage stresses, especially in the structure where the regulated rail is much lower than the VLOAD (>42V). The proposed structure is capable of protecting both stress cases by utilizing the control circuit shown in Fig. 7. The left shaded areas in the figure limits the maximum current drawn from the PSE, while shaded area in the middle controls the maximum ramping rate on VLOAD. Each shaded area has its own regulation loop and control mechanism. However, both loops merge to a common control net of VC_LIM at the gate of the pass device MN0, which isolates the current path from VSS to VGND. Therefore, by controlling the VGS of MN0, both the maximum current flowing to PD and the maximum VLOAD ramping rate can be limited.

When is below the 42V threshold for PD operation [5], the control signal VDD_GT_42V is low and the gate of MN0 is pulled low by R0, so MN0 remains off and no current flows into is in valid operating range (> 42V PD. After startup and and < 57V), the gate of MN0 is pulled high by MP10 to VDD5V, so MN0 is fully on and operates in deep triode region for the lowest on-resistance and voltage drop. In the event of hot-plugging, one of the two regulation loops will be active and control the gate of MN0, depending on the CPD size. The threshold of the 7 value that the two loops switch over between each other is 7

_8'

=2

)9

⁄

∙ 7:

9

(7)

where )9 is the maximum current set by the current-limiting is the bias current flowing through MN23 and is loop. The 9 set by the reference generator circuit in Fig. 3(a). If 7 is less than 7 _8' , the slew-rate limiting loop controls the MN0 gate, so VLOAD ramps up at a constant rate after hot-plugging happens. If 7 is larger than 7 _8' , after the PD is hot plugged to the interface, only the current-limiting loop is active and controls the MN0 gate, so 7 is charged by a constant current of )9 . In the current-limiting loop, the current drawn from PSE is sensed by RSNS3, which creates a voltage drop that is further amplified by a common base differential pair of Q5A and Q5B. Following the amplification stage, two more stages by MP10 and MN0 close the current-limiting loop with negative feedback. The loop gain can be calculated as, ()9 =

)9

∙

_)9

∙

;

∙
7 _8' , the output charging current is limited to a fixed value of )9 , and the voltage across CRAMP ramps at rate slower than the result of (11). In this case, MN15 remains off, and the slew-rate limiting loop is inactive and has no control over the gate of MN0. As for the case that 7 < 7 _8' , the slew-rate limiting loop is in charge of MN15 gate, and the CPD charging current of )9 _ : calculated based on (11) will be less than )9 . Therefore, Q5A remains off and the current-limiting loop is inactive. Since both loops merge to a common high impedance node of VC_LIM, those two loops are compensated for stability by the same capacitor of CC0 at this node. Both the current-limiting loop and the slew-rate limiting loop are checked for stability with the results shown in Fig. 6. The current-limiting loop is simulated under the worst condition of = 42 which is close to the fully-charged voltage. The ) slew-rate limiting loop is simulated under the worst condition of 7 = 7 _8' = 50 μF. Both the peak output current ! )9 " in equation (9) and the " in equation (11) are proportional to maximum slew-rate !A the bias currents of 9 ;, , generated in Fig. 3. Therefore, will decrease as the temperature increases, both )9 and A A

=

which helps alleviate the stringent safety requirement during hot-plugging at high temperatures. According to (7) (9), and (11), the PD current and the supply slew-rate as a function of the load capacitance can be calculated and plotted in Fig. 8 based on the parameters in Fig. 3 and Fig. 7. If the load capacitance is higher or lower than 50 µF (the value of 7 _8' ), the output is protected by limited current or by limited slew-rate during hot plugging, respectively. D. Trimming The current-balancing function and the current-limiting function described in above subsections are under ideal conditions. However, in practical cases where variations and mismatches are unavoidable, the system must be either capable of tolerating those variations or being able to cancel those errors. The proposed architecture incorporates trimming circuits to reduce the variations effects from the current-balancing and the currentlimiting circuit. As shown in Fig. 4(b), two pull down current paths of IPD1 and IPD2 are placed on nets VN1 and VN2, respectively, to counteract variations from RSNS1,2, RG2,3,4, Q3,4, and several current mirrors. The two pulled down trimming currents are adjustable by tuning the resistors of RTM1 and RTM2. The nets VN1 and VN2 are chosen because they are both low impedance nodes by diode-connected MP7A and MP8A, respectively. Since the two current paths of IPD1 and IPD2 are relative high impedance, the frequency response of the original current-balancing loop won’t be much affected by the trimming circuit. Trimming is implemented by adjusting RTM1 and RTM2 values while shorting VSNS1 and VSNS2 together to 50V. RTM1 is tuned until the current flowing through RBS1 is 1µA, and RTM2 is trimmed until the current flowing through RBS2 is 1µA. The value of 1µA is chosen for enough error correction range. The current-limiting circuit in Fig. 7 can be trimmed as well to yield an accurate maximum PD current of )9 . Known from (9), the current limit can be trimmed by either tuning )9 or adjusting 9 . However, the current flowing through Q5A and Q5B needs to be adjusted together for good matching, so )9 is chosen for trimming. By forcing 45V across VDD and VGND while forcing 42V across VLOAD and VSS, maximum current will flow into to the 42V voltage source and the current-limiting loop is active. The value of )9 is then tuned until the current flow into the 42V voltage source reaches the required JKL value. The values of 45V and 42V are chosen because they result a 3V voltage drop across the VDS of MN0, which therefore operates in active region but is not over-heated. Although the proposed trimming circuit helps counteract the transistor variations and mismatches, the proposed structure still shows tight margin regarding the variations from discrete components and the temperature gradients on board. On the other hand, the bias current in transistors of the proposed interface is small, because the resistors utilized in this design should be large enough so as not to affect the signature and classification functions during PD detection [5]. As a result, to be realized in practical applications, the proposed architecture must choose integrated circuit (IC) implementations for less variations and better matching with even lower cost and area.




8

(a) Fig. 9. Assembled prototype of the proposed PD interface. TABLE I COMPONENT PARAMETERS Component DZ1 M N9 M N6, 7, 8,14, 17, 18, 19, 20

M N5, 10, 11, 12, 15, 21, 22, 23

M P5, 6, 7, 8, 9, 12 15 M P16,17, 18 T 1,2 M P1,2,3,4 M N1,2,3,4

Part number

Parameter

NXP PLVA656A ROHM SEMI INFINEON BSS214NW Fairchild BSS138K INFINEON BSS223PW STM STB16PF06L

VZ = 5.5V @ 10uA VZ = 5.6V @ 250uA VDSMAX = 50V VTH = 0.8V VTH = 0.95V (typ) VTH = 1.2V (max) VTH = 1.2V (max) VDSS = 50V VTH = 0.9V (typ) VTH = 1.2V (max) VTH = 1.5V (max) VDSS = 60V

ETH1-230L

Inductance = 350 µH

Vishay SI7469 Fairchild FDMS8560

RDSON = 21 mΩ VTH = 3V (max) RDSON = 2 mΩ VTH = 2.2V (max)

IV. MEASUREMENT The assembled prototype is shown in Fig. 9 with highlighted region for the biasing block, the current-balancing circuit, and the hot-swapping control block. The RJ45 cable that conducting the power from PSE to the proposed interface is around 2 Ω for both channels. The value of M , is then chosen accordingly to be 1 kΩ so that the current-balancing loop has a gain of at least 66 based on (5). All other resistors and capacitors have values labeled in Fig. 3, Fig. 4(b) and Fig. 7. The rest components have their part numbers and some key parameters listed in Table I. The Zener chosen for biasing the internal supply has a reverse clamping voltage (VZ) of ~5.6V under ~100 µA reverse current. Since the biasing currents are spread across the board, source degeneration resistors are used to reduce the current mismatch caused by transistor variations and thermal offset. The measured current-balancing function is shown in Fig. 10. An offset between the two channels was ramped up with a common voltage of 45V. The waveforms shown in Fig .10(a) and Fig. 10(b) are the results without and with the current-balancing function, respectively. Without current-balancing control, at a load current ( ) of 0.5A, an offset of 150 mV caused all the load current to steer into one channel, as shown in Fig. 10(a). The results with current-balance control in Fig. 10(b) showed evenly distributed current after settled to steady state. The input offset of 400 mV was compensated by an increased

(b) Fig. 10. Measured current waveforms to check current- balancing function. (a) The result without current- balancing control. (b) The result with current-balancing control.

regulation current ∆ NO of 0.7 µA which was fed into the gate of the pass device. The measured DC current mismatch between the two channels was less than 1% for an input offset of up to 400 mV. If the offset voltage reserved its polarity, the measured ∆ NO remained unchanged while ∆ NO was increased to regulate the pass PMOS in the other channel. To further check the reliability of the current-balancing function, the measured waveforms with perturbations from the supply common voltage and the load current are shown. The measured load current step response is shown in Fig. 11(a). The currents in both channels remained to be half of total load current which was stepped from 0.2 A to 0.36 A. The measured step response from the input common voltage is shown in Fig. 11(b). The current in both channels showed negligible shift while the common voltage was increased from 42V to 45V. An input offset voltage of 0.2V was added to both step responses to represent a more practical condition. The hot-plugging effects have a strong dependence on the size of the PD decoupling capacitor CPD, as discussed in section III-C. Therefore, the experiment was taken with CPD sizes of 200 µF, 100 uF, 33 µF, 10 µF, and values below 5 µF, as shown in Fig. 12. The hot-plugging was executed by shorting the input side of the RJ45 cable directly to a 45V supply. In Fig. 12, after the event of hot-plugging, the two rails (VLOAD and VSS) on the PD side ramped up together with VDD. This proved an effective isolation between VSS and VGND by the pass device MN0 which had its VGS held low by R0 after initial startup, as described in subsection III-C. The experiment in Fig. 12(a) and Fig. 12(b) had their CPD values higher than the 7 _8' value of ~50 µF based on (7), so the CPD is charged with a fixed limited current of ~0.45 A based on (9). The results showed that larger load capacitors led to a longer charging time and a slower ramping rate on net VSS. In Fig. 12(c), the PD voltage finished ramping with a peak current of 0.28 A which was lower than the current limit of 0.45 A. Therefore, in this condition the MN0 is regulated by the slew-rate limiting loop which yielded a maximum VSS




9

(a)

(a)

(b) Fig. 11. Measured current-balancing result under the responses of (a) the load current step and (b) the common voltage step.

(b)

ramping rate of 6.5 V/msec. The measured ramping rate was lower than the calculated result of 10 V/msec based on (11) due to mismatch in the current mirrors and the parasitic capacitance on net VRAMP_REF. The result shown in Fig. 12(e) was taken without CPD added to the PD supply, but the measured waveforms were the same with any CPD value less than 5 µF. To check the loss and power distribution of the proposed interface, experiments were carried out under different offset voltage and load current conditions with results shown in Fig. 13. The two channels were set to the polarities so that MP1, MP3, MN2, and MN4 in the active diode bridge stage were selected to be turned on. The loss of the pass devices (MN0, MP1,3 and MN2,4) were calculated based on their measured source-to-drain voltages. The RSNS portion in those pie charts represented the total loss due to RSNS0, RSNS1 and RSNS2, while the MN2,4 portion represents the total loss due to MN2 and MN4. The offset voltage between the two channels was set in a polarity so that the VDS of MP1 was in regulation. The measured results showed that the power dissipated by the pass PMOS (MP1) increased as either the offset voltage or the load current increased, as predicted by the calculated result in Fig. 5. The total loss of 158 mW in the last pie chart resulted in an overall efficiency drop of 0.63 % by = 50 ). the proposed interface (assuming The performance comparison among the PoE interfaces is shown in Table I. The proposed design and [12] [13] use all four pairs of the CAT5 cable for power delivery, therefore they output higher power than the other two with only two pairs enabled. However, the design in [12] has no current balancing control, so its maximum deliverable power is derated compared with [13] and this work. The current consumption of the PoE interfaces is around several mA which is much lower than the one consumed by its succeeding stage of DC-DC converter. The proposed prototype and measured results exhibit great potential of achieving better performance if all control circuitry can be realized by integrated circuit technique, which will reduce the cost, power, area of the prototype but with increased reliability and matching performance.

(c)

(d)

(e) Fig. 12. Measured hot-swapping waveforms under load capacitor of (a) 220 µF, (b) 100µF, (c) 33 µF, (d) 10 µF and (e) any size below 5 µF.

V. CONCLUSION This paper proposed a PoE interface that aims at high power PD applications by utilizing all four pairs of the CAT5 cable for current delivery. To achieve maximum power delivered to the PD devices, the currents in the two channels of the CAT5 cables are regulated to be balanced with measured current mismatch less than 1%. The proposed interface includes a hot-plugging control block that helps protects the PoE system. The peak load




MP1 MP3

10 [8] C. Jones, "PoE Targets More Applications With Higher-Power IEEE 802.3bt," Electronic Design, 2014.

RSNS MP1

MN0

MP1

MP3 RSNS

MN2,4

MN0

MP3 RSNS MN0 MN2,4

MN2,4 Ctrl

Ctrl

0 V offset 0.2 A IPD Total loss = 51 mW MP1

Ctrl

200 mV offset 0.2 A IPD Total loss = 70 mW


MP3 RSNS

Ctrl

Ctrl

MP1

MP1

MP3 RSNS Ctrl MN2,4

MN0

0 V offset 0.5 A IPD Total loss = 94 mW

MN0

MN2,4


MN2,4

MP3 MN0 RSNS 200 mV offset 0.5 A IPD Total loss = 142 mW

Fig. 13. Measured loss distribution of the proposed interface under different offset voltage and load current conditions.

TABLE II COMPARISON AMONG PO E INTERFACES [13] [26] [20] [12] Wu Li ADI TI

This work

# of Pairs

4

2

2

4

4

Max. pwr.

48 W

30 W

25.5 W

~35 W*

~48 W

Protect Cur. Balancing

Inrush cur. Inrush cur. Inrush cur. Inrush cur. Y

N

Inrush cur. & slew-rate

[9] B. M. Jassim, D. J. Atkinson, and B. Zahawi, "Modular Current Sharing Control Scheme for Parallel-Connected Converters," IEEE Trans. Ind. Electron., vol. 62, no. 2, pp. 887-897, 2014. [10] S. Luo, Z. Ye, R. L. Lin and F. C. Lee, "A classification and evaluation of paralleling methods for power supply modules," in IEEE PESC 99. 30th Annual, 1999. [11] J. W. Kim, H. S. Choi, and B. H. Cho, "A Novel Droop Method for Converter Parallel Operation," IEEE Trans. Power Electron., vol. 17, no. 1, pp. 25 - 32, 2002. [12] S. R. Tom, "Current balancing in four-pair, high-power PoE applications".Texas Instruments. [13] J. Wu, H. Wu, C. Li, W. Li, X. He and C. Xia, "Advanced Four-Pair Architecture With Input Current Balance Function for Power Over Ethernet (PoE) System," IEEE Trans. Power Electron., vol. 28, no. 5, pp. 2343 - 2355, 2012. [14] H. S. Kim, H. W. Seong, J. H. Cho, J. B. Lee, K. B. Park, G. W. Moon, and M. J. Youn, "Start-Up Control to Prevent Overcurrent During Hot Swap in Paralleled DC–DC Converters," IEEE Trans. Ind. Electron., vol. 60, no. 12, pp. 5558 - 5574, 2013. [15] S. Fan, Z. Xue, Z. Guo, Y. Wang, and L. Geng, "VRSPV Soft-Start Strategy and AICS Technique for Boost Converters to Improve the StartUp Performance," IEEE Trans. Power Electron., vol. 31, no. 5, p. 2016, 3663 - 3672. [16] H. Kim, H. Seong, J. Cho, J. Lee, K. Park, G. Moon, and M. Youn, "StartUp Control to Prevent Overcurrent During Hot Swap in Paralleled DC– DC Converters," IEEE Trans. Ind. Electron., vol. 60, no. 12, pp. 55585574, 2013. [17] C. Chuang and M. Ker, "On-Chip Transient Voltage Suppressor Integrated With Silicon-Based Transceiver IC for System-Level ESD Protection," IEEE Trans. Ind. Electron., vol. 61, no. 10, pp. 5615-5621, 2014.

N

N

Y

[18] W. Tabisz, M. Jovanovic, and F. Lee, "Present and future of distributed power systems," in APEC, Conference Proceedings of, 1992.

Board 0.85 mA

[19] K. Pollak, "Improvements in Means for Controlling or Directing Electric Currents". British Patent 24398, 1895.

IC or Board

Board

IC

IC

IC & Board

Cur. con. **

N/A

N/A

1.35 mA

N/A

*Extracted from the figure in datasheet. **Current consumed by PoE interface.

current and the maximum voltage ramping rate on the PD supply are controlled by two separated regulation loops. For better energy efficiency, a single pass NMOSFET is inserted in the PD ground current path and is shared by both regulation loops. Under a hot-plugging event, the measured peak current and the maximum slew rate matched the calculated results.

[20] Linear Technology, "IEEE 802.3 at High Power PD Interface Controller with 2-Event Classification Recognition".LTC4265 Datasheet. [21] Y. Chen, D. K. Cheng, Y. Lee, "A Hot-Swap Solution for Paralleled Power Modules by Using Current-Sharing Interface Circuits," IEEE Trans. Power Electron., vol. 21, no. 6, pp. 1564 - 1571, 2006. [22] N. Talebbeydokhti, P. K. Hanumolu, P. Kurahashi and U. Moon, "Constant transconductance bias circuit with an on-chip resistor," in ISCAS, 2006. [23] "Fundamentals of Electrostatic Discharge," Compliance Magazine, 1 May 2015. [24] Coilcraft, "“PoE Plus” Magnetics," ETH1-230L datasheet.

REFERENCES [1] J. A. Maestro and P. Reviriego, "Energy Efficiency in Industrial Ethernet: The Case of Powerlink," IEEE Trans. Ind. Electron., vol. 57, no. 8, pp. 2896 - 2903, 2009. [2] M. S. Alamgir and M. S. Islam, "PoE (Power over Ethernet) switch based remote power control system for the better performance of ISPs in Bangladesh," in ICCIT, 2015. [3] R. V. White, "Electrical isolation requirements in power-over-Ethernet (PoE) power sourcing equipment (PSE)," in APEC, 2006. [4] M. Yokohata, T. Maeda and Y. Okabe, "Power Allocation Algorithms of PoE for On-Demand Power Supply," in COMPSACW, 2013. [5] "IEEE 802.3 standard," [Online]. Available: http://standards.ieee.org/about/get/802/802.3.html. [6] CISCO, "Cisco Universal Power Over Ethernet: Unleash the Power of your Network," 2016. [7] Linear Technology, "High Power PoE PD Interface with Integrated Flyback Controller".Design Note 425.

[25] Vishay Siliconix, "P-Channel 80-V (D-S) MOSFET".Si7469DP Datasheet. [26] Y. Li and Z. Zhu, "A 30-W 90% Efficiency Dual-Mode Controlled DC– DC Controller With Power Over Ethernet Interface for Power Device," IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 25, no. 6, pp. 1943 - 1953, 2017.

Zhiming Xiao (M’17) received the B.S. degree from Huazhong University of Science and Technology, Wuhan, China, in 2006, and the M.S. and Ph.D. degrees in electrical engineering from the University of Florida, Gainesville, FL, USA, in 2008 and 2013, respectively. Since 2011, he has been a Design Engineer with the Analog Devices’ Power Management IC Group. His research interests include micropower analog circuits design, switching power converters and their digital control techniques.
