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An Electronic Synapse Device Based on Solid Electrolyte Resistive Random Access Memory Wei Zhang, Ying Hu, Ting-Chang Chang, Kuan-Chang Chang, Tsung-Ming Tsai, Hsin-Lu Chen, Yu-Ting Su, Tian-Jian Chu, Min-Chen Chen, Hui-Chun Huang, Wan-Ching Su, Jin-Cheng Zheng, Ya-Chi Hung, and Simon M. Sze Abstract— The multilevel capability of solid electrolyte resistive random access memory (RRAM) with a Pt/GeSO/TiN structure was explored for potential use as a synapse device. By varying the cutoff voltage during the dc I–V cycles or the ac pulse programming voltage amplitudes, continuous multilevel conductance states were obtained. The reference Pt/GeO/TiN RRAM was fabricated to certify the multilevel capability and was due to the character of the GeS solid electrolyte. Finally, the property of gradual conductance states was exploited to demonstrate spike-timing-dependent plasticity learning, which suggests device’s potential for use as an electronic synapse device for neuromorphic systems. Index Terms— RRAM, solid electrolyte, electronic synapse device, spike-timing-dependent plasticity learning (STDP).
I. I NTRODUCTION
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VER the last decades, rapid advances in digital electronic devices have substantially changed society. However, there are still some bottlenecks in the von Neumann system, such as the low speed of non-volatile storage devices and power consumption. Learning and intelligence also have not been captured in this classic system. Bio-inspired neuromorphic systems have attracted much attention for their excellent properties, including energy-efficiency, parallelism, Manuscript received June 1, 2015; accepted June 19, 2015. Date of publication June 23, 2015; date of current version July 22, 2015. This work was supported in part by the National Science Council Core Facilities Laboratory for Nanoscience and Nanotechnology in Kaohsiung-Pingtung and in part by the Ministry of Science and Technology, Taiwan, under Contract MOST-1032112-M-110-011-MY3. The review of this letter was arranged by Editor C. V. Mouli. (Corresponding authors: Ying Hu and Ting-Chang Chang.) W. Zhang and Y. Hu are with the School of Advanced Materials and Nanotechnology, Xidian University, Xi’an 710000, China (e-mail:
[email protected]). T.-C. Chang, Y.-T. Su, and M.-C. Chen are with the Department of Physics, National Sun Yat-sen University, Kaohsiung 80424, Taiwan, and also with the Advanced Optoelectronics Technology Center, National Cheng Kung University, Tainan 700, Taiwan (e-mail:
[email protected]). K.-C. Chang, T.-M. Tsai, T.-J. Chu, H.-C. Huang, and Y.-C. Hung are with the Department of Materials and Optoelectronic Science, National Sun Yat-sen University, Kaohsiung 804, Taiwan. H.-L. Chen and W.-C. Su are with the Department of Mechanical and Electro-Mechanical Engineering, National Sun Yat-sen University, Kaohsiung 804, Taiwan. J.-C. Zheng is with the Department of Physics, Xiamen University, Xiamen 361005, China. S. M. Sze is with the Department of Physics, National Sun Yat-sen University, Kaohsiung 804, Taiwan, and also with the Department of Electronics Engineering, National Chiao Tung University, Hsinchu 300, Taiwan. Color versions of one or more of the figures in this letter are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/LED.2015.2448756
and fault tolerance [1]–[4]. In addition, arithmetic operations which are based on analog memories also present an attractive computation paradigm to complement future digital von Neumann systems [5]–[9]. Thus, it is a great but meaningful challenge to simulate such an intelligent and energyefficient system. In this letter, we present a novel electronic synapse device which, due to its multilevel capability performance, is a good candidate for neuromorphic systems. The property of gradual resistance was exploited to demonstrate the STDP learning rule achieved by proper design of the spike signaling scheme. II. E XPERIMENTAL S ETUP Synapse devices with a Pt/GeSO/TiN thin-film stack structure were fabricated using the following procedures. A 16nm thick switching layer was deposited on the TiN/Ti/SiO2 /Si substrate by RF magnetron sputtering with the target of GeS. Ultimately, the Pt top electrode with a thickness of 200nm was deposited by DC magnetron sputtering. By material analyses of X-ray photoelectron spectroscopy (XPS), we obtained the mole fraction Ge:S:O in the switching layer of 55%:23%:22%, a result of equipment and condition limitations. The cell size of the RRAM device via in this experiment is 0.8μm∗0.8μm. All the electrical analyses were performed using an Agilent B1500A semiconductor parameter analyzer. III. R ESULTS AND D ISCUSSION The electronic synapse structure is shown in Fig. 1(a), and the current-voltage (I-V) characteristic curve of the electronic synapse device measured by DC cycle sweep is shown in Fig. 1(b). During the set process, a series of positive cutoff voltages from 0.56V to 0.76V with a step of 0.02V are exerted, while in the reset region voltage is changed from −0.92V to −1.08V with a step of −0.02V. Every cutoff voltage in both the set and reset regions is operated 10 times before changing to another cutoff voltage. By showing the I-V curves at the positive sweep in linear scale, a series of continuous multi I-V curves are obtained, as shown in Fig. 1(c); likewise, similar characteristics for negative sweep are obtained and shown in Fig. 1(d). During the positive bias ramp, the device can be set from the highresistance state (HRS) to low-resistance state (LRS). While in the negative bias ramp, the device can be reset from LRS to HRS. The multiple states between LRS and HRS are the analog memory characteristics. Both the set (increase) and reset (decrease) process are equivalent to potentiation and
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ZHANG et al.: ELECTRONIC SYNAPSE DEVICE BASED ON SOLID ELECTROLYTE RESISTIVE RANDOM ACCESS MEMORY
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Fig. 1. (a) Structure of the device with GeSO switching layer. (b) Bipolar resistance switching I-V curves of Pt/GeSO/TiN device. The corresponding multi-state I-V curves in linear scale in the (c) reset and (d) set processes.
Fig. 2. Pulse trains consisting of (a) 100 gradually increasing reset pulses (−1V to −1.3V) and (b) 100 fixed-voltage (−1.1V) reset pulses, both having 100 fixed-voltage (0.7V) set pulses, with pulse width of 0.1μs and pulse delay of 0.2μs.
depression in biological synapses. In this experiment, the bias voltage is given at the TiN electrode and the Pt electrode is grounded, and all the resistance and conductance are obtained at 0.1V. The practical applications of electronic synapse devices are under pulse voltage amplitudes rather than the DC voltage amplitudes. Therefore, the property of gradual conductance changes under pulsing voltage amplitudes is investigated. As shown in Fig. 2(a), the initial state is at LRS, and a pulse train consisting of 100 gradually increasing negative pulses is exerted on the TiN electrode with the pulse voltage amplitudes from −1V to −1.3V, and a voltage step of −0.003V. The pulse width is 0.1μs and the pulse delay is 0.2μs. During this process, the device gradually changes to HRS. Next, a pulse train consisting of 100 positive 0.7V pulses is exerted on the TiN electrode with the same pulse width and delay. This time, the device gradually changes from HRS to LRS. When these two processes are repeated 10 times, the uniform characteristics are demonstrated. If the gradually increasing reset pulse voltages are changed to a fixed pulse voltage (−1.1V), the same characteristics can also be obtained, as shown in Fig. 2(b). These multilevel capabilities in DC cycles and in pulse set/reset processes suggest that it is an excellent candidate for an electronic synapse device. In order to clarity that all the characteristics are the effects of the GeS solid electrolyte, the reference substance
Fig. 3. Bipolar resistance switching I-V curves for (a) Pt/GeSO/TiN and (b) Pt/GeO/TiN devices. Pulse set/reset characteristics for (c) Pt/GeSO/TiN and (d) Pt/GeO/TiN devices. (e) Pt/GeSO/TiN device, showing a series of gradually increasing responses with increasing width and voltage. (f) Pt/GeO/TiN device, showing a sharp increased response only after a certain width and voltage.
Pt/GeO/TiN resistive switching devices were fabricated with the same electrodes and switching layer thicknesses. The basic DC I-V curves look similar, except for the set process of the Pt/GeSO/TiN device gradually rising while the set process of the Pt/GeO/TiN exhibits a sharp rise, shown in Fig. 3(a) and Fig. 3(b). We deduce that this phenomenon is due to the characteristics of the solid electrolyte GeS. A comparison of the Pt/GeSO/TiN and Pt/GeO/TiN devices by pulse set/reset indicates that the Pt/GeSO/TiN devices have a gradual multilevel capability, while the Pt/GeO/TiN devices exhibit a conductance gap during the set process, as can be clearly seen in Fig. 3(c) and Fig. 3(d). A series of gradually increasing set pulse voltages and pulse widths are applied to both devices to further clarify the GeS solid electrolyte effect. Fig. 3(e) and Fig. 3(f) clearly show that the conductance gradually increases with increasing pulse voltage and pulse width in Pt/GeSO/TiN devices. In Pt/GeO/TiN devices, however, there is a sudden sharp change in conductance. All the characteristics comparisons (Fig. 3(a) to Fig. 3(f)) suggest that the gradual multilevel conductance changes are due to the GeS solid electrolyte. To investigate the capability of electronic synapses for emulating the adaptive learning rules of biological synapses, an experiment to emulate the STDP in biological synapses is performed. In a biological synapse, when the pre-spike signal precedes the post-spike signal, the strength of the synapse will undergo a long-term potentiation (LTP); otherwise, it will
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IEEE ELECTRON DEVICE LETTERS, VOL. 36, NO. 8, AUGUST 2015
with step of 0.2μs, the design purpose is that when exerted on the device, with this pulse scheme, the post-spike can overlap and enhance all the pulse amplitudes in pre-spike (the voltage dropped on the electronic synapse is defined as the voltage of pre-spike minus post-spike.) with the spike timing changes. The pulse schemes are shown in Fig. 4(a). A certain intermediate resistance state is chosen as an initial state, and the currents before and after each spike timing are measured for 10 times at 0.1V, calculated by ω=(Iafter -Ibefore )/Ibefore , the data are presented by error bars. After that, the resistance of electronic synapse back to the certain intermediate state by electronic operating. The STDP-like characteristics reflect in Fig. 4(b). In this letter, The STDP-like curve is obtained by changing the spike timing of the electronic synapse, so with the designed pulse schemes, the conductance of the electronic synapse changes along with the changes of spike timing. IV. C ONCLUSION
Fig. 4. (a) The STDP realization schemes, the pre-spike pulse scheme consists of five negative pulses and five positive pulses with the negative pulse amplitudes are −0.7, −0.8, −0.9, −1.0 and −1.1V; the positive pulse amplitudes are 0.7, 0.6, 0.5, 0.4 and 0.3V, the post-spike pulse scheme consists of a negative (−0.3V) and a positive pulse (0.6V). The pulse amplitude across the device is Vpre -Vpost . All the pulse widths and pulse delays are 0.1μs. (b) The STDP-like curve obtained by the electronic synapse device, with feedback defined as ω=(Iafter -Ibefore )/Ibefore , where Ibefore and Iafter are the respective currents at 0.1V before and after the pre-spike and post-spike pairs. The spike timing is defined as t=tpost -tpre .
undergo a long-term depression (LTD). During both these processes, closer spike timings lead to a larger change of feedback. In this experiment, the feedback is defined as ω=(Iafter -Ibefore )/Ibefore , where Ibefore and Iafter are the respective currents at 0.1V before and after the pre-spike and post-spike pairs. The spike timing is defined as t=tpost -tpre . A train of 10 pulses consisting of five negative depression pulses and five positive potentiation pulses is designed as pre-spike, with the negative pulse amplitudes are −0.7, −0.8, −0.9, −1.0 and −1.1V; the positive pulse amplitudes are 0.7, 0.6, 0.5, 0.4 and 0.3V. The post-spike is similarly designed as a pulse train consists of one negative (−0.3V) and one positive (0.6V) pulse. All the pulse widths and pulse delays are 0.1μs, and the spike timings are designed from −1.0μs to 1.0μs,
In conclusion, an electronic synapse device based on GeS solid electrolyte RRAM is fabricated by magnetron sputtering GeS and Pt targets. Due to the limitations of the equipment and conditions, the switching layer is GeSO, as suggested by the material analyses. Multilevel conductance states were obtained both by DC cycles and pulse processes. The reference Pt/GeO/TiN resistive switching devices were fabricated to clarify that all the characteristics are effects of the GeS solid electrolyte. One of the most fundamental adaptive learning rules of biological synapses, the STDP learning rule, is also investigated through the fabricated electronic synapse. R EFERENCES [1] E. Chicca et al., “A VLSI recurrent network of integrate-and-fire neurons connected by plastic synapses with long-term memory,” IEEE Trans. Neural Netw., vol. 14, no. 5, pp. 1297–1307, Sep. 2003. [2] S. Fusi et al., “Spike-driven synaptic plasticity: Theory, simulation, VLSI implementation,” Neural Comput., vol. 12, no. 10, pp. 2227–2258, 2000. [3] S. H. Jo et al., “Nanoscale memristor device as synapse in neuromorphic systems,” Nano Lett., vol. 10, no. 4, pp. 1297–1301, 2010. [4] W. Zhang et al., “Mechanism of triple ions effect in GeSO resistance random access memory,” IEEE Electron Device Lett., vol. 36, no. 6, pp. 552–554, Jun. 2015. [5] G. Q. Bi and M. M. Poo, “Synaptic modifications in cultured hippocampal neurons: Dependence on spike timing, synaptic strength, and postsynaptic cell type,” J. Neurosci., vol. 18, no. 24, pp. 10464–10472, 1998. [6] S. Park et al., “Nanoscale RRAM-based synaptic electronics: Toward a neuromorphic computing device,” Nanotechnology, vol. 24, no. 38, p. 384009, 2013. [7] S. Yu et al., “An electronic synapse device based on metal oxide resistive switching memory for neuromorphic computation,” IEEE Trans. Electron Devices, vol. 58, no. 8, pp. 2729–2737, Aug. 2011. [8] S. Yu et al., “A low energy oxide-based electronic synaptic device for neuromorphic visual systems with tolerance to device variation,” Adv. Mater., vol. 25, no. 12, pp. 1774–1779, 2013. [9] K.-C. Chang et al., “Origin of hopping conduction in graphene-oxidedoped silicon oxide resistance random access memory devices,” IEEE Electron Device Lett., vol. 34, no. 5, pp. 677–679, May 2013.
