2-26 PCM-PWM converter Architecture. 46. 2-27 Jitter Simulation Scheme in SIMULINK. 49. 2-28 Comparison of PCM-PWM Converter PSD with and without ...
AN ENHANCED CLASS-D AMPLIFIER ARCHITECTURE by MICHAEL SCOT PATE, B.S.E.E., M.Sc.E.E., M.S.E.E., M.S. A DISSERTATION IN ELECTRICAL ENGINEERING Submitted to the Graduate Faculty of Texas Tech University in Partial Fulfillment of the Requirements for the Degree of DOCTOR OF PHILOSOPHY Approved Kwong Chao
Chairperson of the Committee
Tanja Karp Michael Giesselmann Sunanda Mitra
Accepted John Borrelli
Dean of the Graduate School
December, 2005
©2005, Michael S. Pate
ii
ACKNOWLEDGEMENTS Through the process of finishing my studies many people have played an important role in getting me to where I am. I would first like to thank Dr. Kwong Chao for all of his help and support over the past several years. He has helped me to find my way and always is there to offer guidance or help in anything, scholastic or otherwise. I would also like to thank Lars Risbo for helping throughout my studies in Denmark and beyond. He has suffered through countless revisions and ideas, for that he deserves my deepest thanks. I would also like to thank all of my family, for understanding when I disappear for months at a time to work and for helping out in any way they could along the way. Most importantly I would like to thank my wife Nichole. She is by far the major driving force that has allowed me to accomplish what I have over the course of the past seven years. She has always been there to listen to me as I work through problems, even when she has no idea what I am talking about. She has always understood when I have had to work long hours and is always there to make sure that I occasionally take time for myself. She has made all of the work possible, taking care of everything that I have not had time to. Without her I would be lost.
iii
TABLE OF CONTENTS ACKNOWLEDGEMENTS
iii
ABSTRACT
viii
LIST OF FIGURES
ix
LIST OF TABLES
xvii
CHAPTER I
II
INTRODUCTION
1
PWM Introduction
2
Class-D Introduction
3
Proposed System Introduction Output Stage Introduction Conversion Stage Introduction
5 6 12
Full System
13
SYSTEMS ANALYSIS
15
Output Stage Basic Analysis Waveform Analysis Inherent System Error Quantizer Analysis System Stability Maximum Input Level Pulse Skipping Comparison to Previous Architecture
15 16 17 27 30 35 37 39 43
Converter Stage PCM-PWM Conversion Feed-Forward Loop System Theory Nonlinear Error Rejection
46 47 47 47 51
Choosing System Parameters
51
iv
III
IV
V
System Design Conclusion
53
CIRCUIT LEVEL DESIGN
54
Integrated Circuit Overview
54
Design Simulation
56
PCM-PWM Conversion Stage Design PCM-PWM converter Digital Sigma-Delta Converter Feed-Forward Components
56 57 61 70
Output Stage Design Loop-Filter Output Devices Full Output-Stage Simulations Error Detector
72 73 88 89 91
Design Conclusions
93
SYSTEM VERIFICATION
97
Test Plan
97
Test Circuit Circuit PCB
99 99 103
Results PCM-PWM Conversion Accuracy Error Correction Error Limiting DC to DC Sigma-Delta Converter
104 106 108 111 113
Testing Conclusions
113
FURTHER ENHANCEMENTS AND CONCEPTS
114
Resolution Enhancement Architecture Resolution Enhancement Performance Error Effects
114 116 121
Additional THD Compensation
122
v
VI
CONCLUSION
125
REFERENCES
127
APPENDIX A
Fourier Decomposition of the Loop-Filter Input
133
B
Device Layouts and Schematics
138
Full System
138
Conversion Stage PCM-PWM Converter Digital Comparator
140 142 144
Sigma Delta Converter Digital Adder Digital Integrator Multiply by Two
146 147 148 149
Feed-Forward Correction Special Adder Loop-Filter Analog Adder
150 150 151 151
Output Stage Loop-Filter Operational Amplifiers Integrators Low-Pass Filter Comparator Error Detection Circuit Output Devices
152 153 154 156 157 157 158 160
VERILOG CODE
161
Test Blocks 7-bit A/D converter 9-bit D/A Converter
161 161 162
Sigma Delta Blocks 7-bit to 9-bit Converter 9-bit Digital Adder with Wrap Protection 9-bit Unit Delay
163 163 164 165
C
vi
9-bit to 1-bit quantizer 1-bit to 9-bit Converter with Inversion 9-bit Multiply by 2
166 166 167
PCM-PWM
168
Analog Components Simple Gain Analog Adder Analog Subtraction
169 169 170 170
vii
ABSTRACT This dissertation presents several enhancements to the standard digitalinput Class-D amplifier structure. Improvements are made both in the conversion process where the standard CD audio Pulse Code Modulation (PCM) signal is encoded in a Pulse Width Modulation (PWM) scheme as well as in the power amplification stage where the PWM signal is amplified to allow for proper load driving power. Theory is developed as a means of demonstrating the power of the enhancements, SIMULINK and MATLAB simulations are then used to verify the introduced theory. The structure is then taken through the schematic design and integrated circuit layout using the CADENCE design environment and fabricated through the MOSIS design foundry. The fabricated device is tested using a custom made test PCB to allow for maximum testing flexibility with minimum required external equipment. The results of the testing are analyzed and ideas for future enhancements to the overall topology are given.
viii
LIST OF FIGURES 1-1
PWM Waveforms Example
2
1-2
Creation of PWM waveform using triangle wave reference
3
1-3
Simple Digital PWM Generation Topology
5
1-4
Full H-Bridge Schematic
6
1-5
Half-Bridge Schematic
7
1-6
Proposed Loop-Filter Topology
7
1-7
Output Stage Topology
8
1-8
PWM Pulse Compensation
9
1-9
System Input, System Output, and Loop-Filter Input Signals
10
1-10 Loop-Filter Output with and without Injected Error
10
1-11 Error Correction Schematic
11
1-12 Proposed PCM-PWM Converter Architecture
13
1-13 Full Proposed System Architecture
14
2-1
Output Stage Architecture
15
2-2
Loop-Filter Topology
16
2-3
General Output Stage Architecture
16
2-4
System Input, System Output and Loop-Filter Input with Injected Error
18
2-5
Loop-Filter Output Waveform
19
2-6
Effect of Non-Ideal K1 on Linearity
22
2-7
2nd and 3rd Harmonic Comparison
26
2-8
Loop-Filter Output with no Inherent Error
29
ix
2-9
Loop-Filter Output Showing Inherent System Error
29
2-10 Comparison of Simulated and Calculated Quantizer Gain
32
2-11 Calculated Second and Third Harmonic Levels as a Function of Frequency
33
2-12 PSD with Large Third Harmonic
34
2-13 PSD with Large Second Harmonic
34
2-14 Comparison of Calculated to Simulated Third Harmonic Level as a Function of Frequency
35
2-15 Unstable System due to Poor Placement of Low-Pass Filter Pole
37
2-16 Timing Definitions for Maximum Input Calculation
37
2-17 Large Amplitude Demonstration
39
2-18 Runaway Error Pulse Skipping
40
2-19 Output Oscillations Due To Large Error
40
2-20 Demonstration of Limited and Unlimited Slope
41
2-21 System Output with High Error with and without Slope Limiting
43
2-22 Previous Loop-Filter Architecture
44
2-23 NTF and STF of Both Systems with Comparable Parameters
44
2-24 Loop-Filter Linearity Comparison
45
2-25 Third Harmonic vs. Frequency Comparison
46
2-26 PCM-PWM converter Architecture
46
2-27 Jitter Simulation Scheme in SIMULINK
49
2-28 Comparison of PCM-PWM Converter PSD with and without Jitter Correction
50
2-29 Bode-Plot of Second-Order Integrator, Low-Pass Filter, and Total Loop Filter 52 x
2-30 Bode-Plot of Output-Stage NTF and STF
52
3-1
System Block Diagram
55
3-2
Output of PCM-PWM converter using VerilogA
57
3-3
Digital Comparator Simulation
59
3-4
Block Diagram of Reference Generation Circuit
60
3-5
Triangle Reference Generator Output
60
3-6
PCM-PWM Converter Output
61
3-7
Digital 7-bit to 1-bit Sigma-Delta Converter Topology
62
3-8
Block-Diagram of Digital Adder with Overflow Protection
64
3-9
Input and Output Waveforms of Digital Adder VerilogA
65
3-10 Input and Output Waveforms of Digital Adder Schematic
66
3-11 Input and Output Waveforms of Digital Integrator VerilogA
67
3-12 Input and Output Waveforms of Digital Integrator Schematic
67
3-13 Multiply by 2 Simulation VerilogA
68
3-14 Multiply by 2 Simulation Schematic
69
3-15 Full Sigma-Delta Output VerilogA
70
3-16 Full Sigma-Delta Output Schematic
70
3-17 Analog Adder Schematic
71
3-18 Ideal and Real Output of Analog Adder
72
3-19 Folded-Cascode Topology
73
3-20 Bode Plot of Folded-Cascode Op-Amp with Differential Input
77
3-21 Bode Plot of Folded-Cascode Op-Amp with Common Mode Input
78
xi
3-22 Input and Output of Folded-Cascode Op-Amp with Large Pulse Inputs
78
3-23 Single-Ended Op-Amp Schematic
79
3-24 Bode Plot of Single Ended Op-Amp with Differential Inputs
80
3-25 Bode Plot of Single Ended Op-Amp with Common-Mode Inputs
81
3-26 Single-Ended Amplifier Transient Response to a Pulse Input
81
3-27 Bias Output Voltages vs. Temperature
82
3-28 Non-Ideal Integrator Output Using SIMULINK
82
3-29 Integrator Schematic Input and Output
83
3-30 Integrator Input and Output when Bypass Devices are Engaged
84
3-31 Second Integrator Stage Response
84
3-32 Second Integrator Stage Response with Resistive Path Engaged
85
3-33 Low-Pass Filter Output
86
3-34 Comparator Simulation with DC=0
87
3-35 Comparator Simulation with DC=-0.5
87
3-36 Pad-Buffer Input and Output (alpha=2.57)
88
3-37 Input and Output Waveforms for Final Pad-Buffer (alpha=4)
89
3-38 Output Stage Ideal Input and Output
90
3-39 Output Stage Simulation with Simulated Injected Error
90
3-40 Output Stage with Large Simulated Injected Error
91
3-41 Output Stage with Large Error and Error Limiter Disabled
92
3-42 Output Stage with Large Error and Error Limiter Enabled
93
3-43 MOSIS Die to Package Bonding Diagram
94
4-1
Full Test System Schematic
100 xii
4-2
Device Supply Generation Schematic
101
4-3
DPST Chip Diagram
102
4-4
Discrete Loop-Filter Implementation Schematic
102
4-5
Test PCB Layout
103
4-6
3D Visualization of PCB
104
4-7
Fabricated Device
105
4-8
Zero DC Input and PWM Output
105
4-9
Low DC Input and PWM Output
106
4-10 High DC Input and PWM Output
106
4-11 Output Duty Cycle vs. Ideal Input Duty Cycle
107
4-12 PWM Input and Output
108
4-13 PWM Input and Output with Small Injected Error
108
4-14 PWM Input and Output with Large Injected Error
109
4-15 Output Duty Cycle vs. Injected Error
109
4-16 Pulse Skipping due to Large Injected Error
110
4-17 Extra Pulses due to Large Injected Error
111
4-18 System with Large Injected Error and Error Limiting Enabled and Disabled 111 4-19 Sigma-Delta Output and Conversion Clock
112
4-20 Sigma-Delta Output with Low Input DC Level
112
4-21 Sigma-Delta Output with High Input DC Level
113
5-1
Resolution Enhancement Architecture
115
5-2
Demonstration of Delay Chain Configuration
116
xiii
5-3
Architecture Comparison
117
5-4
DC Error of Test Systems
118
5-5
Small Signal DC Error of Test Systems
118
5-6
Average Error vs. Number of Stages in Delay Chain
119
5-7
Architecture of Resolution Enhancement Device used in Conjunction with Sigma Delta
120
5-8
Average Error of Resolution Enhancement Device with Sigma Delta vs. Number of Stages 120
5-9
Average Error vs. Delay Error for Error Occurring in Different Stages
122
5-10 PSD of Standard System and Enhanced System with Ripple Suppression 123 5-11 Third Harmonic vs. K1 for Compensated and Uncompensated Systems 124 A-1
Setup for Fourier Series of PWM waveforms
133
B-1
Full System Schematic
138
B-2
System Layout without Padring
138
B-3
Full System Layout
139
B-4
Conversion Stage Overall Schematic
140
B-5
Conversion Stage Overall Layout
141
B-6
PCM-PWM Converter Schematic
142
B-7
PCM-PWM Converter Layout
143
B-8
Digital Comparator Schematic
144
B-9
Digital Comparator Layout
144
B-10 Triangle Wave Reference Generator Schematic
145
B-11 Triangle Reference Generator Layout
145
xiv
B-12 Digital Sigma Delta Converter Schematic
146
B-13 Digital Sigma Delta Converter Layout
147
B-14 Digital Adder Schematic
147
B-15 Digital Adder Layout
148
B-16 Digital Integrator Schematic
148
B-17 Digital Integrator Layout
148
B-18 Multiply by Two Schematic
149
B-19 Multiply by Two Layout
149
B-20 Special Digital Adder
150
B-21 Feed-Forward Loop-Filter
151
B-22 Analog Adder
151
B-23 Output Stage Overall Schematic
152
B-24 Output Stage Overall Layout
152
B-25 Loop-Filter Schematic
153
B-26 Loop-Filter Layout
153
B-27 Folded-Cascode Op-Amp
154
B-28 Simple Single-Ended Op-Amp
154
B-29 Op-Amp Bias
155
B-30 Simple Single Ended Op-Amp
155
B-31 First Integrator
156
B-32 Second Integrator
156
B-33 Low-Pass Filter
157 xv
B-34 Comparator
157
B-35 Single Ended Adder
157
B-36 Error Detection Schematic
158
B-37 Error Detection Layout
158
B-38 Error Decision Schematic
159
B-39 Error Decision Layout
159
B-40 Pad-Driver Schematic
160
B-41 Pad-Driver Layout
160
xvi
LIST OF TABLES 2-1
Output Stage Parameter Summary
51
2-2
Conversion Stage Properties
53
3-1
Example Binary Coding Scheme
55
3-2
Device Size Summary for Folded-Cascode Op-Amp
75
3-3
Folded-Cascode Op-Amp Bias Voltages
76
3-4
Device Sizes for Single-Ended Differential Pair Op-Amp
80
3-5
Pin Descriptions of Device
94
xvii
CHAPTER I INTRODUCTION Class-D amplifiers are a relatively new technology in high performance audio applications. While the theory behind them has been around for some time [10, 45] they were generally considered to have distortion levels that were too high for standard audio applications [21]. It wasn’t until the early 1990’s that Class-D amplifiers began to emerge as possible replacements for the power hungry linear amplifiers that dominated the audio market [47]. Their use in emerging consumer electronics became more intriguing given their extremely high efficiency (~90%) which helps small device batteries last longer, also the possibility of an all-digital signal path allows for lower introduced noise than their analog counterparts [14]. Recently more and more devices have begun incorporating Class-D amplifiers as their performance continues to improve and their efficiencies begin attracting more attention in ever shrinking portable devices. This dissertation presents several improvements to the standard Class-D amplifier structure both in theory and implementation. Architectures are developed from a system level with initial verification using high level simulation tools like SIMULINK and MATLAB, then taken down to the layout level through the CADENCE design environment. The final product is a device fabricated by the MOSIS foundry using a TSMC 0.25 m process tested using a custom printed circuit board (PCB) designed to facilitate maximum flexibility in testing with minimal required external equipment. This chapter will introduce each of the components of the Class-D amplifier structure as well as give an overview of some of the techniques used in this type of amplification.
1
PWM Introduction Pulse Width Modulation (PWM) waveforms encode information in the amount of time that the pulse is in the ‘high’ state as compared to the ‘low’ state. The ratio of on time to off time through a single sample period is known as the duty cycle [19, 25]. The carrier frequency of the PWM waveform represents how often these pulses are instantiated, and is typically much higher than that of the information being encoded as would be expected from standard modulation schemes. Common two-level PWM waveform encoding schemes have symmetric or asymmetric pulses; in the latter the pulse begins or ends the edge of the sample period at a specific value and changes at some time within the sample period specified by the current duty cycle. Symmetric waveforms are centered about the middle of a pulse frame with the edges being equidistant from the center and defined by the current value of the duty cycle. An example of these three waveform types is shown in Figure 1.1. For the system proposed in this dissertation the symmetric PWM, or centered waveform will be used almost exclusively.
Figure 1-1: PWM Waveforms Example
2
Class-D Introduction The Class-D amplifier differs from standard linear amplifiers in that it is digital in nature, stemming from the digital nature of the PWM signal. The load of the amplifier is driven by power MOS devices that are switched on and off at high frequencies corresponding to the applied PWM signal. By switching the MOS devices completely on or completely off very few ohmic losses are encountered especially compared to Class-A or AB devices. This makes for a device with little Joule heating and thus higher possible efficiencies. Current Class-D amplifier designs can typically be broken down into two main sections, the first section is a conversion stage where the input signal is converted to a PWM waveform. The input to this stage can either be an analog or digital signal depending on the overall system architecture. The simplest system involves an analog input converter, where the analog input is simply compared to a generated triangle wave reference1 to create the PWM output, shown in Figure 1.2. In this example the frequency of the triangle wave corresponds to the PWM carrier frequency as discussed in Section 1.1.
Figure 1-2: Creation of PWM waveform using triangle wave reference This conversion process can be accomplished as simply as connecting the input and reference signals to the input of a high gain op-amp acting as a comparator, 1
Triangle wave references are used for symmetric PWM waveforms. For asymmetric PWM a sawtooth wave is used as the reference.
3
with the output of the comparator being the generated PWM waveform. A second type of system involves a digital input PWM converter in which the input is an encoded multi-bit digital signal. An example of a digital input is standard CD audio which is encoded in a Pulse Code Modulation (PCM) fashion with 16bits at 44.1 kHz [2, 25, 29, 38]. The creation of the PWM waveform from digital inputs can be accomplished similar to the analog input system by comparing the digital input to a digital triangle wave reference. The digital converter is slightly more complex than its analog counterpart, with the added complexity being required to reduce the number of bits from the standard 16-bit input. The bit number of the input must be reduced to allow for reasonable clock speeds through the device. Current converters utilize PWM carrier frequencies on the order of 380 kHz [17, 29, 34], in order to provide for a low error conversion from the input PCM to the output PWM the generated digital triangle reference should have as many bits as the input and should pass through all possible levels twice within the sample period. If this is the case then for the low error conversion of a 16-bit input to a 380 kHz output would require an internal clock of 380 kHz*2*216 or approximately 50 GHz. Obviously this is impractical, so the number of bits is reduced to seven or eight by some method that minimizes the error of the required quantization resulting in a clock of approximately 100 MHz. This is typically done through the use of a digital to digital sigma-delta converter operating with low over-sampling ratios allowing the conversion error to be shaped, resulting in lower quantization noise through the audio band. This basic conversion system is shown in Figure 1-3 and will be covered in detail in Chapter 2.
4
Figure 1-3: Simple Digital PWM Generation Topology The second major section of a Class-D amplifier takes the PWM waveform and amplifies it to desired power levels for the load. The main complexity in this stage is typically in the circuitry needed to switch the high-power output devices on and off [1, 22, 32, 58]. This additional circuitry can be extraordinarily complex as multiple stages might be required to allow for the low-voltage PWM input signal to be able to switch a high-voltage MOS device. Also included in this stage is circuitry needed to ensure that output currents due not exceed specific levels so that the device does not melt, as well as circuitry to make the system meet any output electro-magnetic interference (EMI) requirements. This EMI control is often accomplished by limiting the transition rate of the output transistors or by some “soft-switching” techniques [32, 58] Proposed System Introduction The system proposed in this dissertation includes enhancements to both of the main stages of the standard Class-D amplifier structure. On the power output side a specially designed loop-filter has been developed to help reduce the harmonic distortion that is produced through standard feed-back operation. On the conversion side a new technique to reduce the effects of clock jitter is developed using feed-forward schemes and the noise suppression effects of the
5
output stage. The following sections will give a more in-depth introduction to the components of each stage. Output Stage Introduction Typical operation of Class-D amplifiers involves the utilization of a full Hbridge as the load driving stage. The H-bridge topology provides excellent performance through the symmetry provided in the standard operation. Any error that exists at the supply will present itself on both sides of the load, effectively being cancelled out. A schematic of the full H-bridge with associated driver circuitry is shown in Figure 1-4.
Figure 1-4: Full H-Bridge Schematic There are however, certain situations in which a half-bridge would be preferable [56]. Implementing the output stage with only a half-bridge greatly reduces the systems ability to correct for errors both from a non-ideal power supply, and due to the non-equivalent resistance of the NMOS and PMOS devices which creates additional noise and DC offsets. To help compensate for the decreased error suppression a feedback topology can be implemented [30, 36, 56]. A schematic of the half-bridge output stage with associated driver circuitry is shown in Figure 1-5.
6
Figure 1-5: Half-Bridge Schematic The proposed output stage provides excellent error suppression and distortion performance through the use of a feedback loop with a specially designed loop-filter. The loop-filter used is an improvement of a design suggested in [56] and was proposed by Lars Risbo and Claus Neesgaard in [42]. This loop filter allows for very low levels of distortion by maximizing the linearity of the quantizer gain, as will be discussed in Chapter 2. The proposed loop-filter is comprised of a second-order integrator in parallel with a low-pass filter as shown in Figure 1-6. The gains of the two branches will be optimized to produce a low distortion operating regime; this will be discussed in greater detail in Chapter 2.
Figure 1-6: Proposed Loop-Filter Topology
7
The feedback loop used will compare the PWM output with the PWM input signal with no re-sampling of the output. Systems utilizing feedback often re-sample the output to create a digital signal for comparison at the PCM to PWM conversion stage [30]. This system is different because it does not require any re-sampling or direct link between the output stage and the conversion stage other than the signal path itself. This feedback topology makes analysis of the system, extremely complex due to the analog nature of the feedback and loopfilter mixed with the digital nature of the PWM signal itself, creating a new hybrid system that does not fit nicely into either category. The concept of this type of feedback within a Class-D power stage is relatively new, with only a handful of examples of loop-filters. The feedback architecture used for the output stage is shown in Figure 1-7 consists of a subtraction node, analog loop-filter, quantizer and output stage. This architecture is deceptively complex due to the analog loop-filter feeding an inherently non-linear quantizer, as well as the problem with the conversion of signals from amplitude levels to edge time levels. This conversion will be discussed in Chapter 2 and is the basis for the correction capabilities of the loop.
Figure 1-7: Output Stage Topology The proposed loop-filter is able to suppress injected output error by compensating for incorrect signal levels by modifying the duty cycle of the output. In this manner the system is able to keep the area of the output pulses the same as that of the input. A graphical illustration of this concept is shown in Figure 1-8,
8
where a signal level that is too low due to some output error is compensated with a larger duty cycle.
Figure 1-8: PWM Pulse Compensation At the output of the system the signal is passed through a low-pass filter to extract the audio signal and eliminate high-frequency components of the PWM wave, this filter also acts as an averaging mechanism making the corrected output indistinguishable from the input. To get an idea of how the system is able to modify the duty cycle the various pertinent waveforms can be examined. Figure 1-9 shows the system input, system output and loop-filter input waveforms under zero injected error conditions. Ideally the system output is just the input shifted by some constant time ts. This time delay comes from the inherent delay of the output stage due to a delay through the FET driver circuitry and from the behavior of the loop-filter output. Under zero injected error conditions ts is approximately equal to 2td, twice the delay of the output stage.
9
Figure 1-9: System Input, System Output, and Loop-Filter Input Signals With this type of stimulus the proposed loop-filter will have a simple trapezoidal output. When a low-frequency error is injected at the output, it gets integrated by the loop-filter causing a finite slope at the top and bottom of the trapezoidal output. These two waveforms are illustrated in Figure 1-10.
Figure 1-10: Loop-Filter Output with and without Injected Error
10
For this paper a transition time will be defined as the time when the system output is not at the same level as the system input causing a large loop-filter input and giving rise to the edges of the trapezoidal waveform in Figure 1-10. In contrast the non-transition times are when the system input and system output are at the same level causing, under zero injected error conditions, the flat regions in the trapezoidal waveforms. It turns out to be the slope of the nontransition regions of the loop-filter output caused by the small injected error that allows the system to correct for errors. Figure 1-11 looks more closely at the transition of the output waveform with and without injected error.
Figure 1-11: Error Correction Schematic The slope of the output during a transition period is dominated by the large amplitude of the difference of the input and output waveforms and is not affected very much by the injected error, making the slope constant (within limits). Since the slope is constant, any deviation in amplitude at the beginning of the transition will result in a different zero-crossing time proportional to the deviation in amplitude. Due to the negative feedback of the system, a negative output error will cause a positive slope, increasing the pulse width and thereby keeping a constant pulse area. It is in this manner any DC or slow moving errors are 11
corrected, higher frequencies are more complicated due to complicated interactions at the quantizer and little suppression by the loop transfer functions, these will be discussed in Chapter 2. Conversion Stage Introduction The conversion stage proposed in this dissertation utilizes the error suppression properties of the output stage introduced in Section 1.3.1 to allow for a suppression of clock jitter effects. Clock jitter is the term used for non-ideal clock edge position in the reference clock. These slight changes in clock edge times can become a big problem in systems where information is encoded in pulse width. In the case of the conversion from PCM to PWM the non-ideal pulse edge will cause the duty cycle of the output PWM waveform to be altered slightly, thus the clock jitter is directly coupled to the audio-band signal in the converted PWM waveform. The proposed converter uses a feed-forward topology to convert the injected clock jitter error into an amplitude level that the output stage treats as an error, causing the pulse width to be altered reducing the effects of the coupled jitter error. Typically an error that is put into the input of a feedback loop would pass directly through un-attenuated, this is not the case for the proposed output stage due to the presence of the quantizer. In essence the quantizer removes the ability of the system to distinguish if an error occurred at the input or the output. This means that the system will suppress the error regardless of where it came from. This will be described in more detail in Chapter 2. The general topology for this system is shown in Figure 1-12.
12
Figure 1-12: Proposed PCM-PWM Converter Architecture The feed forward loop consists of a sigma-delta converter with the output filtered and subtracted from a filtered version of the PWM signal. The sigmadelta converter is used to create a single bit reference signal with minimum error introduction through the conversion process. The main contribution to the jitter error is assumed to be in the conversion from the PCM to the PWM signal due to the coupling of the jitter to the audio-band signal. Thus a direct representation of the error in time will be put onto the PWM waveform as an amplitude error. Full System The full proposed system with all components introduced in this chapter is shown in Figure 1-13. Some of the notations in this Figure will be discussed further in Chapter 2.
13
Figure 1-13: Full Proposed System Architecture Figure 1-13 is just an overview of the systems level as many added signal input and output paths are included in the circuit level design which will be covered in Chapter 3.
14
CHAPTER II SYSTEMS ANALYSIS In this chapter a detailed analysis of the systems level design will be given for each of the proposed Class-D stages. Throughout the chapter SIMULINK simulations will be provided as a method to help verify the systems level theory. SIMULINK provides a good tool for analyzing high level behavioral models due to its graphical nature and signal-flow orientated approach. The output stage will be discussed first as many of the benefits of the proposed conversion stage depend on the performance of this stage. Output Stage The Output stage of the proposed device consists of three main components, the output transistors, quantizer and the loop filter as shown in Figure 2-1.
Figure 2-1: Output Stage Architecture The analysis of this architecture is very complex due to the inherent non-linearity of the quantizer, as well as the mixed time and amplitude regimes of the various signals. PWM signals exist primarily in the time level regime, this means that the pertinent information of the signal is encoded in the times of the pulse edges as opposed to the amplitude level. For the majority of the system analysis the loopfilter will be the focus, as it is where the capabilities of the system are
15
determined. The structure of the proposed loop-filter is shown again in Figure 22.
Figure 2-2: Loop-Filter Topology Basic Analysis Typically for a systems-level analysis of architectures containing a quantizer, the quantizer is modeled as a simple gain followed by and additive noise source for simplicity [42, 43, 44]. This will be shown to be an oversimplification, but it provides a good first-order approximation. Figure 2-3 shows this simplified topology for the systems level analysis:
Figure 2-3: General Output Stage Architecture From Figure 2-3 a System Transfer Function (STF) and a Noise Transfer Function (NTF), can be derived by examining the signal path from input to output and from the assumed error input to the output respectively, they are given as:
STF =
K q H (s ) Vout (s ) = Vin (s ) 1 + K q H (s )
(2.1)
16
NTF =
Vout (s ) 1 = V n (s ) 1 + K q H (s )
(2.2)
with the form of the loop-filter H(s) being defined as:
H (s ) =
K1 K2 K 2 ps 2 + K 1 s + K 1 p + = s s2 s 2 (s + p ) +1 p
(2.3)
Substituting (2.3) into (2.1) and (2.2) yields:
STF =
(
K q K 2 ps 2 + K 1 s + K 1 p
)
s 3 + p (K q K 2 + 1)s 2 + K q K 1 s + K q K 1 p
s 2 (s + p ) NTF = 3 s + p (K q K 2 + 1)s 2 + K q K 1 s + K q K 1 p
(2.4)
(2.5)
The gain of the quantizer, Kq presents a problem for the remainder of the analysis, in that it treats the signal path differently than the error path. For this analysis the signal path is defined as the actual response to the applied PWM signal amplitude, while the noise path is defined as the deviation in the ideal zero crossing time of the output due to the injected error level. The quantizer gain will be investigated further in Section 2.1.4. Waveform Analysis It is advantageous to create a detailed description of the loop-filter output waveform, both for conceptual understanding and for future analysis. This description can begin by assuming that the system output waveform is just a time delayed version of the system input with a small additional error signal and that all signals are in a steady-state condition. By further assuming that the error
17
signal is slow moving with respect to the carrier frequency it can be treated as a pseudo-DC signal. Using these assumptions the input, output and reference waveforms are shown in Figure 2-4 for a single sample period.
Figure 2-4: System Input, System Output and Loop-Filter Input with Injected Error From Figure 2-4 the loop filter input for a single sample period is defined as:
−E 2−E hi (t ) = Vin (t ) − Vout (t ) = − E
0 ≤ t < t1 t1 ≤ t < t1′ t1′ ≤ t < t 2 − 2 − E t 2 ≤ t < t 2′ −E t 2′ ≤ t ≤ Ts
(2.6)
The output of the loop-filter is given by the convolution of the loop-filter impulse response with the time dependant input as given in (2.6) [31]. It is advantageous to make a semi-informed guess as to the shape of the steady-state loop-filter output based on simulations, this is shown in Figure 2-5. 18
Figure 2-5: Loop-Filter Output Waveform The various definitions for times and amplitudes shown in Figure 2-5 will be used throughout this analysis. From (2.3) it can be shown that the impulse response of the loop-filter is given by [31]:
(
)
h f (t ) = K1t + K 2 pe − pt u (t )
(2.7)
which gives the steady-state loop-filter output as:
ho (t ) =
∞
hi (τ ) ⋅ h f (t − τ )dτ
(2.8)
−∞
Substituting (2.6) and (2.7) into (2.8) yields:
19
− ( An + E n ) +
ho (t ) =
Ap +
t
(2 − E )[K 1 (t − τ ) + K 2 pe − p (t −τ ) ]dτ
t1 ≤ t < t1′
t1
(− E )[K 1 (t − τ ) + K 2 pe − p (t −τ ) ]dτ
t1
Ap + E p + − An +
t
t
t
t1′ ≤ t < t 2
(− 2 − E )[K 1 (t − τ ) + K 2 pe − p (t −τ ) ]dτ
(2.9)
t 2 ≤ t < t 2′
t2
(− E )[K 1 (t − τ ) + K 2 pe − p (t −τ ) ]dτ
t 2′ ≤ t < t 3
t2
where t3 is the input rising edge time of the subsequent period. By implementing the assumption of the error being considered as a DC level it can be moved out of the integral, doing this and simplifying yields:
− ( An + E n ) + (2 − E ) ⋅ F (t , t1 ) t1 ≤ t < t1′ A − E ⋅ F (t , t1′ ) t1′ ≤ t < t 2 ho (t ) = p (Ap + E p ) − (2 + E ) ⋅ F (t, t 2 ) t 2 ≤ t < t 2′ − An − E ⋅ F (t , t 2′ ) t 2′ ≤ t < t 3
(2.10)
with the definition:
F (t , t x ) =
(
1 2 K1 (t − t x ) + K 2 1 − e − p (t −t x ) 2
)
(2.11)
In order to facilitate analytic solutions some simplifications need to be made. Equation (2.11) will be simplified using a Taylor series expansion of the exponential term and keeping only up to the third order term. Doing this results in: F (t , t x ) ≈
1 1 1 2 3 K 1 (t − t x ) + K 2 p (t − t x ) − K 2 p 2 (t − t x ) + K 2 p 3 (t − t x ) 2 2 6
20
(2.12)
By solving (2.10) at each of the loop-filter output boundary conditions more information about the various parameters can be extracted. The boundary conditions can be seen in Figure 2-5. The first boundary condition to be examined is: ho (t1 + t z1 ) = 0
(2.13)
which, from (2.10) and (2.12) becomes:
(2 − E )
K 2 pt z1 +
(
)
1 1 2 3 K 1 − K 2 p 2 t z1 + K 2 p 3t z1 = An + E n 2 6
(2.14)
From (2.14) it is seen that K1 can be set to K2p2 to eliminate the time squared term. Physically this means that the second order component of the slope of the low-pass filter can be cancelled out by the second order integrator if the gains are properly matched. Doing this creates transition periods that are more linear, yielding an overall higher linearity at the output. This linearity can be directly seen by examining the quantizer output vs. the quantizer input for various input levels with different values of K1. This is shown in Figure 2-6, here it is seen that the relationship is very linear for the ideal case where K1=K2p2 but quickly gains nonlinearities for deviations from the ideal.
21
Figure 2-6: Effect of Non-Ideal K1 on Linearity Substituting this definition of K1 back into (2.14) yields:
K 2 pt z1 1 +
A + En 1 2 2 p t z1 = n 6 2−E
(2.15)
The second boundary condition is: ho (t1 + t1′ ) = A p
(2.16)
which becomes:
(2 − E )K 2 pt d
1+
(
1 2 2 p 3t z1 + 3t z1t d + t d2 6
)
= Ap
(2.17)
From here it is advantageous to define the zero crossing time tz1 as the standard system delay time td plus some small error time te1. It can be shown that with
22
these substitutions all remaining non-linear terms in (2.17) are extremely small as compared to the linear terms and can thus be neglected. From the definition of E as a small error term it can also be neglected as compared to the much larger value it is added to during this time frame when the loop-filter input is dominated by the large +2 level. Equation (2.17) can then be seen to reduce to: Ap ≈ 2 K 2 p t d
(2.18)
This term is important as it implies that the loop-filter output amplitude after a transition period is constant. Conceptually this makes sense, once the quantizer changes states the system output will not change for a time of td due to the delay of the driver circuitry. During this time delay the loop-filter output continues to linearly increase. Since the output delay is fixed and constant so is the value of the loop-filter output after the system output finally switches. Similarly it can be shown that: An ≈ 2 K 2 p t d
(2.19)
The third boundary condition to be examined is given by: ho (t 2 ) = A p + E p
(2.20)
which becomes:
K 2 p (mi (t ) ⋅ Ts − t d − t z1 ) +
Ep 1 2 3 p (mi (t ) ⋅ Ts − t d + t z1 ) = 6 EA p
where mi(t) is the input duty cycle as a function of time, defined by:
23
(2.21)
mi (t ) ⋅ Ts = t 2 − t1
(2.22)
For standard linearization schemes the input signal is linearized about its zero position. If this is the case mi will be approximately 0.5 allowing the td and tz1 terms to be neglected in comparison, leaving:
K 2 p mi (t ) ⋅ Ts 1 +
Ep 1 2 2 2 p Ts ⋅ mi (t ) = 6 EA p
(2.23)
The next boundary condition of interest actually crosses from one period to the next. By allowing the next duty cycle to be different from the current, frequencies relatively close to the carrier can be accurately considered. The final boundary condition to be examined with the considerations defined above is: ho (t 3 ) = −( An + E n )
(2.24)
which becomes:
1 1 1 K 2 p ⋅ 1 − (mi (t ) + mi (t + Ts )) ⋅ Ts 1 + p 2 1 − (mi (t ) + mi (t + Ts )) ⋅ Ts 2 6 2
2
=
En An E (2.25)
Using equations (2.25) and (2.19) and the definition of tz1 allows for solving of the deviation from the ideal zero crossing time, given by:
t e1 ≈ EK 2 pt d Ts (1 − mi (t + Ts )) ⋅ 1 +
1 2 2 2 p Ts (1 − mi (t + Ts )) 6
24
(2.26)
By following similar analysis equations (2.23) and (2.18) yield:
t e 2 ≈ EK 2 pt d Ts mi (t ) ⋅ 1 +
1 2 2 2 p Ts mi (t ) 6
(2.27)
The total output duty cycle can now be defined from Figure 2.5 as: Ts ⋅ mT (t ) = (t 2 + t z 2 ) − (t1 + t z1 ) = t 2 − t1 + t e 2 − t e1 = Ts (min (t ) + me (t ))
(2.28)
where me is the deviation form the ideal input duty cycle at the output. Using (2.28) and (2.22) it is found to be:
me (t ) =
t e 2 − t e1 Ts
(2.29)
Substituting (2.26) and (2.27) into (2.29) yields:
me (t ) = EK 2 pt d mi (t ) − 1 −
1 (mi (t ) + mi (t + Ts )) + 2
1 2 2 1 3 p Ts mi (t ) − 1 − (mi (t ) + mi (t + Ts )) 6 2
3
(2.30)
By constraining this analysis to a simple single frequency sinusoidal input waveform the input modulation index takes the form: mi (t ) =
1 (1 + A sin (ω t )) 2
(2.31)
25
using (2.28), (2.30) and (2.31) the total output modulation index as a function of time becomes:
mT (t ) ≈
2 1 (1 + A sin (ω t )) + A EK 2 p 3Ts2 t d A sin (3ω t ) + 3 ω 2Ts2 sin (2ω t ) 2 96 4
(2.32)
The original purpose of the proposed loop-filter was to eliminate second order harmonics, but the preceding analysis predicts a strongly frequency dependant second order term. Figure 2-7 shows both the first and second order harmonics as a function of amplitude for two different input frequencies, from these it is seen that the second harmonic is only appreciable at very low amplitudes.
Figure 2-7: 2nd and 3rd Harmonic Comparison There is an additional problem with (2.32) in that it seemingly does not predict any frequency dependence of the third harmonic level which is something
26
that is seen experimentally [29, 36, 56], this is overcome by examining the structure of the error term that exists under standard operating conditions. Inherent System Error By examining the behavior of the proposed system in greater detail some interesting characteristics become apparent. The first step is to construct a full Fourier decomposition of the loop-filter input. This is done by assuming an ideal, constant delay of twice the standard system delay between the input and the output which is not exactly accurate but a good approximation. Using this and assuming no additional error is added at the output stage the Fourier transform is seen to be2:
u (t ) = 2 Ax sin ω x − +
Ts cos(ω x t ′) 2
8 nπ sin 2 n =1 nπ ∞
∞ k = 2 , even
+ cos
J k (β n )
nπ 2
J 0 (β n )sin (nω s t ′) sin
(
)
nω s T s 2
(
∞ k =1,odd
− nk
(
)
J k (β n ) cos ω nk− t ′ sin ω nk−
with the following definitions:
2
)
T T sin ω t ′ sin ω s + sin ω nk+ t ′ sin ω nk+ s 2 2 − nk
A full Fourier analysis is given in Appendix A
27
(
)
Ts T − cos ω nk+ t ′ sin ω nk+ s 2 2
(2.33)
u (t ) = vin (t ) − vout (t ) t ′ = t − t1′ ≈ t − t 2′
ω nk± = nω s ± kω x ω s is the PWM carrier frequency ω x is the input frequency nπAx βn = Ax
2 is the input amplitude
Jk
is the Bessel function
At first glance (2.33) appears to have no problems, it simply contains the audio information and the carrier frequency with harmonics. Upon further consideration it is realized that there should be no in-band component in this waveform due to the cancellation of the low frequency signals by the subtraction process. This means that the time delay of the output gives rise to an in-band error term, this is very problematic and will be shown to be the cause of much of the distortion seen at the output of the system even under ideal zero injected error conditions. Ideally the loop-filter output should be flat across the top and bottom with zero injected error as shown in Figure 2-8. The additional error term can be clearly seen in simulations by putting a high frequency input (20 kHz) and looking at the loop-filter output, shown in Figure 2-9.
28
Figure 2-8: Loop-Filter Output with no Inherent Error
Figure 2-9: Loop-Filter Output Showing Inherent System Error It will be shown that this new ripple will affect the output distortion in two ways, the first is in the coupling to (2.32). The new error term, consisting of the in-band component of (2.33) can now be directly inserted into to (2.32) as the injected system error, which yields:
29
mT (t ) ≈
3 ωT 1 (1 + A sin (ω t )) + A K 2 p 3Ts2 t d sin 2 48 2
3 ⋅ A sin (3ω t ) + ω 2Ts2 sin (2ω t ) 4 (2.34)
The second coupling that arises due to the additional ripple requires some knowledge about the properties of the quantizer. Quantizer Analysis Full analysis of the system quantizer is a very difficult task due to the extreme non-linearity of the device, but by investigating some of the effects of the device a better understanding can be gained. Due to the nature of the loop-filter output the quantizer will, in essence sample this trapezoidal waveform at the carrier frequency resulting in a folding of the carrier and its harmonics back down towards DC. Under ideal conditions this presents no problem as this is how the audio information is re-inserted forming the output PWM waveform. However if a cosine ripple waveform is present then this folding process will result in a mixing of frequencies which will give rise to harmonics about the input audio frequency. The most dominant carrier harmonics surround the carrier frequency and are all even order harmonics of the input added and subtracted from the carrier. When these mix with the in-band cosine function the result is only odd-harmonics with amplitudes proportional to all of the possible mixing terms. As an example the third harmonic created through this process will have an amplitude of:
H3 =
8A
π
H (ω s ) ⋅ NTF (3ω ) ⋅ K q sin
ωTs 2
J2
with:
30
Aπ Aπ R12 + J 4 R14 2 2
(2.35)
R xy = H ( xω s + yω ) ⋅ sin ( xω s + yω )
Ts T − H ( xω s − yω ) ⋅ sin ( xω s − yω ) s 2 2
(2.36)
Here the transfer functions are due to the weighting of the specific frequencies by the loop-filter and overall NTF respectively. The Kq term is the quantizer gain with respect to the system error, which can be found by comparing the DC components of a Fourier decomposition of the quantizer input and output with a small applied error signal. This gain term can be shown to be:
K q ,error =
2 K 2 pTs
(2.37)
The quantizers response to the signal path will result in a different gain simply given by the instantaneous scaling of the input to full-scale. The different gains arise due to the different ways that the quantizer processes the two types of signals. The error gain is due to the conversion of the error signal from an amplitude level to a switching time. The signal gain is simply due to the scaling of the signal to full-scale at all time. Assuming very small error and averaging over the quantizer input this gain becomes:
K q , signal =
1
(2.38)
2 K 2 pt d
This value can be tested by simulating the system with varying DC input levels and measuring the mean quantizer output divided by the mean quantizer input for each input level, this comparison is shown in Figure 2-10.
31
Figure 2-10: Comparison of Simulated and Calculated Quantizer Gain From Figure 2-10 the predicted value is seen to be adequate, with less than 2% error as a worst case. Substituting the quantizer gain terms into the NTF and STF as defined by (2.4) and (2.5) respectively yields: s 2 + ps + p 2 STF = 2t d s 3 + (2t d p + 1)s 2 + ps + p 2 NTF =
(2.39)
s 2 (s + p ) s 3 + (4 f s + p )s 2 + 4 pf s s + 4 f s p 2
(2.40)
These equations can now be used in conjunction with (2.34) and (2.35) to estimate the second and third harmonic levels seen at the output. A comparison of these levels as a function of frequency is shown in Figure 2-11.
32
Figure 2-11: Calculated Second and Third Harmonic Levels as a Function of Frequency In Figure 2-11 a simulated noise floor of -150 dB is included to illustrate how the second harmonic is typically unobservable, except at specific input amplitudes and frequencies. These harmonic levels can be seen by examining a Power Spectral Density (PSD) of the system output. If the system is subjected to a large input amplitude and large frequency the third harmonic is easily seen, this is shown in Figure 2-12. As the amplitude decreases the second harmonic becomes dominant and can be clearly seen at high input frequencies. Figure 213 shows a PSD with a large second harmonic level.
33
Figure 2-12: PSD with Large Third Harmonic
Figure 2-13: PSD with Large Second Harmonic As a test of the theoretical harmonic level defined through (2.34) and (2.35), full system simulations can be run at several input frequencies to compare the calculated third harmonic level to the simulated, this comparison is given in Figure 2-14.
34
Figure 2-14: Comparison of Calculated to Simulated Third Harmonic Level as a Function of Frequency Here the agreement between theory and simulation is seen to be very good, with only a few dB difference between the two signals through the simulated frequencies. System Stability In order to ensure a well behaved device the overall stability must be considered, this is done by re-examining (2.33). It is seen through simulations that the signal path is affected by higher order harmonics that survive through the loop filter. The worst case situation occurs at n=1 which corresponds to the PWM carrier frequency and its associated harmonics. Looking at only these terms allow (2.33) to be reduced to:
35
−8
u cf (t ) = +
J0
π
∞ k = 2 ,even
Jk
πAx 2
πAx 2
sin (ω s t ′) sin
ω s t ′s 2
[sin ((ω s − kω x )t ′) + sin ((ω s + kω x )t ′)
.
(2.41)
If any of the carrier harmonics are close to the pass-band frequency they can set up high frequency oscillations which will cause the output to switch rapidly. Looking at the possible frequencies in (2.41) that might pass through the loopfilter yields:
hk =
8
π
Jk
πA 2
sin((ω s − kω x ) t ′)
(2.42)
Equation (2.42) simply isolates the lower sideband of the harmonics surrounding the PWM carrier frequency. A condition for the minimum harmonic that exists in the pass band of the low-pass filter can be given by:
ω s − k min ⋅ ω x = p
(2.43)
with p being the pole-frequency of the low-pass filter and kmin having a worst case value of approximately 4 due to the Bessel function. The system should then remain stable as long as the pole frequency is sufficiently below the carrier frequency to adequately suppress the appropriate carrier harmonics. Figure 2-15 shows an example of a system with a low-pass filter pole that is set too high. What is seen is that the system oscillates wildly and without predictability despite a well-behaved input signal.
36
Figure 2-15: Unstable System due to Poor Placement of Low-Pass Filter Pole Maximum Input Level As an additional systems level consideration the maximum input level is examined. This parameter plays an important role in overall behavior as it sets a fundamental limit on the capabilities of the device. The maximum input amplitude actually turns out to be limited only by the system delay. A detailed view of the loop-filter input pulse train is given in Figure 2-16.
Figure 2-16: Timing Definitions for Maximum Input Calculation where m is the modulation index given by:
37
m=
A +1 2
(2.44)
From the Figure 2-16 it becomes apparent that the pulses cannot encroach upon one another if ideal operation is to be maintained, which leads to the condition: mTs + t d ≤ Ts
(2.45)
Substituting (2.44) into (2.45) yields:
A ≤ 1−
2t d Ts
(2.46)
which gives a limit to the maximum input amplitude as a function of system parameters. When this limited is exceeded the pulses begin to encroach upon one another, causing the transition period of the loop-filter output to decrease until it finally gets to the point where the output cannot cross zero, and therefore the output will not change. This situation is shown in Figure 2-17.
38
Figure 2-17: Large Amplitude Demonstration Pulse Skipping An additional consideration of this system is how much error can safely be injected without adverse effects on the output of the system output. These effects manifest themselves in either a skipping of output pulses, or by additional pulses occurring during a single input period. Both of these situations cause degradation of the audio signal with the latter actually posing a risk to the output devices. The output pulse skipping is caused when the system tries to compensate for a large injected error level and in doing so moves its pulse edges far enough apart such that the system output is unable to switch during the subsequent input period. This typically occurs under high error and high input amplitude conditions. Once the system starts missing pulses the error begins to run away, many pulses can be missed until the error returns to an acceptable level, this is illustrated in Figure 2-18.
39
Figure 2-18: Runaway Error Pulse Skipping The second type of error, output oscillations, are set up when the injected error forces the loop-filter output towards the zero crossing long before the input changes states, this causes the output to switch, since the input has not yet switched the output will quickly return to the previous state. This pattern will repeat continuously until the input changes states as shown in Figure 2-19.
Figure 2-19: Output Oscillations Due To Large Error Both situations can be avoided by simply limiting the slope of the non-transition periods of the loop-filter output. By limiting the slope the output can be 40
guaranteed to be able to return to zero within a single transition period, and also not to cross zero too long before the input. A comparison of a waveform with a limited slope to one with an unlimited slope is shown in Figure 2-20. From this it is seen that the unlimited slope allows the system to reach an amplitude where it cannot pass the zero crossing point before the input changes back.
Figure 2-20: Demonstration of Limited and Unlimited Slope The output of the unlimited system in Figure 2-20 will not change states and will continue to staircase up until the error comes back down similar to what is seen in Figure 2-18. In calculating the maximum slope the absolute maximum allowed input amplitudes, the time delay of the output stage and PWM sample frequencies are used as found in (2.46). The calculation begins with a simple y=mx+b type of relationship. In the worst case scenario the input amplitude will be equal to the maximum given by (2.46), then the loop-filter output must be able to get back to the zero axis before the input changes states again. This means that with the constant slope of 2K2p during the transition time the output has a total time of 2td to get from the current value to zero, this gives: 0 = S tran ⋅ t min + A p + E p ,max
(2.47)
41
where Stran is the slope of the transition period, tmin is the minimum amount of time the system has to change states, Ap is defined by (2.18) and Ep,max is the maximum value of Ep that will allow the system to change states. Putting in the values described above yields: 0 = (− 2 K 2 p ) ⋅ (2t d ) + 2 K 2 pt d + E p , max
(2.48)
rearranging yields: E p ,max = 2 K 2 pt d
(2.49)
In order to stay less than this maximum error value the slope has to be limited, the maximum slope can be found using: E max = S max ⋅ t max
(2.50)
where Smax is the maximum allowable slope and tmax is the maximum amount of time between edges of the maximum duty cycle. This time is equivalent to the sample period minus the tmin term from (2.47). Putting these values into (2.50) yields:
S max =
2 K 2 pt d Ts − 2t d
(2.51)
Limiting the slope of the trapezoidal waveform essentially limits the correction per period that is possible by the loop. Any additional error, which would correspond to additional slope, will be passed through the loop un-attenuated. While this is not ideal it does prevent the system output from becoming unstable and keep the output stage from destroying itself through additional pulses being inserted in a 42
short time period. An example of the system running with an input amplitude of 0.5 and high levels of injected DC output error (30%) with and without slope limiting is shown in Figure 2-21, the figure shows the system output after being passed through a low-pass filter to extract the audio content. The slope unlimited system shows obvious glitches in the output waveform due to output pulse problems, while the slope limited system shows a clean output with no visible glitches.
Figure 2-21: System Output with High Error with and without Slope Limiting Comparison to Previous Architecture The performance of this design is centered mainly around the loop-filter topology. The loop-filter that is currently most widely used in feedback type output stages consists of a second-order integrator in parallel with a first-order integrator [56] shown in Figure 2-22.
43
Figure 2-22: Previous Loop-Filter Architecture By using a similar linear analysis as that used in Section 2.1.1 the NTF and STF for this system can be shown to be:
STF =
s+K 2t d s 2 + s + k
(2.52)
NTF =
2t d s 2 2t d s 2 + s + K
(2.53)
By appropriately selecting parameters for both systems the STF and NTF can be matched very nicely, as shown in Figure 2-23.
Figure 2-23: NTF and STF of Both Systems with Comparable Parameters
44
From Figure 2-23 the advantages of the proposed system are not immediately clear, to understand the advantages the linearity of the quantizer must be examined. Figure 2-24 shows the quantizer output vs. the input for both the previous and proposed loop-filters.
Figure 2-24: Loop-Filter Linearity Comparison From this figure it is clear that the previous system causes the gain of the quantizer to be highly non-linear, while the proposed system is extremely linear. This can be further seen by examining the third harmonic level as a function of frequency for both systems, this is shown in Figure 2-25. Here it is seen that the third harmonic levels are much lower for the proposed system than those of the current one.
45
Figure 2-25: Third Harmonic vs. Frequency Comparison Converter Stage The PCM to PWM converter topology consists of a standard PCM-PWM converter block with an additional feed-forward path as shown in Figure 2-26. This section will discuss the theory behind the inclusion of an additional feedforward path in order to suppress the jitter that couples to the audio band through the PCM to PWM conversion process.
Figure 2-26: PCM-PWM converter Architecture
46
PCM-PWM Conversion In standard converter topologies the PCM signal is compared to a digital reference waveform generated either internally or externally. As mentioned previously, to facilitate low-error correction through the conversion process the reference should have as many possible levels as the reference. If this is not the case then the output PWM waveform will be limited in resolution to the lowest resolution of the two waveforms being compared. Thus any additional bits in the reference waveform as compared to the input will be wasted, while any fewer will result in additional quantization noise. Standard converters typically utilize a 7-bit reference waveform with the PWM sample frequency being around 380 kHz. In this manner a 100 MHz resolution is obtained at the PWM signal, Chapter 5 discusses a possible way to increase this resolution without having to raise the clock frequency. Feed-Forward Loop The proposed feed-forward loop consists of three main components, two analog loop-filters and a digital sigma-delta converter. The digital converter is required to reduce the number of bits from 7 down to 1 to allow for a direct comparison to the PWM waveform. The sigma-delta is chosen due to the shaping of the introduced quantization noise out of the base-band and into much higher frequencies where it will not affect the system. The loop-filters will be discussed in more detail in the following section but are, in general, simple analog filters that allow for selection of frequencies to pass to the output stage. System Theory From figure 2-26 it can be shown that the output with the proposed feedforward loop is given by:
Y (s ) = X (s ) ⋅ (1 − H 2 (s ) + H 1 (s )) + E1 (s ) ⋅ (1 − H 2 ) + E 2 (s ) ⋅ H 1 (s )
47
(2.54)
From (2.54) it is seen that setting H2 equal to H1 provides for direct transmission of the input to the output, using this yields: Y (s ) = X (s ) + E1 (s ) ⋅ (1 − H ff (s )) + E 2 (s ) ⋅ H ff (s )
(2.55)
where: H 1 (s ) = H 2 (s ) = H ff (s )
(2.56)
Some insight into what Hff(s) should be can be gained by examining the properties of E1 and E2. Due to the noise shaping properties of the sigma-delta converter E2 should be fairly small at low frequencies and should increase at higher frequencies. E1 is assumed to be due primarily to the clock jitter coupling to the amplitude through the PCM-PWM conversion block. Under these circumstances the values of E1 that are of concern will be in the audio-band due to the conversion from the time domain to the amplitude domain through the PCM-PWM conversion block. Thus if Hff(s) is a low-pass filter E2, whose power is mainly at high frequencies, will be further reduced and E1 will be weighted by one minus a low-pass which can be designed to be a high-pass filter. This reduces the in-band component of the jitter error coupled to the signal. To show this suppression a simulated jitter signal can be included in the conversion system simulations. This jitter signal is created using the blocks shown in Figure 2-27.
48
Figure 2-27: Jitter Simulation Scheme in SIMULINK This system allows for altering the slope of the zero crossing time of the PWM reference waveform by having the random multiplicative and additive errors sampled at half of the PWM sample frequency corresponding to each side of the triangle reference wave. Using this model a full PCM-PWM conversion simulation can be run with and without the feed-forward loop enabled. These simulations, along with an error free simulation are shown in Figure 2-28.
49
Figure 2-28: Comparison of PCM-PWM Converter PSD with and without Jitter Correction The simulations of the system show that the added clock error signal is not only removed, but the error generated through the conversion process is also reduced. This allows the proposed architecture to be extended to allow for relaxed design requirements through the conversion stage with little effect on overall performance.
50
Nonlinear Error Rejection As mentioned above the output stage will suppress errors regardless of whether they are applied at the input or the output. This can be understood through the realization that the input to the loop filter is the difference between the input and the output, with the input assumed to be a standard full amplitude PWM waveform. Thus if the output amplitude is too large the reference will be a lower value due to the subtraction. This is also the case if the input amplitude is too low, thus due to the absolute scaling of the quantizer to ±1 the system loses the ability to distinguish between errors added at the input from those added at the output. The system then tries to correct any error whether it originates from deviations from ideal output or from ideal input. Choosing System Parameters Using the theory developed in the preceding sections a set of system parameters can be chosen to produce the desired system behavior. Table 2-1 provides a summary of the parameters chosen for the output stage. Table 2-1: Output Stage Parameter Summary Parameter
Value
K2
1 (0 dB)
p
2π ⋅ 50 kHz
K1
9.87 × 1010 (220 dB)
Using these parameters a bode plot for the second-order integrator, low-pass filter and total loop-filter is given in Figure 2-29, the STF and NTF are shown in Figure 2-30.
51
Figure 2-29: Bode-Plot of Second-Order Integrator, Low-Pass Filter, and Total Loop-Filter
Figure 2-30: Bode-Plot of Output-Stage NTF and STF
52
For the conversion stage the parameters are summarized in Table 2-2, and should provide for a good test condition for the feed-forward loop. Table 2-2: Conversion Stage Properties Parameter
Value
PWM Carrier Frequency
384 kHz
PCM-PWM input bits
7
FF Loop-Filter Order
1
System Design Conclusion The design conditions have been laid out and parameters have been chosen to provide for a robust system capable of providing performance equal to or better than current system implementations. In the next chapter the design and layout of the actual device will be discussed and finally results from the fabricated device will be shown. The circuit level design is done such that the results come as close as possible to the results listed through this chapter to ensure good behavior of the system.
53
CHAPTER III CIRCUIT LEVEL DESIGN In this chapter many of the details that went into the actual design of the integrated circuit for the proposed system will be addressed. The starting point for the circuit level design is the systems level analysis described in Chapter 2. All of the schematics and layouts discussed in this section are included in Appendix B for reference. The discussion of the design will begin by examining some of the general considerations for the entire system, then the conversion stage will be examined and finally the design of the output stage will be discussed. Integrated Circuit Overview The Class-D amplifier integrated circuit was designed with full testability in mind. With regard to this many additional input and output pins were used to facilitate additional testing capabilities through specific component isolation as well as signal injection and testing. The fabrication process selected was the Taiwan Semiconductor Manufacturing Company (TSMC) [53] 0.25 micron process which allows for five metal layers and a native metal to metal thin film capacitor device. This process contains small high-speed digital devices and good analog FET operation. The transistors used are 2.5V devices with symmetric n-type and p-type gate threshold voltages. The actual design of the device was accomplished using the CADENCE design environment [7] with verification done using SPECTRE with design models provided by TSMC through the MOSIS foundry [27]. Due to the complex nature and large size of the digital sigma-delta converter required to convert from the 16-bits of standard CD audio down to the required 7-bits of the PCM-PWM converter input this component was omitted from the design. Instead the converted 7-bit audio signal is provided to the device at a frequency of 705 kHz found by assuming an OSR of 16 multiplied
54
by the 44.1 kHz of the standard audio. A block diagram of the system with additional testing capabilities is shown in Figure 3-1.
Figure 3-1: System Block Diagram It is seen from Figure 3-1 that the input to the Class-D output stage can either be the converted PWM signal from the conversion stage or a PWM signal that is directly put into the chip from an external source. In this manner the output stage can be isolated from the converter allowing for detailed testing and error analysis. For the system a signed binary format was chosen with 1000000b being the zero value. A list of codes and their associated values is given in Table 3-1 using only 3-bits for reference. Table 3-1: Example Binary Coding Scheme Binary Code
Value
111
+3
110
+2
101
+1
100
0
011
-1
010
-2
55
001
-3
000
-4
From this example it is seen that there is one more possible negative value than positive value. To solve this problem the lowest possible value (all-0’s) is eliminated from possibility allowing for symmetric coding about the zero value. Design Simulation Many simulations were done to verify the design of the schematics, in many cases full transient simulates can take anywhere from several hours to several days to complete. In order to facilitate faster verification VerilogA [7] models are used. VerilogA allows for fast simulation and algorithm verification as compared to the slower full schematic transient simulations. The VerilogA code for the system is included in Appendix C for reference. Throughout the next sections many simulations results will be provided using both VerilogA and standard transient simulations. Certain VerilogA models are required for easy analysis of schematic results, these include simple analog to digital and digital to analog converters. These are implemented in order to examine the signals generated within the digital blocks easily without having to examine every signal within the multi-bit busses. These were also used to create input signals simply by using analog sources then converting that into a digital signal with the correct number of bits for the system. PCM-PWM Conversion Stage Design The majority of the PCM-PWM conversion stage design was digital in nature with only a few analog components which exist in the experimental feedforward path. Standard digital block libraries were not available through the MOSIS foundry for the process selected so cells were created from scratch.
56
Each major portion of the conversion stage will be addressed with simulations provided to verify functionality. PCM-PWM converter The most important component of this portion of the system is the actual PCM to PWM conversion block. This device consists of a digital comparator, updown counter to generate the digital triangle wave reference, and various flipflops for synchronization and glitch reduction. Before the design of the individual components is examined it is useful to look at a VerilogA simulation to verify the chosen conversion algorithm. Since VerilogA is a behavioral simulation language the specific internal components need not be specified, only the overall functionality. Using the full PCM-PWM converter model, found in Appendix C, in a transient simulation results in the PWM waveform found in Figure 3-2. The resultant PWM waveform is exactly what is expected, with the duty cycle correctly representing the applied DC input of 0.
Figure 3-2: Output of PCM-PWM converter using VerilogA The first portion of the converter block to examine is the digital comparator which generates the actual PWM output by comparing the generated triangle waveform to the applied PCM signal. The digital comparator was implemented 57
by subtracting the two input signals from one another using a two’s complement binary addition scheme. The two’s complement is generated by inverting the signal to be subtracted and adding it to 0000001b. The carry from the final addition as well as from the addition stage of the two’s complement generation are combined using a NOR gate with the result being used as the comparison output. As an example two 4-bit signals can be compared using the subtraction method described above. The two numbers to be compared are 1001 (+1) and 0111 (-1), using the same coding scheme as the system shown in Table 3-1. The arithmetic then becomes: 1001 − 0111
1001 +
1001 (1)0010
(3.1)
Which has a carry bit meaning that the output is 0 after the NOR, corresponding to less than. If the numbers are compared in the opposite order the equation becomes. 0111 − 1001
0111 +
0111 (0)1110
(3.2)
This time the output is 1, corresponding to a greater than. The second input to the NOR gate takes care of values that overflow the two’s complement generation structure. This can be shown to work for all values allowed at the input of the comparator. To test the digital comparator component block a DC input is applied to a VerilogA A/D converter on one input terminal. The other input is a triangle reference waveform of the same frequency as that of the real system (384 KHz). The simulated input waveforms along with the output of the comparator are shown in Figure 3-3. The output of the system can be seen to contain glitches at specific points, this is not troubling due to the latching scheme 58
that is used at the output of this stage resulting in a clean output waveform with no glitches.
Figure 3-3: Digital Comparator Simulation The second portion of the PCM-PWM converter to be examined is the updown counter which generates the triangle reference waveform, a block diagram of the structure used is shown in Figure 3-4. The heart of this device is a simple digital adder which will be discussed later in this chapter. At a system reset the input to the adder is forced to 0000001b, which is the lowest possible value. It is then added to 1000001b causing a single bit increment at each clock edge due to the latching feedback structure. When the output gets to 1111111b, which is the highest possible value, the system reacts by changing the signal to be added to 0111111b causing a single bit decrement at each clock edge. Similarly when the output returns to 0000001b the addition reverts to 10000001b. This pattern continues until a reset is detected allowing for a full triangle wave. This system is tested by running it for a full sample period, examining the output using a VerilogA model of a D/A converter to convert the output from 7-bits to an analog level for easier visualization. The output is shown in Figure 3-5, again glitches 59
are present due to the operation of the ripple carry adder. The glitches are not of importance due to the latching that is done within the circuitry.
Figure 3-4: Block Diagram of Reference Generation Circuit
Figure 3-5: Triangle Reference Generator Output Finally a full simulation of the PCM-PWM converter schematic is done for verification. Both components described above are used together for the full simulation. Again a VerilogA model of an A/D converter is used to convert the 60
input analog signal to a digital level. The pertinent waveforms are shown in Figure 3-6.
Figure 3-6: PCM-PWM Converter Output It is seen from Figure 3-6 that the output switches states at the exact time that the reference rises above the input level, which is what is expected. Here the output is taken after an additional flip-flop removing the glitches in the output seen in Figure 3-3. Digital Sigma-Delta Converter The proposed feed-forward path within the conversion stage requires the addition of the converted PWM signal to the 7-bit modified PCM signal. Since this is not directly possible the modified PCM signal is first passed through a digital sigma-delta converter to lower the number of bits to one to allow for a direct comparison. A block diagram of the digital sigma-delta converter topology used is shown in Figure 3-7.
61
Figure 3-7: Digital 7-bit to 1-bit Sigma-Delta Converter Topology When analyzing a sigma-delta converter the error is assumed to come entirely from the quantization process. The transfer function of a digital integrator in the z-domain is given as:
H int ( z ) =
z −1 1 − z −1
(3.3)
which makes the overall system transfer function of the system:
(
)
Y ( z ) = X ( z )z −2 + 1 − z −1 E ( z ) 2
(3.4)
From equation (3.4) it is seen that the input is simply delayed by two cycles while the error due to quantization is weighted by a squared term. The error weight actually greatly suppresses the low-frequency errors while amplifying the high frequency errors. This can be seen when the meaning of the term is considered, the current error is subtracted from the previous error. If the error has not changed significantly (slow moving, low frequency) then this weighting term will be very low. However if a large change has occurred, such that the system has managed to change signs, then the weighting term is actually greater than one causing amplification of the error. This is not troubling as the frequencies that 62
are amplified are very high in frequency and will not affect the system. For a more detailed analysis of sigma-delta converters in all shapes and forms the user is directed to “Oversampling Delta-Sigma Data Converters: Theory, Design, and Simulation,” by Candy and Temes. The converter used in the proposed system uses 9 internal bits to allow for minimum error due to scaling, integration and addition by allowing additional headroom. Again a good check is to test the algorithm against a VerilogA model. The full VerilogA model used is comprised of the individual component blocks that make up the schematic model. By using the same set of components for both models a single schematic block can be tested at a time by inserting it in the overall VerilogA model allowing for higher testing speed. The first stage in the digital sigma-delta converter topology is to convert the input from 7 to 9-bits, the additional two bits are placed between the MSB and the second input bit and are set to the inverse of the MSB to properly bias the signal. Once this is done the signal is added to the feedback signal using a modified ripple-carry adder with additional circuitry to ensure that overflow or wrap-around does not occur. Special care must be taken to ensure the proper handling of positive and negative number about the zero level (1000000b). This was accomplished by first adding the two signals together with a standard ripple-carry adder then negating the MSB by adding it to a binary 1 to get the output biasing correct. To stop overflow the carry bit of the ripple-adder and the carry bit of the MSB negation are monitored. If only one of the two bits is high the result must be ‘locked’ to either the maximum or minimum allowable values depending on values of the inputs. A block diagram of this system is shown in Figure 3-8.
63
Figure 3-8: Block-Diagram of Digital Adder with Overflow Protection Two examples can be examined to help understand the functionality, first a small positive number is added to a smaller negative number both being only 4-bits for simplicity:
+
1010
2
0111 (1)0001
+ −1 −7
(3.5)
This is not correct due to the overflow bit not being counted in the sum. To fix this the MSB simply needs to be negated, or an additional sum of: 0001 +
1000 (0)1001
(3.6)
This number corresponds to +1, which is correct. Since the carry bits are different in the two addition stages no additional action is required. The second example is a large positive number added to another large positive number:
64
+
1101
5
1100 (1)1001
+ 4 1
(3.7)
This is again not correct, renormalizing as in the previous example yields: 1001 +
1000 (1)0001
(3.8)
While this is still not correct both the addition stages resulted in a carry bit alerting the system that the output must be locked. The carry bit of the first stage tells which value the output should be locked to, in this case since it is a binary 1 the output should be locked to 1111b (+7). The system is tested by adding a DC signal to a triangle wave similar to that used in the PCM-PWM converter tests. The results of the simulation are shown in Figure 3-9.
Figure 3-9: Input and Output Waveforms of Digital Adder VerilogA
65
What is seen is that the two input signals, the triangle wave and DC level, are added correctly and when the sum exceeds the maximum allowed level it saturates as opposed to wrapping around. The same inputs can be applied to the schematic, this is shown in Figure 3-10.
Figure 3-10: Input and Output Waveforms of Digital Adder Schematic Again the outputs are seen to be correct, they directly match what is seen in the VerilogA simulation shown in Figure 3-9. After the digital adder the signal is put into a digital integrator consisting of an additional digital adder, delay element and a buffer to improve the drive capabilities through the device. The integrator is set up to add the input signal and the delayed version of the sum, which is also the output. This allows for a direct implementation of (3.3). This system is tested by putting in a ramp function and examining the output. These waveforms are given in Figure 3-11 using VerilogA models of the blocks.
66
Figure 3-11: Input and Output Waveforms of Digital Integrator VerilogA It is seen that after the input becomes positive the output begins the squared relationship characteristic to integrators with ramp inputs. The output of the schematic with the same input is shown in Figure 3-12. Here the output is seen to be very similar to that of the VerilogA model.
Figure 3-12: Input and Output Waveforms of Digital Integrator Schematic 67
After the integrator stage the signal is added to a feedback signal that has been multiplied by two. The multiplication is accomplished via a simple bit shift, filling in the LSB to appropriately bias the signal toward zero. Precautions must again be taken to ensure that the signal will not overflow. A locking system similar to that of the digital adder is used here to serve the purpose of saturation. This stage is verified using a simple sinusoidal input, the input and output waveforms using the VerilogA model are given in Figure 3-13. What can be seen in the simulation is that when the multiplication should result in a value higher than the maximum or lower than the minimum the system locks the value to prevent erroneous outputs due to overflow.
Figure 3-13: Multiply by 2 Simulation VerilogA Figure 3-13 shows the output is approximately double that of the input, as expected. The results of the full schematic are shown in Figure 3-14. The schematic version of the multiplication behaves identically to that of the VerilogA model with the exceptions of the glitches at the clock edges due to the settling in the ripple carry adder. 68
Figure 3-14: Multiply by 2 Simulation Schematic The final portions of the digital sigma-delta converter involve the quantization of the 9-bit signal to 1-bit and the rescaling back to 9-bits from 1-bit for the feedback path. Both operations are simple, in the quantization only the MSB is passed through, and in the re-scaling all bits are set to the value of the 1bit quantized signal. The full digital sigma-delta system can now be tested to verify the overall performance. Figure 3-15 shows the output using the VerilogA model, here the system input was 0, the output average is approximately 0 meaning that the conversion is correct. Figure 3-16 shows the output using the full schematic model, with the same input the output is still approximately 0. The full integrated circuit was designed such that the output of this sigma-delta converter can be directly measured allowing for testing of the integrated device directly. The verification process used to test the digital sigma-delta converter is described in Chapter 4.
69
Figure 3-15: Full Sigma-Delta Output VerilogA
Figure 3-16: Full Sigma-Delta Output Schematic Feed-Forward Components An important component of the feed-forward loop is the analog loop-filter used to extract the error within the audio-band caused by jitter, conversion error and other non-idealities. As described in Chapter 2 the loop-filter used here is a 70
simple first-order RC filter for ease of implementation. The pole value of the filter was selected such that a good suppression can be obtained using this feedforward loop. In order to put the error signal back onto the PWM waveform an analog adder is required. The adder is designed using a high-gain foldedcascode op-amp that will be described in Section 3.4.1 along with several resistors to create a standard adder structure as seen in Figure 3-17.
Figure 3-17: Analog Adder Schematic In order to keep the feed through of the signals from one signal to the other the input resistances need to be kept high, but if they get too large the rise and fall time of the PWM waveform is affected. The adder is tested by putting in two sine waves with different amplitudes and frequencies and measuring the output. The results of the schematic simulation as well as the VerilogA model are shown in Figure 3-18.
71
Figure 3-18: Ideal and Real Output of Analog Adder Here it is seen that the schematic output contains some error due to a non-ideal gain through the stage. The small value of the error will not cause problems due to the nature of the inputs at this stage. Output Stage Design The output stage was designed to simply simulate a high-power output stage. The output devices themselves are not capable of handling large amounts of current, nor can they take more than 2.5 Volts resulting in a very low power operation. Several stages were included to help simulate the delay that would come from the driver circuitry required to make the high-power device switch. The ability to have an external high-power system was included by including a path for an external feedback signal to be put into the device. In this manner a high-power output stage with all required driver circuitry could be included off-chip with the output of the chip acting as the control signal. The output of the high-power devices can be put back into the loop to test any nonideal affects that arise.
72
Loop-Filter The heart of the output stage is the loop-filter developed in Chapter 2. It is this component that gives rise to all of the enhanced performance of the system, therefore special attention was paid in the design of the components contained within it. Since most of the output stage is analog circuitry the basic building block is the operational-amplifier or op-amp. Two designs were created for this device, a folded-cascode device for large gains and a simple single-ended differential pair for lower gain operation. The structure of the folded cascode device is shown in Figure 3-19.
Figure 3-19: Folded-Cascode Topology Design of the Op-Amp begins with the familiar current equation for an MOS device in saturation, given by [55, 60]:
ID =
W 1 (VGS − VT )2 K′ 2 L
(3.9)
Rearranging (3.9) allows for solving of the W/L ratio for each device based on the parameters of the system. Doing this for each device in Figure 3-19 yields:
73
W L W L W L W L W L W L
2 ⋅ 1 × 10 −6
=
166 × 10 −6 (0.2 )
1, 2
= 3, 4
= 5,6
166 × 10 −6 (0.1)
= =
(3.10)
2
= 11.7
(3.11)
2
= 11.7
(3.12)
2 ⋅ 10 × 10 −6
166 × 10 −6 (0.1)
=
11
= 0.33
2 ⋅ 10 × 10 −6
7 ,8
9 ,10
2
2 ⋅ 10 × 10 −6
49 × 10 − 6 (0.1)
2
= 37.4
(3.13)
2
= 20
(3.14)
2
=6
(3.15)
2 ⋅ 11 × 10 −6
49 × 10 − 6 (0.15) 2 ⋅ 2 × 10 −6
166 × 10 − 6 (0.06 )
The values of the length and width may seem arbitrary as long as the ratio is correct, but the DC gain of the system is given by [40]:
A V = g m 1 {[g m 7 ro 7 (ro 1 ro 9 )] [g m 5 ro 5 ro 3 ]}
(3.16)
where:
g mx = K ′
W L
(VGS − VT )
(3.17)
x
and:
rox =
1 1 W K′ 2 L
(VGS − VT )
≈ 2
⋅λ
1 L ∝ λI D I D
(3.18)
x
74
This means that the gain of the system is proportional to the length of the devices. To this end the devices are made long enough to allow for a decent gain through the stage (~60dB). This is not an unlimited process as the length will affect many other parameters within the system [55, 60]. The values of W and L of the common mode feedback (CMFB) circuitry can be found by realizing that the common mode rejection ratio (CMRR) will be improved by making the gain of the CMFB as high as possible. The gain of the CMFB is based upon the resistance of the M12 and M13 devices, which are not in saturation to allow them to act as voltage controlled resistors. The resistances of these two devices are given by [46, 52]:
R12,13 =
1
(3.19)
W K′ (Vo − VT ) L
From this, values can be picked based on the desired performance of the device. Table 3-2 summarizes the values of the length and width for all of the devices in the folded-cascode architecture. Table 3-2: Device Size Summary for Folded-Cascode Op-Amp Device
Width
Length
M1,2
1 µm
3.1 µm
M3,4
11.2 µm
0.96 µm
M5,6
11.2 µm
0.96 µm
M7,8
35.9 µm
0.96 µm
M9,10
19.4 µm
0.96 µm
M11,15
1.43 µm
0.24 µm
M12,13
2 µm
12 µm
75
The bias voltages to make the op-amp perform as designed, by forcing the FET devices to operate in the saturation region can be found using the relationship: Vds ≥ V gs − VT
(3.20)
where Vgs-VT is often referred to as the overdrive voltage VOD. Going through the amplifier each required bias voltage limit can be found as: Vb1 ≥ VOD11 + VTN + I D RT = 0.06 + 0.35 + 0.005 = 0.415
(3.21)
Vb 2 ≥ VOD 3 + VTN = 0.1 + 0.55 = 0.65
(3.22)
Vb 3 ≥ VOD 5 + VTN + V DS 3,min = 0.1 + 0.55 + 0.1 = 0.75
(3.23)
Vb 4 ≤ V DD − (VOD 7 + VTP + V DS 9, min ) = 2.5 − 0.1 − 0.53 − 0.1 = 1.77
(3.24)
Vb 5 ≤ V DD − (VOD 9 + VTP ) = 2.5 − 0.15 − 0.53 = 1.82
(3.25)
Using these relationships the final bias voltages are given in Table 3-3. Table 3-3: Folded-Cascode Op-Amp Bias Voltages Vb1 0.45V Vb2 0.9V Vb3 1.25V Vb4 1.75V Vb5 1.9V To further ensure the performance of the device, the noise generated within it can be examined. The total noise in a folded-cascode op-amp can be shown to be [40]:
2K N 2 K N g m2 3 2 K P g m2 9 2 2 g m 9 2 g m3 v = 8kT + + + + + (3.26) (WL )1 C ox f (WL )3 Cox fg m2 1 (WL )9 Cox fg m2 1 3 g m1 3 g m2 1 3 g m2 1 2 n
76
Substituting the values of the system results in:
v n2 = 1.262 × 10 −16 +
6.536 × 10 −14 f
(3.27)
The total noise will be the sum of this over the appropriate frequencies. For this analysis the audio band is the region of interest, resulting in:
v n2 = 1.262 × 10 −16 + 6.536 × 10 −14
20000 20
1 df = 4.52 × 10 −13 V 2 f
(3.28)
This value is very low and is well within reason for our device. Using the values calculated above the device can be simulated to ensure proper performance. Figure 3-20 shows a Bode Plot for the folded-cascode op-amp with a standard differential input, Figure 3-21 has a common mode input to illustrate the CMRR of the system.
Figure 3-20: Bode Plot of Folded-Cascode Op-Amp with Differential Input 77
Figure 3-21: Bode Plot of Folded-Cascode Op-Amp with Common Mode Input From these figures it is seen that the device performs very nicely. The DC gain of the folded-cascode op-amp comes out to around 65dB which is adequate for the requirements of the system. The response to a common mode signal is around -9dB which puts the CMRR at approximately 70dB, this is a very good value for such a simple device. Next a pulse train can be applied to the system to test the slew rate, this is shown in Figure 3-22.
Figure 3-22: Input and Output of Folded-Cascode Op-Amp with Large Pulse Inputs 78
This performance is not particularly good corresponding to current starvation at large amplitudes [40]. This is not overly troubling as this device was not meant to be used in large amplitude operating regimes. The second op-amp designed was a low gain high bandwidth singleended simple differential pair. A similar analysis can be followed to determine the device sizes for the single-ended op-amp used as shown in Figure 3-23. For a single-ended output a common-mode feedback stage is not required [40].
Figure 3-23: Single-Ended Op-Amp Schematic Going around the architecture the device size ratios are found to be: W L W L W L
= 1, 2
= 3, 4
= 5
2 ⋅ 20 × 10 −6
166 × 10 − 6 (0.075) 2 ⋅ 20 × 10 −6
49 × 10 −6 (0.25)
= 41.7
(3.29)
= 19.4
2
2 ⋅ 40 × 10 −6
166 × 10 −6 (0.075)
2
2
(3.30)
= 41.7
(3.31)
The lengths and widths of the devices are summarized in Table 3-4. 79
Table 3-4: Device Sizes for Single-Ended Differential Pair Op-Amp Device
Width
Length
M1,2
10 µm
0.24 µm
M3,4
4.65 µm
0.24 µm
M5
10 µm
0.24 µm
With these sizes the required bias voltage limit can be found to be: Vb1 ≥ VOD 5 + VTN = 0.075 + 0.3 = 0.375
(3.32)
Using these values a good gain is achieved over a very broad set of frequencies. The bode plots of the system with differential inputs and common-mode inputs are shown in Figures 3-24 and 3-25 respectively. From these the DC gain is seen to be around 31dB and the CMRR is about 45dB. The response to a large input signal is much better than the folded-cascode device and is shown in Figure 3-26.
Figure 3-24: Bode Plot of Single Ended Op-Amp with Differential Inputs 80
Figure 3-25: Bode Plot of Single Ended Op-Amp with Common-Mode Inputs
Figure 3-26: Single-Ended Amplifier Transient Response to a Pulse Input In order to properly bias the op-amps a series of bandgap references are used. The bandgap reference is used due to its resilience to changes in temperature [22, 40, 49, 60]. These devices were tuned to allow for minimum temperature effect using the temperature coefficients of the MOS devices, 81
resistors and BJT devices. Figure 3-27 shows the various created voltages with a temperature sweep to demonstrate how little the voltages change over the temperature sweep.
Figure 3-27: Bias Output Voltages vs. Temperature Once the op-amp has been designed it must be used in some fashion. The first block to design is the integrator, this component is relatively simple except for the addition of the slope limiting functionality as described in Chapter 2. In this first attempt at an error limiting circuit a simple approach of monitoring the voltages at specific points and adjusting the gain of the integrators was used. Figure 3-28 shows the expected non-ideal integrator output as simulated in SIMULINK.
Figure 3-28: Non-Ideal Integrator Output Using SIMULINK 82
What can be seen is that the slope on the top and bottom of the output are both heading toward the zero-crossing axis. This is characteristic of very low levels of error being put into the loop, corresponding to non-idealities within the schematic. Figure 3-29 shows the actual simulated integrator input and output. Again the slopes are both heading toward the zero-crossing axis with additional jumps during the transition times corresponding to schematic non-idealities.
Figure 3-29: Integrator Schematic Input and Output To implement the error saturation a bypass path is added to the integrator. When the error gets too high and pulse skipping is likely a conductive path through the integrator stages is provided and the capacitors are reset by connecting both ends to analog ground. The input and output waveforms with this resistive path engaged are shown in Figure 3-30.
83
Figure 3-30: Integrator Input and Output when Bypass Devices are Engaged For the purpose of stability the second integrator stage consists of only a passive RC filter with no active amplification. The RC pole is set low to emulate a pure integrator at medium frequencies. The transient response of this passive RC implementation is shown in Figure 3-31.
Figure 3-31: Second Integrator Stage Response 84
Again a bypass stage is added to allow for pulse-skipping prevention. A transient simulation with this path engaged is shown in Figure 3-32.
Figure 3-32: Second Integrator Stage Response with Resistive Path Engaged The second branch of the loop-filter is a simple low-pass filter with no bypass paths. This component is an active device using the folded-cascode opamp. The filter is implemented as an active gain followed by a passive low-pass filter. The transient response of this stage is shown in Figure 3-33.
85
Figure 3-33: Low-Pass Filter Output The output of the low-pass filter and the second order integrator need to be combined and passed through a quantizer. These two steps are done simultaneously by the comparator device to speed up the response of the loopfilter. The addition is done through two single-ended analog adder circuits. The adders work by adding the positive side signal of one loop-filter branch to the negative side signal of the second branch resulting in a subtraction. The result is amplified through the use of a larger feedback resistor in the analog adder circuit. By subtracting the two signals a comparison is actually being made, in that if the positive side signal is larger the output will be closer to VDD while if the negative side is larger the output will be closer to ground. The outputs of these adders are then put into a low drive strength latch and finally into a high drive latch for a hysteresis effect to prevent multiple latchings due to noise. Figures 3-34 and 335 show the comparator simulations with two different DC levels compared against a sine wave to demonstrate the operation of the device.
86
Figure 3-34: Comparator Simulation with DC=0
Figure 3-35: Comparator Simulation with DC=-0.5 A small delay is seen from the time when the amplitudes cross one another to when the output switches stages. This delay is due to the finite drive of the opamps when trying to change the state of the first latch, overall this is acceptable. 87
Output Devices To simulate the delay of high-power output device a pad-driver architecture was used. The driver consists of three stages of incrementally larger device sizes following the well-known logarithmic per stage size increase of [50]:
α N = ln
CL Cin
(3.33)
with an assumed load of 100pF and an input capacitance of 600aF. Using three stages causes the calculated scaling factor to be 2.3. Using a slightly large scaling factor of 2.57 and applying a 10 MHz input pulse train results in the waveforms shown in Figure 3-36. By allowing for slightly large devices the performance can be improved. Figure 3-37 shows the response to the same stimulus with a scaling factor of 4.
Figure 3-36: Pad-Buffer Input and Output (alpha=2.57)
88
Figure 3-37: Input and Output Waveforms for Final Pad-Buffer (alpha=4) Full Output-Stage Simulations Using all of the output-stage components from the preceding sections the full output-stage schematic can be simulated. Simple transient simulations were used with sources to allow for injection of error in both the common mode and differential configurations. Figure 3-38 shows the input and output with no injected error at the output. From this it is seen that the input and output duty cycles are very similar with a constant delay as would be expected.
89
Figure 3-38: Output Stage Ideal Input and Output To test the error suppression capabilities of the system a small amount of DC error can be injected at the output. Figure 3-39 shows the input and output waveforms, this time with an injected DC error level at the output. It is seen that the duty cycles are now different corresponding to a compensation of the output by the system.
Figure 3-39: Output Stage Simulation with Simulated Injected Error
90
Large amounts of injected error can be simulated to test for the effects of pulseskipping as described in Chapter 2. Figure 3-40 shows the input and output waveforms with large amounts of injected error at the output. The rapid oscillations in this figure are extremely bad for the output stage and need to be dealt with.
Figure 3-40: Output Stage with Large Simulated Injected Error Error Detector In a first attempt to limit the amount of error that the output stage can correct, an error sensing circuit was developed. The output of the low-pass filter stage within the loop-filter is monitored to get an idea of the amount of error contained within the loop. These signals were chosen because the injected error at the output of the device will give rise to a common mode error within the loopfilter. If this level gets too large the resistive paths within the two integrator stages, described earlier get engaged allowing for a direct control of the output by the input. These paths essentially bypass the effects of the loop-filter until the error comes back down to a reasonable level. The error monitor consists of a buffer stage with a large input impedance so as not to affect the gain of the low91
pass filter, followed by an adder circuit so that some idea of the common mode level of the system can be gleamed. After the adder the signal is passed into a decision circuit that determines if the system is within the appropriate bounds, if it is not the bypass resistance paths are engaged within the integrator stages. Figure 3-41 shows the output stage simulation with large amounts of injected error at the output with no error detection/limitation enable. The type of error simulated here caused the output to skip pulses as opposed to adding additional pulses as seen in Figure 3-40.
Figure 3-41: Output Stage with Large Error and Error Limiter Disabled If the error limitation circuit is enabled the system will force oscillations to occur at the output, regardless of the amount of error injected at the output of the device. Figure 3-42 shows the system with the same amount of injected DC error, but this time the error limiting circuit is engaged.
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Figure 3-42: Output Stage with Large Error and Error Limiter Enabled Figure 3-42 shows a better operation as no output pulses were missed. While all of the error was not corrected it is more important that the output switch states every time the input does. Design Conclusions This chapter has given an overview of the devices and components used to make up the proposed Class-D system. While a full analysis of every transistor used is beyond the scope of the paper the main purpose was to introduce the components and give mention to the practical issues that arose. The design outlined in this chapter was submitted to MOSIS foundry for fabrication in May of 2005. The MOSIS foundry graciously decided to fabricate this device as a research project at no charge to Texas Tech University under the agreement that the results of the device be provided back to them as a method for evaluating the process flow. For reference the bonding diagram provided by MOSIS for the submitted device is shown in Figure 3-43. Table 3-5 lists the pins, their corresponding pin numbers as well as a brief description of their functionality.
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Figure 3-43: MOSIS Die to Package Bonding Diagram
Pin Number
Table 0-5: Pin Descriptions of Device Pin Name Description
1
DVDD
2
FB_PWM_P
Digital circuitry supply Externally supplied PWM signal for feedback, analog
3
FB_PWM_N
Externally supplied PWM signal for feedback, analog
4
EXT_IN_EN
Enable signal for externally supplied feedback PWM signal
5
DVSS
Digital circuitry ground
6
PVDD1
Output stage power device supply, p side
7
PVSS1
Output stage power device ground, p side
8
PVSS2
Output stage power device ground, n side
9
SD_OUT
Digital sigma-delta 7-bit to 1-bit converter output 94
10
VDD
Analog circuitry supply
11
FF_DIG_P
Feed-forward loop output
12
FF_DIG_N
Feed-forward loop output
13
PWM_EN
Enable signal for externally supplied PWM signal as input of output stage, bypassing the conversion stage
14
PWM_IN
External PWM signal to be supplied to output stage input
15
PVDD2
Output stage power device supply, n side
16
D0
Conversion stage input, bit-0
17
D1
Conversion stage input, bit-1
18
D2
Conversion stage input, bit-2
19
D3
Conversion stage input, bit-3
20
DVSS
21
D4
Conversion stage input, bit-4
22
D5
Conversion stage input, bit-5
23
D6
Conversion stage input, bit-6
24
CLK
25
DVDD
26
NC
27
FF_EN
Digital circuitry ground
Clock, frequency of 7-bit input signal Digital circuitry supply No connect Enable signal for feed-forward loop in conversion stage
28
AVSS
29
NC
30
CLK_128
31
VSS
32
FB_EN
33
RST
Analog ground (VDD/2) No connect High frequency clock (128*CLK) Analog circuitry ground Enable signal for feedback loop in output stage Reset signal for output stage capacitors and reference wave clock generation
34
LIM_EN
Enable signal for error limiting circuitry 95
35
NC
No connect
36
VREF
Output of error limiting circuitry
37
VO_N
System output
38
VO_P
System output
39
VO_S1_P
Conversion stage output
40
VO_S1_N
Conversion stage output
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CHAPTER IV SYSTEM VERIFICATION To ensure that the integrated circuit design worked as planned a full and thorough verification of the system was planned. The functional verification was to be accomplished through the use of a specially designed test circuit. This chapter describes the tests that can be used to fully verify the functionality of the device, the circuit used for verification, and provides an analysis of results of the tests performed. Test Plan This section will describe the different system parameters that should be tested for this kind of device and the setup required to perform that particular test [6]. The tests described here were not all performed on the fabricated device due to lack of access to equipment and limited test circuit functionality. The individual tests that are desirable in characterizing Class-D audio devices are summarized below. 1. THD – One of the most important parameters of an audio system is the total harmonic distortion or THD at the output of the device. The THD gives a measurement of the amount of distortion at the output as compared to the signal strength. Typically this parameter is not directly measured, what is measured is the THD plus noise, (THD+N). This figure tells not only about the amount of distortion within the system but also the amount of noise generated within the various components of the amplifier structure. The noise can be from system level considerations like quantization noise down to device level considerations like thermal and flicker noise [40]. To test the THD+N a single frequency sine wave is put into the system and the output frequency spectrum is measured. Due to the design of the system the THD+N of the overall system as well as for
97
the conversion stage and output stage can be measured independently from one another. 2. DC Conversion Accuracy – The accuracy of the output as compared to the input is measured by sweeping a DC input signal and measuring the averaged DC output at specific points. Again due to the structure of the system the conversion accuracy can be measured independently of the output stage accuracy. The test setup allows for applying specific DC inputs through DIP switches corresponding to setting specific input bits. This allows for precisely setting the input level to minimize measurement error. By measuring the DC output to DC input function an idea of overall linearity can be gained. 3. Sigma-Delta Conversion Performance – The performance of the 7-bit to 1-bit digital sigma-delta converter can be directly measured due to the availability of the sigma-delta output at a pin of the chip. Again a specific DC input value can be chosen and the output measured using a digital oscilloscope. 4. SNR – Another very important specification in amplifier design is the signal to noise ratio (SNR) of the system. This parameter describes the amount of signal power as compared to the amount of power contained within the noise spectrum through the audio band. This is measured by again applying a single frequency sinusoidal input and measuring the noise floor with respect to the fundamental. This is typically done for many input amplitudes and frequencies to create a good test coverage. Again the entire system can be tested as well as the isolated conversion and output stages. 5. Dynamic Range – This test is very similar to the SNR test but is much more specific. For the dynamic range (DR) the SNR is measured at an input level of -60dB with respect to full-scale. 60dB is then added to the measured SNR resulting in the DR of the system. Again this is typically measured for several 98
frequencies and for the overall system and the isolated components. This value can also be included in the measurements to be performed on the digital sigmadelta converter as well as the PCM-PWM converter. 6. Feed-Forward Loop Characteristics – This is a new component so special care should be taken in characterizing the performance of this first generation system component. The digital output as provided by the chip can be examined using different amounts of simulated clock jitter to determine the future use of this mechanism. 7. Error Limiting Circuitry – Another new component that can be tested is the error monitoring and limiting system. This system is tested by utilizing the ability to inject feedback signals into the loop. The signals that are fed into the system allow for direct control of the amount of error, thus allowing for direct testing of the capabilities of the error limiting devices. Test Circuit In order to quickly and accurately complete tests on all of the provided stages a stand-alone test setup was created. The setup includes many of the components needed to perform the tests mentioned above with as little equipment as possible. The idea of the circuit was to be able to create as many of the required signals for the amplifier as possible using components on the board, allowing for minimal test equipment. The following sections describe the circuit as well as the fabricated PCB in greater detail. Circuit A full system was designed to be able to test many of the functionalities of the Class-D amplifier device. Figure 4-1 shows a complete schematic of the test system. The test circuit allows for many of the required signals for the fabricated
99
amplifier to be created on the PCB and tuned through the use of potentiometers or to be supplied externally allowing for complex testing.
Figure 4-1: Full Test System Schematic The individual supply levels for the test device are created using a resistor chain with a potentiometer to allow for precise tuning, or for variation from ideal levels. The voltage level is then put into an op-amp in a voltage-follower configuration allowing for a high input-impedance and low output-impedance. The op-amp chosen has a high output drive to allow for sourcing enough current to operate the device. Figure 4-2 shows the schematic for a single supply generation circuit.
100
Figure 4-2: Device Supply Generation Schematic As mentioned previously most supplies and signals are able to be generated onchip as well as supplied by external sources. The on-chip reference is created as described above while the off-chip reference is supplied by connecting a source to a BNC connector on the circuit. The selection of signals is facilitated through a set of double-pole single-throw (DPST) switches using a special chip. The diagram for the device is shown in Figure 4-3.
101
Figure 4-3: DPST Chip Diagram3 This device is used with the drains tied together across a single set of selection possibilities, the selection is made by setting or clearing the INx pin. This will engage only on path and will completely disengage the alternative path. As an additional test configuration the loop-filter topology as described in Chapter 2 was implemented at a discrete level on the board to allow for testing of various features of the board before the actual fabricated devices were completed. The schematic of this implementation is shown in Figure 4-4. Using this circuitry the loop-filter topology can be tested both at the discrete implementation level as well as at the integrated device level.
Figure 4-4: Discrete Loop-Filter Implementation Schematic
3
Figure reproduced from the device datasheet found at: http://www.vishay.com/docs/70049/70049.pdf
102
PCB Once the schematic was fully designed a PCB was created to allow for higher accuracy testing. A PCB implementation is almost required for projects with as large a scale as the test circuit described above. A lower noise operation is allowed due to the minimal soldering required for the final implementation allowing for better results. The layout of the PCB as submitted to Advanced Circuits (www.4pcb.com) for fabrication is shown in Figure 4-5 along with a 3D model created through the PROTEL design system in Figure 4-6.
Figure 4-5: Test PCB Layout
103
Figure 4-6: 3D Visualization of PCB
Results Full testing of the device turned out to be extremely difficult due to the variance of equipment used. The initial testing of the devices was carried out at Texas Tech University using standard equipment, a more detailed set of tests was planned to be done at Texas Instruments using more sophisticated instruments tailored specifically towards audio measurements. Due to scheduling constraints and instrumentation requirements the more advanced measurements were not possible, but detail about the performance of the amplifier was obtained using conventional instruments. This section will discuss the tests that were performed and the results that were obtained. In general the fabricated device worked as planned, with all major functionality working at a high level. The fabricated device is shown in Figure 4-7.
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Figure 4-7: Fabricated Device PCM-PWM Conversion Accuracy A simple comparison between the digital input to the device and the PWM modulation index at the output of the PCM-PWM converter was done to examine the accuracy of the conversion stage. Figure 4-8 shows a simple example of a waveform with the DC level and the output PWM waveform, Figure 4-9 shows a low DC level and the corresponding PWM output and Figure 4-10 shows a high DC level and the PWM output. In all of these figures the DC level was created using the DIP switches located on the test circuit and then passed through a Dto-A converter to allow for simple viewing on an oscilloscope.
Figure 4-8: Zero DC Input and PWM Output
105
Figure 4-9: Low DC Input and PWM Output
Figure 4-10: High DC Input and PWM Output Figure 4-11 shows the Converted PWM duty cycle as a function of the ideal input duty cycle based on the input DC level. It is seen that the converted level is extremely linear especially around the zero level. Some of the non-linearity at the upper end of the operation may actually be attributed to the D-to-A converter as opposed to the Class-D amplifier itself.
106
Figure 4-11: Output Duty Cycle vs. Ideal Input Duty Cycle Error Correction The output of the device with zero injected error is seen to follow that of the converted PWM signal exactly. This is good as it means that the output stage, under nominal conditions, adds very little additional error. This is shown in Figure 4-12 where a PWM signal has been put directly into the device and the PWM output after the feedback loop is examined.
107
Figure 4-12: PWM Input and PWM Output As the injected error is varied on the test circuit the output PWM duty cycle begins to change to try to correct the total area as described in Chapter 2. This is shown in Figures 4-13 and 4-14.
Figure 4-13: PWM Input and Output with Small Injected Error
108
Figure 4-14: PWM Input and Output with Large Injected Error It is seen that for small injected error signals the output waveform is as predicted but as the injected error increases the signal becomes less stable changing duty cycles erratically. To some extent this was predicted during the calculations for pulse skipping in Chapter 2. Figure 4-15 shows the output duty cycle as a function of the injected error signal for a constant input PWM duty cycle.
Figure 4-15: Output Duty Cycle vs. Injected Error 109
Here it is seen that the system output duty cycle linearly changes with the injected error level until the error reaches approximately 12% deviation from ideal levels, beyond this the duty cycle deviation becomes unstable. The linear relationship at low injected error levels is very good as it will allow for low distortions due to error correction at the output stage of the device. Error Limiting As seen in Figure 4-14 the duty cycle begins to become unstable at larger injected error levels. This was discussed in Chapter 2 and becomes extremely apparent when the output begins skipping cycles, or injecting extra cycles due to the large amounts of injected error at the output. These two situations are shown in Figures 4-16 and 4-17 respectively, each figure contains the output PWM waveform at the top and the converted DC input level on the bottom.
Figure 4-16: Pulse Skipping due to Large Injected Error
110
Figure 4-17: Extra Pulses due to Large Injected Error In Figure 4-16 The PWM waveform is stuck at a single level and is not changing due to the large injected error at the output stage of the device. Figure 4-17 shows the output waveform oscillating during what should be a single level again due to the large injected error signal. The incorporation of the error limiting circuitry helps to correct both of these situations, Figure 4-18 shows a PWM waveform with the error limiting circuitry disabled and enabled to demonstrate how oscillations are forced.
Figure 4-18: System with Large Injected Error and Error Limiting Enabled and Disabled From Figure 4-18 it can be seen that the system is forced to oscillate when the error correction circuitry is enabled. This allows for larger error signals to be safely to be injected without the fear of device failure at the output.
111
DC to DC Sigma-Delta Converter As part of the Feed-Forward Correction path the DC to DC Sigma-Delta converter was created. Figure 4-19 shows the Sigma-Delta output signal and high-frequency conversion clock.
Figure 4-19: Sigma-Delta Output and Conversion Clock From this figure it is seen that the output changes states every two clock cycles and maintains approximately 50% duty cycle corresponding to a zero level input. Figure 4-20 shows the output in response to a lower DC input level.
Figure 4-20: Sigma-Delta Output with Low Input DC Level As expected the overall average value of the sigma-delta output signal goes down with the lower DC input level. Similarly the average value will increase at higher DC input values, this is demonstrated in Figure 4-21. 112
Figure 4-21: Sigma-Delta Output with High Input DC Level Testing Conclusions The device seems to perform well through these simple tests; however more detailed testing is desired to fully characterize the performance of the device. The test plan laid out at the beginning of this chapter is left in as a roadmap for future testing.
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CHAPTER V FURTHER ENHANCEMENTS AND CONCEPTS This chapter contains ideas and concepts that were developed too late to be included in the actual fabricated device but provide for possible added functionality and future systems-level device enhancements. These are concepts for future systems and are included as documentation of ideas. Resolution Enhancement Architecture In Typical PCM to PWM converter architectures the resolution of the output PWM waveform is limited by the clock frequency of the triangle wave reference used in the comparison. Thus to increase the resolution the overall system clock must also increase which, in turn increases the power consumption of the device and decreases the overall efficiency. A method for increasing the effective resolution of the device is to insert a stage that can subdivide the sampling period into N smaller equally sized sections thus providing for an Ntimes resolution increase. Doing this without increasing the clock frequency can be accomplished using delay elements as the input to a multiplexer and selecting a delay element based on a previous error generating stage. The error gives a direct representation of how far off the PWM wave is from ideal, thus the multiplexer line is selected that most closely brings the waveform closer to the ideal. This new system component can be utilized in a wide variety of areas, anywhere there is an error generating stage this device can be implemented to help raise the resolution, on the condition that the signal does not need to be resampled after the stage. As an example a small, low-power, fast PCM-PWM converter could be created by omitting the sigma-delta stage. Instead of the correctly used implementation the lower bits that are thrown away before the PCM-PWM converter block could be used as the reference signal to the 114
proposed stage which would help compensate for the generated error. The proposed component topology is shown in Figure 5-1.
Figure 5-1: Resolution Enhancement Architecture The control lines of the multiplexer select the appropriately delayed signal to correct the pulse edge, which allows for fine correction of the output within a single clock period. This results in an increased time resolution by further subdividing the clock period of the high frequency PWM clock. Each element feeding the multiplexer should have a delay equal to:
td =
Tclk N −1
(5.1)
where N is the number of delay elements in the chain and Tclk is the period of the clock. As an example a system with four stages setup for a symmetric correction is shown in Figure 5-2. It is seen that the standard pulse, or zero correction, is taken in the center of the delay chain allowing for both positive and negative correction. This architecture is attractive due to the low number of parts required 115
for realization. With only N delay stages, each being comprised of as little as two inverters, and a multiplexer.
Figure 5-2: Demonstration of Delay Chain Configuration Resolution Enhancement Performance To test the effectiveness of the new architecture it can be compared to standard topologies utilizing a second-order sigma-delta converter. The two test architectures are shown in Figure 5-3 along with a reference architecture that simply truncates the signal before the PCM-PWM converter with no correction.
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Figure 5-3: Architecture Comparison For all test systems the input is converted from 16 to 7 bits with a PWM carrier frequency of 384 kHz. The PCM-PWM conversion is done through the digital comparison of the 7-bit signal with an internally generated 7-bit triangular reference. The resolution enhancement device is simulated with a maximum of thirteen delay stages with the standard output chosen to be after the 7th stage allowing for symmetric correction, as shown in Figure 5-2. The error signal is taken as the 9 bits that were removed from the input, rescaled to allow for proper control of the multiplexer. To facilitate changing the pulse shape complementary rising and falling edge delays are used about the center stage. This means that if the error was such that on the rising edge the 8th stage delay is chosen on the falling edge the 6th stage output is used. Doing this type of correction is required for symmetric PWM due to the need to move the pulse edges in opposite directions to affect the duty cycle of the waveform. Figure 5-4 shows the output error of the three systems shown in Figure 5-3 over the full input range. Figure 5-5 shows the same simulation but only with an input of 0 to 0.1 to highlight the differences in the shapes of the error signals.
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Figure 5-4: DC Error of Test Systems
Figure 5-5: Small Signal DC Error of Test Systems For this simulation the delay used for each stage is given by:
td =
(13 − 1) ⋅ 2
1 7
⋅ 44.1 kHz
≈ 14.8 ns
(5.2)
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From Figure 5-4 and Figure 5-5 it is seen that the small-signal noise performance is worse in the resolution enhanced architecture than the sigma-delta while the larger signal performance is approximately the same. What should be noted is that the resolution enhancement device does not exhibit the random error of the sigma-delta but rather the same triangular shaped error signal of the truncated signal, with additional levels. Figure 5-6 shows a comparison between the three systems with a varying number of delay stages in the resolution enhancement device.
Figure 5-6: Average Error vs. Number of Stages in Delay Chain The error shown is the average error of a DC sweep similar to that in Figure 5-4 found by adding the errors for each input level and dividing by the number of DC input levels. It is seen from Figure 5-6 that the proposed system performs best using 9 delay stages, which corresponds to the number of bits removed from the input, Fewer stages does not allow for maximum compensation while additional stages causes over correction. Another situation in which the resolution enhancement device could work well is when used in conjunction with a sigma-delta device. Figure 5-7 shows a 119
possible system configuration utilizing both devices, for this type of setup the delay would be:
td =
1 ≈ 1.38 ns (9 − 1) ⋅ 16 ⋅ 2 7 ⋅ 44.1 kHz
(5.3)
Figure 5-7: Architecture of Resolution Enhancement Device used in Conjunction with Sigma Delta Figure 5-8 shows the average error, again vs. the number of stages, when using the two devices together as shown in Figure 5-7. Utilizing the device in this manner could allow the requirements of the sigma-delta converter to be greatly relaxed. For example the number of stages could be reduced resulting in an overall smaller device.
Figure 5-8: Average Error of Resolution Enhancement Device with Sigma Delta vs. Number of Stages 120
Error Effects A practical consideration is how this device will react to deviations from ideal delay within the delay chain. Due to the symmetry of the pulse edge delays with the configuration described in Section 5.1.1 this error is minimized. When a non-ideal delay is encountered the same non-ideal delay is encountered on the opposite pulse edge. This delay on both edges simply shifts the pulse and all subsequent pulses, but does not affect the duty-cycle, thus the output level remains constant. This situation does not occur for non-symmetric PWM waveforms, any deviation from standard delay will be directly represented in the output PWM waveform. This pure shifting does not always occur, even in the symmetric case. If the required correction is large the same delay stages may not be used for both the rising and falling edges of the PWM wave, causing the duty cycle to be changed slightly. Figure 5-9 shows the effects of delay error in different stages of the chain, simulated using a 9 element delay chain using the resolution enhancement architecture in conjunction with the sigma-delta converter. What is seen is small amounts of deviation from the standard operating condition regardless of where the delay occurs, with the largest deviations occurring if the error is in the middle stage. At first it also seems strange that the delay with no error is not the minimum; this is probably due to the random nature of the error in the sigma delta approach. Even with additional error in a single stage the overall duty cycle will still be closer to the input than if the resolution enhancement device were not used.
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Figure 5-9: Average Error vs. Delay Error for Error Occurring in Different Stages Additional THD Compensation As seen from Chapter 2 the self generated cosine wave resulting from the subtraction of the output from the input is very problematic to the system performance. It would be very advantageous if this error could be eliminated as lower distortion conditions would then occur. Since the magnitude and phase of the error waveform are known a simple additional filter could be implemented allowing the re-creation of this waveform and thus cancellation before the loopfilter. The comparison of the PSD of the standard system and a compensated system is shown in Figure 5-10.
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Figure 5-10: PSD of Standard System and Enhanced System with Ripple Suppression From this it is seen that distortion can be decreased by over 20dB through the introduction of this additional filter path. An additional feature of removing the injected ripple is that it further enhances the optimization of balancing the gains of the loop-filter. Figure 5-11 shows a plot of the simulated third-harmonic level versus the deviation of K1 from the optimum value for the compensated and uncompensated systems. The compensated system, which operates more like the ideal system assumed in the calculations of Chapter 2, has a clear minimum in the third-harmonic level at the calculated optimum value of K1.
123
Figure 5-11: Third Harmonic vs. K1 for Compensated and Uncompensated Systems While no full implementations have been tested using this concept of using an additionally filtered version of the loop-filter reference to improve overall linearity, the concept is highly intriguing due to the huge gains that seem possible.
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CHAPTER VI CONCLUSION This dissertation has introduced several improvements to standard ClassD operating structures. Improvements were proposed in both of the major sections of the amplifier, the conversion stage and the output stage. The various components of the proposed system were introduced at a basic level, and then the theory behind the improvements was introduced and verified using the SIMULINK simulation package. A transistor and layout level design was then discussed with simulation results provided through the use of CADENCE with device models provided by the MOSIS design foundry. Finally the fabricated devices were tested and analyzed through the use of custom designed test equipment made to increase the speed and efficiency of testing. In addition to the implemented improvements several future improvements were suggested and developed. Possible components for future systems were introduced with some idea of possible direction or usage within next generation amplifiers. Within the main amplifier described in Chapters 1-4 further improvements are possible, both in the theoretical aspects as well as in the implementation. In particular more time needs to be spent on the development of the pulse-skipping monitor and prevention circuitry. These systems will be crucial to complete implementations as they will allow for the end user to utilize any external components with the amplifier, regardless of their noise generation. The system itself will then correct as much of the resultant error as possible producing a better output than other devices could. This will make for a more attractive implementation since it allows for low cost components to be used. If this error limiting system is not correctly implemented severe restrictions would have to be placed on the components used in the end system to ensure that error levels were within reason so that no undesirable output glitches would occur. This is probably one of the more important components for wide-spread implementation 125
of these feedback systems and thus should be dealt with in much greater detail. Additionally the implementation of the loop-filter can be addressed as this component is directly responsible for the performance of the output-stage, any additional improvements would be welcomed. The fabricated device was tested with available equipment, however more detailed tests using sophisticated audio specific testing devices would have further increased the level of understanding of the device and characteristics of feedback power-stages in general. This testing was not possible due mostly to the fact that the more advanced testing equipment requires special input and output connections to allow for the more advanced testing modes. To fully utilize the equipment a different test board would have to be designed. In general the initial results provided by the tests that were performed are extremely good. All of the functionality designed into the device was verified to work as designed, with only the detailed performance needed to be tested in more detail.
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132
APPENDIX A FOURIER DECOMPOSITION OF THE LOOP-FILTER INPUT To construct a Fourier series of the PWM wave with a small injected error signal a PWM pulse must be defined. The pulse definition used through this analysis is shown in Figure A-1.
Figure A-1: Setup for Fourier Series of PWM waveforms
From Figure A-1 the time dependant signal can be represented as:
x(t ) =
−A
for
A
for
−A
for
− Ts ≤ t < t1 2 t1 ≤ t < t 2 . T t2 ≤ t ≤ s 2
(A.1)
The Fourier coefficients will then be given by:
a0 =
a0 =
2 Ts
t1
t2
Ts 2
t1
t2
(− A)dt + ( A)dt + (− A)dt
T − s 2
(A.2)
T 4A t 2 − t1 − s Ts 2
(A.3)
133
an =
an =
bn =
bn =
2 Ts
t1
(− A) cos
−Ts 2
Ts 2
t2
2nπt 2nπt 2nπt dt + ( A) cos dt + (− A) cos dt Ts Ts Ts t1 t2
2A [sin (nω s t 2 ) − sin (nω s t1 )] nπ 2 Ts
t1
(− A)sin
−Ts 2
(A.4)
(A.5) Ts 2
t2
2nπt 2nπt 2nπt dt + ( A)sin dt + (− A)sin dt Ts Ts Ts t1 t2
2A [cos(nω s t1 ) − cos(nω s t 2 )] Ts
(A.6)
(A.7)
In the above equations ω s is the sample frequency of the PWM wave in radians/second. It is now seen that after some simplifications the waveform can be given by:
x(t ) =
Aω s
π
t 2 − t1 −
Ts + 2
∞
2A [sin (nω s (t 2 − t )) − sin (nω s (t1 − t ))] . n π n =1
(A.8)
This is a very general equation for the waveform. In order to extract any information from it a more useful form must be taken. To do this a specific type of PWM waveform is chosen, namely the symmetric PWM wave. This type is created when the pulses are centered about the middle of the sample period as discussed in Chapter 1. The following modifications are made as a consequence of this assumption: − Ts m(t ) 2 T t 2 = s m(t ) . 2
t1 =
(A.9)
134
The m(t) portion is the time dependant modulation index of the waveform. The function is also normalized by setting the amplitude to 1 to help simplify the equations. Using the above definitions results in: a 0 = 2(2m(t ) − 1) an =
(A.10)
4 sin (nπm(t )) nπ
(A.11)
bn = 0 .
(A.12)
yielding:
x(t ) = (2m(t ) − 1) +
∞
4 sin (nπm(t )) cos(nω s t ) . n =1 nπ
(A.13)
Equation (A.13) can further be examined if it is realized that m(t) can be a simple sinusoid. This is the audio-band waveform information that was encoded within the PWM waveform. The parameter m(t) will then be redefined to be
m(t ) =
Ax sin (ω x t ) + 1 2
(A.14)
where Ax and ω x are the amplitude and frequency of the input to the PWM converter, respectively. Using (A.14) in (A.13) yields:
x(t ) = Ax sin (ω x t ) +
A sin (ω x t ) − 1 4 sin nπ x cos(nω s t ) . 2 n =1 nπ ∞
(A.15)
This means that the system output, given the above assumptions, can be defined by:
135
y (t ) = x(t − t s′ ) + E (t − t s′ ) = Ax sin (ω x (t − t s′ )) +
. A sin (ω x (t − t s′ )) − 1 4 sin nπ x cos(nω s (t − t s′ )) + E (t ) 2 n =1 nπ
(A.16)
∞
Here t s′ has been defined as the delay of the switching time from the input to the output. Next the subtraction node can be examined to find the reference signal, which is the loop-filter input. This is seen to be
u (t ) = x(t ) − y (t )
(A.17)
u (t ) = Ax [sin (ω x t ) − sin (ω x (t − t s′ ))] +
A sin (ω x t ) − 1 A sin (ω s (t − t s′ )) − 1 4 sin nπ x cos(nω s t ) − sin nπ x cos(nω s (t − t s′ )) 2 2 n =1 nπ ∞
− E (t ) .
(A.18)
After much algebra this results in:
u (t ) = 2 Ax sin ω x − +
Ts cos(ω x t ′) 2
8 nπ sin 2 n =1 nπ ∞
∞ k = 2 ,even
+ cos
J k (β n )
nπ 2
J 0 (β n ) sin (nω s t ′)sin
(
)
n ω s Ts 2
(
(A.19)
)
T T sin ω t ′ sin ω s + sin ω nk+ t ′ sin ω nk+ s 2 2
∞ k =1,odd
− nk
− nk
(
)
J k (β n ) cos ω nk− t ′ sin ω nk−
(
)
Ts T − cos ω nk+ t ′ sin ω nk+ s 2 2
where the following simplifications have been made:
136
− E (t )
u (t ) = vin (t ) − vout (t ) t ′ = t − t1′ ≈ t − t 2′
ω nk± = nω s ± kω x ω s is the PWM carrier frequency ω x is the input frequency nπAx βn = Ax
2 is the input amplitude
Jk
is the Bessel function
(A.20)
137
APPENDIX B DEVICE LAYOUTS AND SCHEMATICS All schematics and layouts are found here for reference. Full System
Figure B-1: Full System Schematic
Figure B-2: System Layout without Padring 138
Figure B-3: Full System Layout
139
Conversion Stage
Figure B-4: Conversion Stage Overall Schematic
140
Figure B-5: Conversion Stage Overall Layout
141
PCM-PWM Converter
Figure B-6: PCM-PWM Converter Schematic
142
Figure B-7: PCM-PWM Converter Layout
143
Digital Comparator
Figure B-8: Digital Comparator Schematic
Figure B-9: Digital Comparator Layout
144
Figure B-10: Triangle Wave Reference Generator Schematic
Figure B-11: Triangle Reference Generator Layout
145
Sigma Delta Converter
Figure B-12: Digital Sigma Delta Converter Schematic
146
Figure B-13: Digital Sigma Delta Converter Layout Digital Adder
Figure B-14: Digital Adder Schematic
147
Figure B-15: Digital Adder Layout Digital Integrator
Figure B-16: Digital Integrator Schematic
Figure B-0-17: Digital Integrator Layout
148
Multiply by Two
Figure B-18: Multiply by Two Schematic
Figure B-19: Multiply by Two Layout
149
Feed-Forward Correction Special Adder
Figure B-20: Special Digital Adder
150
Loop-Filter
Figure B-21: Feed-Forward Loop-Filter Analog Adder
Figure B-22: Analog Adder
151
Output Stage
Figure B-23: Output Stage Overall Schematic
Figure B-24: Output Stage Overall Layout
152
Loop-Filter
Figure B-25: Loop-Filter Schematic
Figure B-26: Loop-Filter Layout 153
Operational Amplifiers
Figure B-27: Folded-Cascode Op-Amp
Figure B-28: Simple Single-Ended Op-Amp
154
Figure B-29: Op-Amp Bias
Figure B-30: Simple Single Ended Op-Amp
155
Integrators
Figure B-31: First Integrator
Figure B-32: Second Integrator
156
Low-Pass Filter
Figure B-33: Low-Pass Filter Comparator
Figure B-34: Comparator
Figure B-35: Single Ended Adder
157
Error Detection Circuit
Figure B-36: Error Detection Schematic
Figure B-37: Error Detection Layout
158
Figure B-38: Error Decision Schematic
Figure B-39: Error Decision Layout
159
Output Devices
Figure B-40: Pad-Driver Schematic
Figure B-41: Pad-Driver Layout
160
APPENDIX C VERILOG CODE This appendix contains the majority of the VerilogA code used in the testing of the Class-D amplifier described in this dissertation. Test Blocks These blocks were used for testing various components, they contain items like A/D converters used to create required digital signals using an analog source. 7-bit A/D converter // VerilogA for mp8_VerA, AD_7b, veriloga `include "constants.h" `include "discipline.h" module AD_7b(VDD, VSS, an, dig, clk); // declare the ports input an, clk, VDD, VSS; output [0:6] dig; // set the specs for the ports electrical an, clk, VDD, VSS; electrical [0:6] dig; // define the input range as a parameter parameter real in_range=1; parameter real AGND=0; parameter real V_clk_ref = 1.0; real c_vin; integer j; real outdum[0:6]; // begin the module definition analog begin // set the initial output to be 0 // this may not be the best thing to do @(initial_step) begin generate i (0,6) begin V(dig[i])
