An Improved Small-Signal Parameter-Extraction Algorithm for GaN ...

IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 56, NO. 7, JULY 2008

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An Improved Small-Signal Parameter-Extraction Algorithm for GaN HEMT Devices Ronan G. Brady, Student Member, IEEE, Christopher H. Oxley, and Thomas J. Brazil, Fellow, IEEE

Abstract—A highly efficient and accurate extraction algorithm for the small-signal equivalent-circuit parameters of a GaN high electron-mobility transistor device is presented. Elements of the extrinsic equivalent-circuit topology are evaluated using a modified “cold field-effect transistor” approach whereby the undesirable need to forward bias the device’s gate terminal is avoided. Intrinsic elements are determined based on a circuit topology, which identifies, for the first time, a time delay in the output conductance of GaN-based devices. The validity of the proposed algorithm has been thoroughly verified with excellent correlation between the measured and modeled -parameters up to 50 GHz. Index Terms—Gallium nitride (GaN), heterojunction field-effect transistor (HFET), high electron-mobility transistor (HEMT), parameter extraction, small-signal modeling.

I. INTRODUCTION

R

ECENT publications on GaN-based high electron-mobility transistor (HEMT) technology have demonstrated superior performance capabilities over more traditional GaAs/ InP/SiGe-based counterparts [1]–[3]. The large bandgap energy , typically of the order of 3.4 eV, results in higher breakMV/cm) permitting much larger voltage down fields ( swing across the output of the device [4]. Fabrication of the substrate [5], e.g., device on a high thermal conductivity W/cm K) will enable improved power-hanSiC ( dling capabilities and increased thermal stability under adverse temperature operating conditions [6]. Furthermore, enhanced carrier-confinement processes, whereby both piezoelectric and spontaneous polarizations contribute to the 2-DEG layer formation, induce improved sheet carrier densities in excess of 2 10 e/cm [7] when compared with GaAs, typically 2 10 e/cm . Monte Carlo simulations have also predicted satcm/s [8]. uration velocities of the order of Taking all these factors into consideration, GaN-based transistor technologies have undoubtedly become an ideal candidate for high-power and high-frequency microwave circuitries for applications in many areas including aerospace, military, and wireless communications. Over the last few decades, the development of an accurate device model has proven to be a vital step in the “first-pass” Manuscript received January 18, 2008; revised April 16, 2008. First published June 13, 2008; last published July 9, 2008 (projected). This work was supported by the Science Foundation Ireland under the Principal Investigator Award at University College Dublin, Dublin, Ireland. R. G. Brady and T. J. Brazil are with the School of Electrical, Electronic and Mechanical Engineering, University College Dublin, Dublin 4, Ireland (e-mail: [email protected]; [email protected]). C. H. Oxley is with the Computing Science and Engineering Department, De Monfort University, Leicester LE1 9BH, U.K. (e-mail: [email protected]). Digital Object Identifier 10.1109/TMTT.2008.925212

design approach when designing monolithic microwave integrated circuits (MMICs). Models provide a valuable tool for predicting the large-signal performance of a device when simulated with complex modulation schemes like wideband code division multiple access (W-CDMA). An electrical equivalent circuit is one such device model. It provides a means of describing the electrical properties of the device-under-test (DUT) by linking elements of the equivalent circuit directly to the physical structure of the device. Complete characterization of a device’s large-signal performance warrants an accurate evaluation of this underlying equivalent circuit under small-signal conditions. During the last decade, a number of papers have presented different approaches for extracting the small-signal model (SSM) parameters of GaN-based transistors. An LDMOS modeling technique [9] has been proposed for the GaN heterostructure field-effect transistor (HFET) [10], whereby all eight parasitic elements are evaluated solely from the DUT in an off state. However, the present authors are of the view that, for some devices, extraction of the elements of the parasitic network using a single bias state can be problematic. In particular, the data required for series element extraction can be quite noisy and certain network parameters may exhibit an undesirable dependence with frequency. A 22-element distributed model proposed in [11] requires the estimation of initial element values for a bi-directional optimization technique. However, the process of acquiring these initial estimates involves the use of several empirical and algebraic assumptions, which may not suit all device structures. A low gate bias model extraction technique [12] has demonstrated an efficient SSM evaluation. All elements are determined without forward biasing the gate of the device. Nonetheless, the procedure can only be applied to devices where the equivalent drain–source capacitance is negligible. As will be highlighted in this paper, is, in general, not negligible and can be particularly high under certain cold field-effect transistor (“cold-FET”) bias conditions. The existence of a significant effect has been addressed in a recent GaN “cold-FET” extraction approach [13]. In spite of this, an iterative procedure is required to determine a suitable forward biasing condition that is high enough to suppress the channel resistance, but low enough not to cause significant current flow through the gate terminal that could otherwise permanently degrade the future performance of the device. Furthermore, a certain level of modeling experience is required to identify the appropriate frequency ranges over which the -parameters can be used to evaluate the parasitic resistances. Several publications [14], [15] have identified the existence of time delays in the output conductance element of

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the standard small-signal equivalent circuit of FET devices. Without modifications to the conventional intrinsic circuit topology [16], this feature can be misinterpreted as bias-dependant drain and source access resistances. In extreme cases, these resistances may even appear negative [14], the plausibility of which is questionable from a physical point-of-view, while they can also create problems with implementation in simulators. at higher frequencies has been The increased phase delay in attributed to this phenomenon [17]. Based on this observation, an additional time dependence has been introduced into the element of a conventional equivalent circuit [18], [19]. In are identified for the this study, similar phase delays in first time in GaN-based HEMTs. Utilizing the circuit topology proposed in [18] issues regarding the physical consistency of the extracted access resistances are resolved. A complete extraction procedure of all equivalent-circuit elements in a GaN HEMT device is presented in this paper. All extrinsic parasitic elements are evaluated under “cold-FET” conditions without forward biasing the gate terminal, as there is no requirement for the channel resistance to be small. Using a straightforward optimization procedure and utilizing a selection of well-established analytical expressions, values for the intrinsic equivalent-circuit elements can be accurately determined. The robustness and efficiency of this novel approach clearly distinguishes this study from previous extraction methodologies. This is demonstrated by the fact that elements are determined in a step-by-step noniterative procedure, which requires minimal intervention or experience on the part of the model developer. The validity of the proposed small-signal modeling methodology is discussed and the reliability of the evaluated SSM parameters is rigorously demonstrated. II. DEVICE STRUCTURE The SSM has been determined for an AlGaN/GaN HEMT transistor fabricated at QinetiQ Ltd., Hampshire, U.K. It consists of a double cell “pi” structure with a 0.29- m gate length, as measured by focused ion beam cross sectioning. The gate metallization is a “T profile” in order to minimize the parasitic gate resistance. The total gatewidth is 100 m, consisting of two unit gatewidths of 50 m, and the gate-to-drain spacing is approximately 1.8 m. The layer structure consists of 28-nm AlGaN (26%), 1 nm of aluminum nitride (AlN), and 1.2- m insulating GaN on a 4-H vanadium-doped silicon carbide (SiC) substrate. The AlN layer has the effect of increasing the mobility and is expected to reduce real space transfer into the AlGaN layer at high electric fields [20]. III. EXTRACTION PROCEDURE The complete small-signal circuit proposed for this device is shown in Fig. 1. Lumped components of the intrinsic topology represent the first-order linearization of nonlinear elements in the equivalent-circuit model including a pair of parallel current sources. Both of these are derived from a single nonlinear current source, the first representing a standard transconductance, whereas the second represents a generalized conductance

Fig. 1. Complete small-signal equivalent circuit for a GaN HEMT including intrinsic and extrinsic circuit topologies.

Fig. 2. Reduced equivalent-circuit topology for a “pinched-off” GaN HEMT.

with possible delay. Time delays, indicative of the observed frequency dependence in each of these conductances, are specified with reference to the intrinsic terminal voltages, as depicted in Fig. 1. The extrinsic parasitics include bias-independent eland . Assuming ements that the parasitics are evaluated and deembedded correctly, the remaining bias-dependant intrinsic elements can be evaluated using both the analytical expressions presented in [16] plus the straightforward fitting routine described in this paper. The following outlines the novel procedure for the correct extraction of the entire set of circuit elements. A. Parasitic Pad Capacitance Extraction Parasitic gate and drain pad capacitances of GaN HEMT are generally extracted from conventional “cold-FET” techniques, V, using -parameter measurements below pinched-off bias conditions, namely, . Under these conditions, channel conductivity is negligible and the now passive device exhibits a purely capacitive behavior under low to medium frequencies [21]. For our GaN HEMT, under the pinchoff bias of V, the equivalent-circuit topology of Fig. 2 was deemed to be an adequate electrical representation of the device in this bias state [9]. The star-connected network of gate capacitance elements exploits the symmetrical behavior of the depletion capacitance under the gate [22]. Linear regression fits to the various algebraic -parameter quantities,

BRADY et al.: IMPROVED SMALL-SIGNAL PARAMETER-EXTRACTION ALGORITHM FOR GaN HEMT DEVICES

2

Fig. 3. Measured and modeled Y -parameters (0.2–50 GHz) for a 2 50 m : V and V GaN HEMT under a “cold-FET” bias condition of V : V.

00

= 08 0

=

TABLE I EXTRACTED “COLD-FET” PINCHED-OFF ELEMENTS

as illustrated in Fig. 3, provide values for the individual elements according to the following mathematical expressions: (1) (2) (3) As one can see, the highly linear behavior of the measured admittances justifies the reduced circuit topology of Fig. 2 over the lower frequency band. The extracted capacitances are presented in Table I. It may be noted that a possible parasitic feedback capacitance between the gate and drain terminals has been omitted in the circuit of Fig. 2. In fact, based on geometrical data, estimates of this capacitance indicate values that are a factor of ten down on the pad capacitances, thereby permitting its omission from the equivalent circuit of Fig. 1, and subsequently, Fig. 2. This assumption will be further justified by the observed frequency independence of the extracted intrinsic parameters presented later in this paper. Furthermore, the authors acknowledge that the assumption of intrinsic symmetries, as inferred by Fig. 2, does not necessarily hold for all devices [23]. Certain device structures may also exhibit nonnegligible feedback capacitances [24]. A more generalized extraction approach would be to utilize open dummy structures, as demonstrated on the GaN HEMT in [12] and [13]. However, such structures were not available to the present authors, but techniques of this type should be used whenever these structures are available.

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2

Fig. 4. Distributed gate network for a 2 50 : V and V channel bias condition of V

=00

m

GaN HEMT under open

= 0:0 V.

RC network has been proposed to characterize the electrical behavior of an FET device [25]. However, this model fails to account for any drain–source capacitance associated with the channel, arising from the separation of high electron concentration access regions at the drain and source [17]. Under low bias conditions, this separation becomes small and, thus, a sigat V can be expected. Therenificant increase in fore, a more suitable distributed circuit topology is proposed, as illustrated in Fig. 4. Here, and represent the distributed elements of the drain–source channel resistance and capacitance, respectively, while and account for the equivalent impedance under the Schottky barrier, as described by Dambrine et al. in [25]. From transmission line theory, the impedance matrix of this two-port network is given by

(4)

represents the characteristic impedance and is the product of the transmission line coefficient and gate length of the gate’s equivalent transmission line network. These quantities can be determined from an analysis of the distributed equivalent circuit of Fig. 4, and are given by the following: (5) (6) . Under microwave frequencies and, thus, the equivalent intrinsic impedance matrix simplifies to the following: where

B. Parasitic Inductance and Resistance Extraction Having evaluated the parasitic pad capacitances, an accurate means of characterizing the series access regions of the device was sought. Under open channel conditions, a distributed

(7) Deembedding the extracted pad capacitances from the equivalent circuit of Fig. 1, the complete -parameter representation

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of the measured device, under unbiased “cold-FET” conditions, becomes

TABLE II EXTRACTED Z -PARAMETERS

(8)

(9)

(10) Previous extraction methodologies [26], [27] that avoid the forward gate biasing techniques describe a similar set of equations for the DUT, though without the apparent complication of the , as shown in (8)–(10). Therefore, drain–source capacitance with reference to (8)–(10), the direct extraction approach for the remaining parasitic elements can no longer be applied here. in parallel with the channel reHowever, the interaction of sistance introduces a favorable dispersive behavior into the measured series resistances. Therefore, despite increasing the comeffectively permits the distinction of plexity of the analysis, the channel resistance from the parasitic resistances, as can be mathematically inferred from (8)–(10). Hence, by incorporating this system of equations into a least squares (LS) fitting routine, one can evaluate unique and consistent values for the remaining parasitic elements. The general error function of such an LS fitting routine is given by

(11) The following algorithm now details each step of the proposed novel extraction procedure. Step 1) To improve the efficiency of the LS fitting process, -paramindividual impedance elements of the eter can be estimated as follows:

Fig. 5. Measured and modeled real and imaginary parts of the Z -parameter (0.2–50 GHz) for an unbiased “cold-FET” 2 50 m GaN HEMT.

2

, which are dominated by the the real parts of interaction of with the channel resistances over the entire measured frequency range. At the highest frequencies, both the drain inductance and source inductances begin to dominate the imaginary part of the measured series impedance and are appropriately estimated by (15). An LS fit of (10) to the measured complex -parameter over the measured frequency range reveals the optimum values of these estimated quantities. Table II outlines values for both the estimated and fitted quantities for this step. A comparison of the measured and modeled results of both the real and imaginary components of is given in Fig. 5. This graph also highlights the significant reduction in the measured series output resistance over , as described earlier. The frequency due to fitted and values can now be fixed for the remainder of the extraction process. and source inductance Step 2) The source resistance dominate the real and imaginary parts of at the highest frequencies and can be estimated as follows:

(12) (13) (14)

(16) (17)

(15) where

and quantities subscripted with and denote parameters measured at the lowest, intermediate, and highest frequencies of 0.2, 25.0 and 50.0 GHz, respectively. The estimates given by (12)–(14) are based on an analysis of

A similar LS fit of (9) to the measured complex -parameter reveals the final values of these quantities. The estimated and fitted values are given in Table III. Furthermore, a comparison of the mea-parameter for this step is sured and modeled shown in Fig. 6.


TABLE III EXTRACTED Z -PARAMETERS

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TABLE IV EXTRACTED Z -PARAMETERS


2

Step 3) Finally, estimates of the equivalent impedance pa-parameter are made as follows: rameters of the

(18)

(19)


2

TABLE V EXTRACTED SERIES PARASITIC ELEMENTS

At this stage, all the data required for the complete characterization of the device’s parasitic network has been obtained. Where necessary, values for each individual parasitic element can be determined by performing algebraic operations on the fitted data from Tables II–IV. Table V now outlines the final values for each individual parasitic element, which will be used to determine the measured intrinsic parameters of the device.

(20) C. “Hot-FET” Intrinsic Element Extraction (21)

Under the lower frequencies, the complex impedances presented by the gate leakage resistance and gate capacitance are prevalent. Using the fitted and values from Step 1) and rearranging (8), reasonable estimates of these intrinsic parameters are made according to (18) and (19). Series gate parasitics begin to dominate the measured impedances at the highest frequencies and are estimated according to (20) and (21). A final LS fit of the complex -parameter to (8) provide the optimum values for these quantities, the results of which are shown in Table IV. A graph of this fit is presented on a log scale in Fig. 7 to clearly highlight the outstanding correlation between the measured and modeled results over the measured frequency range.

Values determined for the extrinsic elements can be deembedded from the measured data by a series of straightforward mathematical operations to reveal the measured intrinsic -parameters of the device [25]. Traditionally, equations described in [16] can be used to determine the remaining elements of the intrinsic circuit [26]–[28]. However, the introduction of the drain conductance delay parameter gives an overdetermined system of equations. This problem is depicted in the general equivalent circuit of Fig. 8, which is a simplified form of the intrinsic topology described in Fig. 1. Mathematically unique values can be extracted for a maximum of two intrinsic elements or parameters from each admittance quantity at each measured frequency. This is not so in the case of , which is now described in terms of three parameters as follows:

(22) Therefore, a final fitting routine to (22) is required to evaluate the equivalent values of these parameters at each bias point.

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Fig. 8. Generalized equivalent intrinsic topology of a GaN HEMT device showing the lumped complex admittance quantities in each limb and their associated equivalent-circuit parameters.

0

Fig. 9. Real and imaginary parts of the measured (+) and modeled ( ) S -parameters (0.2–50 GHz) for 2 50 m GaN HEMT at V = 0:0 V and V = 0:0 V.

2

0

Fig. 10. Real and imaginary parts of the measured (+) and modeled ( ) S -parameters (0.2–50 GHz) for 2 50 m GaN HEMT at V = 8:0 V and V = 0:0 V.

2

0

Fig. 11. Extracted intrinsic elements of C ; C , and (0.2–50 GHz) for a 2 50 m GaN HEMT at V = 12:5 V.

g

versus frequency

Fig. 12. Extracted intrinsic elements of C ; C , and = (0.2–50 GHz) for a 2 50 m GaN HEMT at V 20:0 V.

g

versus frequency

2

00:6 V and V

=

Having outlined a detailed algorithm for extracting the SSM of a GaN HEMT, Section IV will now provide a thorough validation of this proposed approach. IV. RESULTS AND DISCUSSION In Section III, the extraction algorithm for the extrinsic parasitics under “cold-FET” conditions was presented. To evaluate the accuracy of the extracted parasitic elements, Figs. 9 and 10 now compare a selection of the measured and modeled -parameters of the device under both of these “cold-FET” bias conditions. Real and imaginary components of these quantities are plotted separately to highlight the excellent correlation between the measured and modeled results over the measured frequency range. These results provide a good indication of the accuracy of the extracted parasitic values thus far. Deembedding all bias independent parasitic components from the measured data, the intrinsic elements were then determined under active multibias conditions. In the case where elements could be evaluated by direct analytical expressions, their unique values were determined over the entire measured frequency range. A selection of these elements extracted over frequency for two different bias points is shown in Figs. 11 and 12. Ignoring measurement errors, it is quite apparent that the extracted elements exhibit clear frequency independence over the measured frequency range. Similar results were observed for the majority of bias points across the bias plane. This result further validates both the chosen topology and the accuracy

2

07:0 V and V

=

of the proposed extraction technique. The real and imaginary for these bias points are also shown in Figs. 13 and parts of 14, highlighting the appropriateness of the output conductance time delay approach. To verify the small-signal behavior of the model, the proposed circuit topology of Fig. 1 was simulated with the extracted values determined using this novel procedure for our GaN HEMT. Table VI outlines a selection of the extracted values for three different bias points over the range of ( 5–0 V). The ability of the model to accurately reproduce the measured data at these varying bias extremes is demonstrated in Fig. 15. Calculation of the error between the measured and


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0

Fig. 13. Measured (+) and modeled ( ) intrinsic output conductance Y (0.2–50 GHz) and associated fitting parameters of g ; , and C for a 2 50 m GaN HEMT at V = 6:0 V and V = 12:5 V.

2

0

0

Fig. 14. Measured (+) and modeled ( ) intrinsic output conductance Y (0.2–50 GHz) and associated fitting parameters of g , , and C for a 2 50 m GaN HEMT at V = 7:0 V and V = 20:0 V.

2

0

TABLE VI EXTRACTED INTRINSIC ELEMENTS FOR 2

2 50 m GaN HEMT 2

0

Fig. 15. Measured ( ) and modeled ( ) S -parameters (0.2–50 GHz) for 2 50 m GaN HEMT for bias points (a) V = 0:0 V and V = 8:0 V, = 3:0 V and V = 20:0 V and (c) V = 5:0 V and (b) V V = 6:0 V.

2

modeled results is determined from the following generalized error expression [29]:

% (23) where and denote the number of bias and frequency points, respectively.

0

0

In Fig. 16, the variation of all intrinsic parameters over the bias plane is presented, in particular, the drain–source capacin Fig. 16(c). In saturation the high-field channel itance region extends towards the drain, separating the highly doped source and drain access regions in an electrostatic sense, and develops [30]. Under decreasing bias and a resulting bias, this separation becomes smaller, thus reincreasing ducing this separation and giving rise to a sudden spike in the ex, particularly around , as shown. In retrotracted around the “cold-FET” spect, the behavior of the extracted V and V highlights the rebias point of quirement of the improved extraction methodology presented in this paper. The extracted capacitance at this bias is of the order of 15 times the magnitude of that extracted in the saturation region and, thus, its inclusion in the presented distributed topology of Fig. 4 is well justified. Overall, the behavior of the all-extracted elements is generally smooth over the bias plane, which

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Fig. 16. Extracted intrinsic elements for 2


2 50 m GaN HEMT over the measured bias plane.

is a favorable feature tending to verify the reliability of values determined by optimization-based extractions. These results are also consistent with those presented in previous publications on similar devices [11], [13]. A physical explanation of the drain time delay can be inferred from an analysis of its behavior over the bias plane. At biases exceeding the saturation voltage, the edges of the depletion layer are no longer largely confined to the region beneath the gate contact. In particular, the drain side of the depletion region extends steadily toward the drain terminal under increasing drain voltage. Correspondingly, a similar monotonic increase in the extracted drain delay can be observed in Fig. 16(e). Hence, one can postulate that it represents a delay in the drain current’s response to the drain voltage arising from delays associated with the partially depleted high-field region. This essentially constitutes a transmission line effect, which, from a compact equivalent-circuit point-of-view, justifies the form of (22). Nonetheless, a more detailed explanation, particularly from researchers within the physical modeling community, may be warranted. , in terms of modeling accuracy, can The effectiveness of be demonstrated by a comparison of the error in with and

without its inclusion in the circuit of Fig. 1. Applying (23) to -parameters across the entire all the measured and modeled bias plane, the authors have found that the error is reduced from 11.2% down to 3.5%. Several accounts have detailed bias dependencies in the acand of GaN-based transistors [31], [32]. cess resistances Their importance and subsequent impact on the linearity performance in terms of the measured transconductance and cutoff frequency has been demonstrated [33], [34]. It should be noted that the access resistances extracted for this device were bias independent. The values determined under “cold-FET” conditions were found to be highly sufficient in reproducing the measured -parameters of our device. Furthermore it is quite clear from Figs. 11 and 12 that the extracted intrinsic elements remained independent of frequency over the active bias plane. This is a clear indication of the accuracy of the model parasitics and, therefore, the use of bias-independent access resistances appears to be well founded. Although it can be argued that the inclusion of a time delay in the output conductance could be “masking” nonlinearities in the access resistances, the authors found that its omission resulted in negative resistances, which is both incon-


sistent with device physics and unsuitable for implementation in large-signal simulation environments. The efficiency of the proposed extraction algorithm is demonstrated by the fact the entire small-signal performance of the device across the I–V plane (125 bias points) was determined in under 30 s. The accuracy and closeness of the parameter estimates, as highlighted in Tables II–IV, and the overall systematic approach of the extraction procedure contributes to its efficiency. Simulations were performed in a MATLAB simulation environment on a 1.65-GHz computer. Our technique has recently been applied to another 2 50 m GaN HEMT from a separate development process. Modeling accuracy, comparable to that presented in this paper, has been observed for this device including identification of almost identical delay phenomena in the output conductance. Straightforward scaling rules, similar to those proposed in [35], have permitted the extension of the proposed extraction methodology to wider device structures. Preliminary fitting results from a 2 125 m GaN HEMT have been very promising, indicating the robustness of the proposed extraction methodology. V. CONCLUSION A highly accurate and robust small-signal parameter extraction algorithm has been presented for a 2 50 m GaN HEMT device. All parasitics have been evaluated using traditional “cold-FET” techniques that utilize a modified distributed channel model, which accounts for the significant drain–source capacitance observed under these bias conditions. Furthermore, the requirement to suppress the channel resistance by forward biasing the gate terminal is avoided. Straightforward expressions are introduced to estimate these parasitic quantities and subsequently improve the efficiency of the systematic optimization procedure. A time dependency in the output conductance has been introduced into the equivalent-circuit topology. It effectively represents a time delay at the output and accounts for the observed increase in phase delay at higher frequencies. A simple optimization procedure has been described to evaluate its behavior across the bias plane. The extracted intrinsic elements have also shown appropriate frequency independence over the entire measured frequency range. The validity of all extracted values has been verified with excellent correlation between the measured and modeled -parameters up to 50 GHz. ACKNOWLEDGMENT The authors would like to sincerely thank Dr. M. Uren and D. Hayes, both with QinetiQ Ltd., Hampshire, U.K., for supplying the measured small-signal parameter data. REFERENCES [1] S. N. Mohammad, A. A. Salvador, and H. Morkoç, “Emerging gallium nitride based devices,” Proc. IEEE, vol. 83, no. 10, pp. 1306–1355, Oct. 1995. [2] S. T. Sheppard, K. Doverspike, W. L. Pribble, S. T. Allen, J. W. Palmour, L. T. Kehias, and T. J. Jenkins, “High-power microwave GaN/ AlGaN HEMT’s on semi-insulating silicon carbide substrates,” IEEE Electron Device Lett., vol. 20, no. 4, pp. 161–163, Apr. 1999.

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Ronan G. Brady (S’07) was born in County Cavan, Ireland, in 1982. He received the B.E. degree in electronic engineering from University College Dublin (UCD), Dublin, Ireland, in 2003, and is currently working toward the Ph.D. degree in characterization and modeling of microwave devices at UCD. He is currently with the RF and Microwave Research Group, UCD. His research interests include device characterization and nonlinear modeling with an emphasis on the accurate prediction of dispersion phenomena in GaN-based devices.

Christopher H. Oxley received the B.Sc. degree in physics from the University of London, London, U.K., in 1969, and the Ph.D. degree from De Monfort University, Leicester, U.K., in 2005. In 1969, he joined the Allen Clark Research Centre, Caswell, U.K. He recently joined the faculty of the Computing Science and Engineering Department, De Montfort University, Leicester, U.K. He has authored or coauthored over 70 scientific papers. He holds four patents. Throughout his career, he has been involved in the area of microwave devices/circuits. His current interests include thermal imaging of electronic devices, electrical characterization/modeling of III–V and III nitride devices and electrical properties of conducting fabrics. Dr. Oxley is a Fellow of the Institution of Engineering and Technology (IET).

Thomas J. Brazil (M’86–SM’02–F’04) received the B.E. degree in electrical engineering from University College Dublin (UCD), Dublin, Ireland, in 1973, and the Ph.D. degree in electronic engineering from the National University of Ireland, Dublin, Ireland, in 1977. He then joined Plessey Research, Caswell, U.K., where he was involved with microwave subsystem development prior to returning to UCD in 1980. He is currently a Professor of electronic engineering and holds the Chair of Electronic Engineering at UCD. His research interests are in the fields of nonlinear modeling and characterization techniques at the device, circuit, and system levels. He also has interests in nonlinear simulation algorithms and several areas of microwave subsystem design and applications. He has authored or coauthored numerous publications in the international scientific literature in these fields. Prof. Brazil is a Fellow of Engineer Ireland and a Member of the Royal Irish Academy. From 1998 to 2001, he was an IEEE Microwave Theory and Techniques Society (IEEE MTT-S) Worldwide Distinguished Lecturer in high-frequency computer-aided design (CAD) applied to wireless systems. He is currently a member of the IEEE MTT-1 Technical Committee on CAD.