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{fluo, ma}@ece.arizona.edu, http://www.ece.arizona.edu/~ma/ISDL.htm. Abstract—This paper describes an integrated switching power converter with a hybrid ...
An Integrated Switching Power Converter with a Hybrid Pulse-Train/PWM Control Feng Luo and Dongsheng Ma Department of Electrical and Computer Engineering The University of Arizona Tucson, AZ 85721, USA {fluo, ma}@ece.arizona.edu, http://www.ece.arizona.edu/~ma/ISDL.htm Abstract—This paper describes an integrated switching power converter with a hybrid control scheme. The design incorporates a pulse-train control for fast and smooth transient response, and an analog PWM control for low ripple voltage regulation. The converter was designed with a TSMC 0.35 µm CMOS N-well process. The simulation results show that, with a supply voltage of 3.3 V and a maximum load power of 225 mW, the output voltage is well regulated with a ripple voltage down to 6 mV. A fast and smooth transient response is observed with less than 5-µs settling time. The maximum power efficiency is 92.4%with a power range of 30 mW to 225 mW. The entire chip area is 1.69 mm2, including on-chip power transistors. The research provides an effective solution to highperformance integrated power converter designs.

I. INTRODUCTION In recent years, the development of advanced VLSI systems poses new challenges on power supply designs. Such a supply is expected to have fast transient performance to immediately response to sudden load changes of multimode systems. In addition, it should maintain low ripple voltage all the time for clean power delivery to all circuit modules and devices. A switching power converter is considered as one of the best candidates due to its high efficiency and voltage conversion flexibility. However, for a conventional PWM controlled switching converter, certain drawbacks exist for these new applications.

In this paper, a new switching power converter with a hybrid control scheme is proposed. It incorporates an improved pulse-train control scheme for fast and smooth transient response and a PWM control scheme for fine voltage regulation. The two schemes can transit seamlessly depending on the dynamic operating status. The rest of the paper is organized as follows. Section II briefly reviews the prior arts of the pulse-train technique. System architecture and operation principle of the hybrid controlled switching converter are discussed in Section III. The design idea will be verified by post-layout HSPICE simulations in Section IV. Finally, we conclude our work in Section V. II.

REVIEW OF THE PRIOR PULSE-TRAIN TECHNIQUE

Output Vol tage Vo

For a voltage-programming PWM converter, due to the existence of the complex poles in the loop gain transfer function, it is very difficult to design the compensation network to achieve a wide loop-gain bandwidth and thus fast response [1]. For a current-programming PWM converter, although it has two separated poles in transfer function and wider loop-gain bandwidth, special current sensing circuit is required and ramp compensation has to be made to avoid sub-harmonic oscillation [2]. For improved transient performance, a pulse control technique is introduced in [3]. By assigning two different pulses instead of a constant pulse as the control signal of the power switches, the converter’s transient performance is much improved. However, because both two pulses have fixed duration, it is almost impossible

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to ensure the instantaneous duty ratio in each switching cycle as same as the desired value in a traditional analog PWM controlled converter. As a result, the output voltage toggles around the desired regulation level with large ripple voltages. In addition, with the long fixed pulse durations, overcharging or over-discharging actions can easily occur during the dynamics and lead to large damping behavior at the output.

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Fig. 1 The pulse-control scheme proposed in [3].

The original pulse-control technique was first proposed in [3]. Fig. 1 illustrates the typical power pulse control scheme. In this technique, the converter is regulated by two different power pulses, based on the real-time output voltage level. When the output voltage is higher than the desired

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Accordingly, we divide the output voltage into five different regions. In Region I, the output voltage at the instant “A” is much lower than the desired level. A large amount of power is needed to charge up the capacitor at the output. The controller will assign a long-duration “Extreme High” pulse to ensure this action with fast transient speed. At “B”, the output voltage is still low, but very close to the desired level. To avoid overshooting, a smaller “High” pulse will be used to charge up the output in a moderate manner. At “C”, the converter’s output has been in a relatively accurate regulation range. An analog PWM control will be activated to determinate the duty ratio of the converter with infinite resolution. This ripple voltage becomes much smaller due to the accurate duty ratio and an assigned much faster switching frequency (Nfs). At the instant of “D”, the output voltage of the converter is higher than the level for the PWM operation. A “Low” pulse will be assigned to the converter. Because the equivalent duty ratio is lower than the one in PWM control, it makes the output voltage drop back to the desired level. If the output voltage is much higher than the desired level (at “E”), one “Extreme Low” pulse will be employed with even smaller duty ratio to allow the output voltage drop down faster. The difference between the case “D” and “E” is that the duty ratio in “D” is chosen to be larger than that in “E” to avoid over-discharging on the output capacitor.

regulation voltage, low-power “sense pulses” are used to drive the power switches such that less power will be delivered to the output. On the other hand, when the output voltage is lower than the desired level, instead of sense pulses, high-power “power pulses” are employed. With the longer turn-on time, more power is delivered to the load. The ratio of the on-time durations of a power pulse to a sense pulse is chosen by optimizing both the output voltage ripple and the load power range from a full power load to the lightest possible load. A deeper thought on the control scheme concludes the following design tradeoff: during the startup or load transient period, the bigger power pulses deliver more energy and thus help get faster response, while the smaller sense pulses can provide less severe damping behavior. However, in the steady state, these fixed-duration digital pulses lead to poor resolution of the output level. In this case, if the sense pulse is chosen to be too long, the ripple at the output voltage will be very large and noisy. If it is chosen to be too short, small ripple can be obtained, but the sense pulse will have poor control on large-signal damping behavior. Pulse s ignal Error s ignal

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Fig. 2 The pulse-train control scheme proposed in [4].

Another adaptive pulse-train technique was purposed by one of the authors in [4]. Fig. 2 shows the timing diagram. The error signal (or called as duty ratio signal) of the converter is modulated by pulse train through an AND gate. As a result, the pulse train signals charge the inductor with a few pulses instead of one single continuous period. An internal control signal can enable pulse-train function for high-resolution regulation in steady mode and disable it for the fast dynamic response in transient mode. However, This design only employs constant pulse-train and does not consider any inductor current information, which slows down the load transient response.

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Fig. 3 The proposed hybrid control scheme

Fig. 4 depicts the block diagram of the proposed pulsetrain control scheme part. The output voltage is online sensed to determine the instantaneous voltage region and the type of pulse or the duty ratio (for PWM control) to be assigned in the next cycle. This control scheme can achieve very fast transient response, smooth dynamics and small ripple voltage. Pulse-Train Control Loop Pulse-Train

III. THE PROPOSED SWITCHING CONVERTER DESIGN

Pulse Selector

A. The proposed hybrid control scheme To overcome the drawbacks in the existing designs, we proposed a new hybrid control scheme, incorporating both an improved pulse-train control and an analog PWM control. Fig. 3 illustrates the operation of the hybrid control scheme. In this scheme, the mode of operation is highly determined on the instantaneous output voltage level of the converter.

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Fig. 4 Block diagram for the proposed pulse-train control part

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Fig. 5 Block diagram of the proposed converter with a hybrid pulse-train/PWM control

by the control signal from the buffer in Fig. 5. The node X is connected to the drain of the power transistor Mp in Fig. 5. Once Mp is turned on, Mp1 is also turned on. In this case, Mp and Mp1 have the same dc biasing voltages. Therefore, the current through Mp is proportional to that of Mp1 according to the scaling ratio N. Mp1 is designed to be much smaller than Mp, and N>>1. The power loss by the sensing resistor is scaled down by n times.

B. System Implementation Fig. 5 shows the system block diagram of our proposed converter. In this proposed hybrid control scheme, we have the flexibility to operate the converter with either pulse-train control, or PWM control or both. In PWM mode, the error amplifier generate a duty ratio at a much higher switching frequency to control the switching actions of the power transistor Mn and Mp. In pulse-train control mode, a series pulse train will be generated based on the real-time voltage level. The type of the pulse is determined by the instant voltage region where the output voltage is located. Two external control signals S0, S1 are used to help tune the switching frequency for test purpose.

IV. SIMULATION RESULTS The proposed converter was designed and simulated with TSMC 0.35 µm CMOS N-well process. The entire design requires a silicon area of 1.69 mm2, including all the pads and power transistors.

Vdd

Post-layout HSPICE simulations are conducted. In this design, one 4.7-µH inductor and a 10-µF filtering capacitor are employed in the power stage. The ESR of the capacitor is 100 mΩ. The nominal input voltage of the converter is 3.3 V, while the output is regulated at 1.5 V with a maximum power of 225 mW. The power efficiency of the converter is simulated first. As shown in Fig. 7, with a range of load power from 30 mW to 225 mW, the maximum efficiency is 92.4%. In Fig. 8, the ripple voltage of the converter in the pulse-train mode is controlled below 25 mV, while a ripple voltage of 6 mV is observed in the PWM mode. Fig. 9 shows the load transient performance of the proposed converter in pulse-train control mode. As illustrated in the figure, a load change from 100 mA to 75 mA occurs at 250 µs. The closeup results on the output voltage and inductor current in Fig. 10(a) and 10(b) demonstrate a smooth and stable transient performance. The output voltage variation due to this transition is less than 30 mV with a settling time of less than 5 µs. The effectiveness of the high and low pulse train is demonstrated through the fast and smooth dynamics of the converter. As a comparison, a conventional PWM controlled converter is simulated. As shown in Fig. 11, the converter takes 150 µs to reach the steady state with a voltage variation of more than 110 mV.

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Fig. 6 Schematic of current sensing circuit

To facilitate the PWM control and to prevent too large current damage the power components, a very cost-effective current sensing circuit is employed with transistor scaling technique [5, 6]. Fig. 6 shows the circuit schematic, which is a modified version of a BiCMOS counterpart [5]. Here, the transistors M3 and M4 constitute a current mirror in sinking equal currents into two identical transistors M1 and M2, if the transistors are well matched; the voltages at the source of M1 and M2 are equal, forcing the drain voltages of Mp, Mp1 and Ms1 to be equal. Mp and Mp1 work as two switches controlled

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Fig. 10 The simulated load transient response with pulse-train control: (a) the close-up look at the output voltage, and (b) the inductor current.

Fig. 7 The simulation result of power efficiency at the steady-state.

Fig. 11 The simulated load transient response with PWM control: (top) the output voltage, (bottom) the close-up look at the output

V. CONCLUSIONS A new switching power converter IC with hybrid pulsetrain/PWM control is presented. With the proposed architecture and control scheme, the performances on ripple voltage and transient response are both improved. Detailed circuit implementation is discussed. The results on both pulse-train and PWM control successfully verify the design idea. It provides an effective solution to high performance power converter designs.

Fig. 8 The simulated output ripple voltage: (top) in pulse-train control mode, (bottom) in PWM control model.

REFERENCES [1]

[2]

[3] Fig. 9 The simulated load transient response with pulse-train control: (a) the output voltage, and (b) control signal at the load. [4]

[5]

[6]

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W-H. Ki, “Signal flow graph in loop gain analysis of dc-dc PWM CCM siwtching converters”, IEEE Transactions on Circuits and Systems Part I, No.6, pp.644-654, Jun. 1998. W-H. Ki, “Analysis of subharmonic oscillation of fixed-frequency current-programming switch mode power converters”, IEEE Transactions on Circuits and Systems Part I, Vol. 45, No. 1, pp. 104108, Jan. 1998 M. Ferdowsi, A. Emadi, M. Telefus, and C. Davis, “Pulse Regulation Control Technique for Flyback Converter”, IEEE Transactions on Power Electronics, Vol. 20, No.4, pp. 798-805, Jul. 2005. C. Zhang, D. Ma, and A. Srivastava, “Integrated Adaptive DC/DC Conversion with Adaptive Pulse-Train Technique for Low-Ripple Fast-Response Regulation,” International Symposium on Low Power Electronics and Design (ISLPED), pp. 257-262, 2004. W-H. Ki, “Current sensing technique using MOS transistors scaling with matched bipolar current sources,” U.S. Patent 5757174, May 1998. D. Ma, W-H. Ki, C-Y. Tsui, and P. K.T.Mok, “Single-Inductor Multiple-Output Switching Converters With Time-Multiplexing Control in Discontinuous Conduction Mode,” IEEE Journal of SolidState Circuits, Vol. 38, No.1, pp. 89-100, Jan. 2003.