and p-MOSFETs biased in the substrate-enhanced gate ... - diegm

IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 49, NO. 5, MAY 2002

787

Damage Generation and Location in n- and p-MOSFETs Biased in the Substrate-Enhanced Gate Current Regime Francesco Driussi, David Esseni, Member, IEEE, Luca Selmi, Member, IEEE, and Fausto Piazza

Abstract—This paper analyzes MOSFET degradation in the regime of hot carrier injection enhanced by substrate bias Substrate-Enhanced Gate Current (SEGC). The results are compared with the damage generated during conventional Channel Hot Carrier (CHC) stress experiments. The investigation was carried out on state of the art n+ -poly n-MOSFETs and p+ -poly p-MOSFETs, and it includes both a detailed characterization of standard electrical parameters (i.e., threshold voltage, drain current and linear transconductance) and a spatial profiling of stress-induced interface states. Our results reveal that the application of a substrate bias enhances degradation on both n-MOS and p-MOS devices and spreads toward the center of the channel the spatial profile of the damage. For a given gate current and oxide field in the injection region, the total amount of the generated damage is quite similar in both cases, but in the SEGC regime, the spatial distribution of generated traps is more distributed along the channel. Index Terms—Channel Hot Carrier (CHC), CHISEL, damage profiling, Flash memories, hot carrier degradation, substrate bias.

I. INTRODUCTION

T

HE application of a substrate bias to n-MOSFETs activates the phenomenon of Substrate-Enhanced Gate Current (SEGC) also referred to as Channel-Initiated Secondary Electron (CHISEL, [1]–[5]), which can largely overcome the contribution to the gate current given by of the conventional channel hot electron (CHE) injection. These days, this phenomenon is routinely observed in deep sub- m n-MOSFETs, and, very recently, SEGC in pMOS devices has been also reported on the gate [6]. In fact, the dependence of the gate current and the correlation between and the substrate voltage revealed that the increase of with the substrate current has in p-MOSFETs the same origin as in n-MOS tranbias sistors [6], [7]. In both nMOS and in pMOS devices, the physical mechanism increase is a chain of impact ionization responsible for the events leading to carrier pair generation deep inside the MOS depletion region. The generation of these substrate hot carriers and their subsequent injection into the gate oxide are dramatically enhanced by the substrate voltage. Manuscript received July 27, 2001; revised November 28, 2001. This work was supported in part by the UE (ULIS W.G.) and the Italian CNR (Madess II). The review of this paper was arranged by Editor G. Groeseneken. F. Driussi, D. Esseni, and L. Selmi are with the DIEGM, 33100 Udine, Italy (e-mail: [email protected]). F. Piazza is with the ST Microelectronics, Agrate Brianza, Italy. Publisher Item Identifier S 0018-9383(02)03542-6.

The applicative interest of this mechanism for future fast and low power Nonvolatile Memories (NVM) has been repeatedly demonstrated [4], [8]–[10]. Hot carriers possibly injected into the gate oxide generate and degrade the electrical characteristics interface traps of MOS transistors. Thus, the larger gate current provided by CHISEL with respect to conventional CHE is expected to induce a faster degradation for given gate and drain voltages. However, a fair comparison for stress-induced degradation between CHE rather than and CHISEL should be performed at the same and . This is particularly true from the at the same viewpoint of NVM programming, where the relevant reliability figure is the damage produced by a given amount of injected charge. Furthermore, the impact of interface states and trapped charges on the device current–voltage ( – ) characteristics depends significantly on the spatial location of the damage [11], [12]. Since it has been suggested by numerical simulations that CHISEL injection should be more distributed toward the channel region than conventional CHE one [13], [14], it is not straightforward to draw even a simple qualitative conclusion on the relative severity of the overall device degradation in the two hot electron injection regimes. This paper addresses these issues and presents a detailed comparative analysis of hot carrier degradation in the CHE and CHISEL regime. In particular, constant-bias stress experiments were carried out on n- and p-MOSFETs to analyze the evolution of the generated damage. At each stress step, a complete characterization of the most relevant MOSFETs parameters was carried out, including charge-pumping (CP) measurements [15] suitable to extract the spatial profile of the generated interface traps [16]–[18]. The degradation induced by CHE and CHISEL stress condiand stress tions have been compared both at the same voltages and at the same stress . Our experimental results confirmed that hot carrier injection in the SEGC regime is more distributed toward the center of channel than in CHE regime where the generated damage is concentrated at the drain side of the channel [19]. We also show that, for a given stress , in the SEGC regime the damage produced at the center of the channel gives a larger relative contribution to the overall degradation of the – characteristics than in CHE stress conditions, where the degradation is mainly due to the damage at the drain end of the channel.

0018-9383/02$17.00 © 2002 IEEE

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II. SUBSTRATE ENHANCED GATE CURRENTS Experiments were performed on n- and p-MOSFETs fabricated with 0.35 and 0.25 m dual-gate CMOS technologies featuring a gate oxide thickness of 7 and 5 nm, respectively. Devices with different drain engineering options (i.e., LDD extensions or abrupt junction profile) have been also considered. A. nMOSFETs Gate Currents Fig. 1(a) shows the gate current characteristics of the LDD nm for different substrate voltages. nMOS devices with is clearly observed as the substrate A significant increase of is raised above 0 V. voltage with is due to tertiary electron injecThe increase of tion, which clearly overcomes the CHE contribution. As a result, the maximum of the gate current occurs for progressively as is increased resulting in a tighter correlation lower and , which has been recognized as a signature between of the CHISEL regime [20], [5], [21] B. pMOSFETs Gate Currents Fig. 1(b) shows gate current characteristics of non-LDD pMOSFETs. At zero substrate bias, we observe the well-known -filled symbols) due to positive electron gate current ( secondary electrons generated by impact ionization of channel component drastically drops for larger hot holes; this is raised, the body effect increases the than 2.5 V. When curves shift to larger values of . threshold voltage and Furthermore, secondary electrons are more efficiently deflected decreases, eventoward the substrate and the maximum tually becoming undetectable. approaches approximately 2.8 V, a negative gate curAs -open symbols) is observed which exhibits rent component ( a bell shaped behavior similar to that of the substrate current as until the oxide field becomes large enough to a function of induce tunnel injection of electrons from the gate which leads increase at larger than V. By applying the to the characterization technique developed in [5], based on the reand , we could unambiguously attribute lation between to tertiary holes generated in the substrate by the secondary electrons [6], i.e., to an impact ionization feedback mechanism complementary to the one responsible for the gate current enhancement in n-MOSFETs. III. CHARACTERIZATION EXPERIMENTS A wide set of measurements was performed after each step of electrical stress. Conventional device parameters such as , maximum linear transconductance threshold voltage , and linear drain current were routinely monitored. CP experiments were used to have a direct determination . of stress-induced interface states Furthermore, stress experiments have been carried out to inspatial profiles in either CHISEL vestigate differences of or CHE injection regimes. To this purpose, CP measurements with constant slew rate and variable base and top levels ( and , respectively) were used. In the following, the key assumptions of this characterization technique are briefly summarized in order to better understand the physical meaning of the results discussed in Sections IV and V.

Fig. 1. (a) Gate current of the LDD nMOSFETs used in this work for different substrate voltages and for V 4:5 V (W=L = 100=0:5 m). (b) Gate currents of the non-LDD pMOSFETs, featuring t = 5 nm (W=L = 500=0:5 m) for V = 3:5 V and different substrate voltages. Filled symbols are positive I due to electron injection. Open symbols are negative I due to hole injection.

=

0

A given region of the channel at an abscissa contributes if is lower than the local effective flat-band voltage [15]) and is larger than the local threshold voltage . In n-MOSFETs and progressively grow from the source-drain regions to the center of the channel [22], [18] and it is therefore possible to modulate the channel zone and of that contributes to the CP current by changing is increased for a given the CP pulse. In particular, when , the CP current tends to a fairly constant value , as shown in the experimental curves of Fig. 2, corresponding to the contribution of the entire channel. When charge-pumping measurements are performed at constant slew-rate (SR), the emission and recombination times are constant, so that, assuming that the original trap distribution at the Si-SiO interface of the virgin device is uniform along the is proportional to the length of the pumped channel [18], versus characregion. This makes it possible to use the function [16]. teristics (Fig. 2) to extract the profile does not change after stress Assuming that the the stress-induced interface states, CP and indicating with current variations after stress are given by to (

(1)

DRIUSSI et al.: DAMAGE GENERATION AND LOCATION IN n- AND p-MOSFETs

(

)

Fig. 2. Charge-pumping current curves of a virgin I and stressed . The stress-induced variation of the charge-pumping n-MOSFET I I I is also shown. The frequency and slew rate current I of the CP pulses are f Hz and V/s, respectively. V V. In the qualitative sketch are shown the local threshold V and Flat-Band V voltages in a n-MOSFET along the channel. Note how it is possible to modulate the region contributing to charge-pumping current by varying the top and the base levels of CP pulse, V and V , respectively.

(

(1 = [ = 05 ( )

)

0 ]) = 2 1 10

SR = 4 1 10

789

( )

where and are the abscissas at which and , respectively, and it is implicitly assumed at the source side of the channel is neglithat stress-induced gible. Inverting this equation, we find the lateral distribution of generated traps as [16] (2) is known from the virgin device. This techwhere nique was used to extract the generated trap distribution both in nMOS and pMOS devices as described in Sections IV and V. IV. nMOS DEGRADATION In this section, the degradation induced by CHISEL and CHE in n-MOSFETs are studied and compared either at the same stress bias or at the same stress . In the former case, a given and values are used for different substrate set of stress and are adjusted so as to voltages, while in the latter, at the different . maintain the same A. Constant Drain Voltage Experiments Stress experiments at constant bias were carried out on nMOSFETs in the two injection regimes. Fig. 3 illustrates the calculated from CP current variation versus characteristics as in Fig. 2 at the maximum . Since is proportional to the total number of stress induced interface states, Fig. 3 shows that the application of a substrate bias enhances trap generation, consistently with the shown in Fig. 1(a). As can be seen by comparing increase of generation due Figs. 1(a) and 3, the relative increase in application is smaller than the corresponding relato a increase, but this is not totally unexpected given the tive generation on the hot well-known sublinear dependence of dependence of carrier fluence [23]. Above threshold, the and is weaker in the CHISEL than in CHE case. along the The spatial distribution of stress-induced Si-SiO interface corresponding to the experiments of Fig. 3

(1 )

Fig. 3. Charge-pumping current increase I of LDD nMOSFETs versus stress gate voltage V . Stress time is 10 s, and stress bias is V : V, V (filled symbols) and V (open symbols). W=L = : m, t nm.

=0 =7

j j=2

= 45 = 20 0 5

is shown in Fig. 4 As expected, a sharp degradation peak in proximity of the drain is observed in the device stressed with CHE [Fig. 4(a)]. In the SEGC regime, besides the increase , we also note a shoulder of the degradation of generated profile that emerges toward the channel. The amplitude of this shoulder tracks the increase of the main degradation peak during stress time [Fig. 4(b)]. The importance of the shoulder with respect to the peak in profile, that is, the fraction of traps generated in the the channel with respect to those at the drain, depends on stress is decreased and bias conditions and tends to increase as increased. By changing the stress bias, it is thus possible to induce different profiles of trap generation. However the degradation peak at the drain end of the device never disappears. This is not unexpected because on the one numerical simulations show that the hand even at competing effect of the reversed oxide field on the large vertical drop accelerating the electrons toward the Si-SiO interface results in a peak of hot carrier injection in proximity of the drain-end of the channel also in the CHISEL regime [13], [24]. triggers an injection On the other hand, the application of of tertiary electrons which adds to conventional CHE, thus producing a degradation which adds to the CHE induced damage. A confirmation of the fact that the damage is more distributed toward the channel in the CHISEL regime can be obtained from . In fact it is the degradation of the drain current reduction known that in short-channel LDD MOSFETs the is most sensitive to generated in the at relatively low (i.e., the intrinsic channel because the channel resistance resistance of the MOS transistor) is much larger than the . At large parasitic source and drain series resistance values, instead, the relative importance of increases and becomes very sensitive to interface states generated in the source-drain regions below the spacers, which increase values [25], [26]. measured at Fig. 5(a) reports the stress-induced versus the increase of for the CHISEL low and at high are compared and CHE stress conditions. Since the , then we are comparing the degradation for a given . The data reported in produced by the same amount of total

790


Fig. 4. (a) Lateral profile of generated trap distribution of LDD nMOSFETs with t nm stressed in the CHE regime (V : V, V : V and jV j V). Generated damage is concentrated at the drain end of the channel. (b) Lateral profile of generated trap distribution of LDD nMOSFETs with t nm stressed in the CHISEL regime (V : V, V : V and jV j : V). A clear shoulder of generated traps toward the center of the channel is observed. The coordinate x is the relative lateral position along the Si-SiO interface from the drain end to the middle of the channel.

=7 =0 =7 =20

= 45

= 45

= 30

= 30

Fig. 5(a) correspond to stress time that induce only very small shifts (below 50 mV) to be sure that reduction is mainly rather than charge trapping in the due to stress-induced oxide. , degradation is larger at low During stress at high than at high , confirming the significant damage inside the degradation is larger at channel. In CHE regime, instead, V and mainly due to damage below the spacer as expected for LDD devices [25], [26]. Furthermore, we see that degradation for (filled symbols) is strongly increased for with the substrate voltage whereas (open symbols) is very similar for different . Qualitatively similar results [see Fig. 5(b)] were found at all stress gate voltages. degradation confirm that the In summary, these results of application of a substrate bias results in a trap generation that is more distributed along the channel than in conventional CHE conditions and support the indication of a broader spatial distribution of the gate current obtained by the Monte Carlo simulations of [13], [14]. B. Constant Gate Current Experiments One of the most common applications of CHISEL injection is in the field of NVM, where it provides a viable alternative to

(1

) 1

=1

Fig. 5. (a) Drain current degradation I =I monitored at low (V V) and high (V V) gate voltages versus I for LDD nMOSFETs with t nm (W=L = : m). For a given I , degradation in the channel (monitored by I =I at low V ) is much more sensitive to V than degradation at the channel edge (monitored by I =I at high V ). Stress V : V and stress V : V. (b) Drain-current degradation I =I monitored at low (V V) and high (V V) gate voltages versus I for LDD nMOSFETs with t nm (W=L = : m). Stress V : V and stress V : V.

=7

= 45 (1 ) 1 =45

=4

= 20 0 5 1

= 25 =1 =7 =35

1

1

=4

= 20 0 5

CHE injection for low-voltage low power operation. In order to compare CHISEL and CHE degradation in bias conditions relevant for NVM applications, we carried out stress experiments and maintaining an approximately constant elecat the same tric field in the gate oxide in proximity of the injection area. To and adjusted to obtain the this purpose we set A/ m for different . same Fig. 6 shows the CP current variations and the maximum at linear transconductance degradation ( mV) versus stress time for three different biases having the pA) for n-MOSFETs with same gate current ( m. It is interesting to note that, when stress is kept constant, CP currents and transconductance variations are quite bias. The slight increase of the similar for the different slope of the curves was not observed during constant voltage stress experiments [19]. Therefore, rather than a peculiar feature of the CHISEL regime it appears to be related to the reduced applied to maintain constant. Fig. 7 reports spatial profiles of the damage generated at s during the constant stress experiments. As expected from data in Fig. 6, the area below the curves (i.e., the total ) is essentially the same but a shoulder of the stress-induced profile extending toward the channel emerges at large as in the case of constant experiments (Fig. 4), confirming


(1 ) ) 3 1 10

Fig. 6. Charge-pumping current increase I and degradation of maximum linear transconductance g =g during stress experiments on LDD nMOSFETs whit t nm. The stress bias was chosen to yield approximately the same value of gate current (I A/m) for the different V . W=L = : m.

= 20 0 5

Fig. 7.

(1 =7

(1 = 20 0 5

)

=1

Fig. 8. Drain current degradation I =I monitored at low (V V) and high (V V) gate voltages versus I for LDD nMOSFETs with t nm (W=L = : m) stressed at the same gate current. For a given I , degradation in the channel (monitored by I =I at low V ) is enhanced by V , while degradation at the channel edge (monitored by I =I at high V ) is slightly reduced by the decrease of V that reduces the CHE contribution to I degradation.

1

=7 1

=4

1

1

Lateral profile of generated trap distribution in LDD nMOSFET with

= 7 nm. Stress bias voltages are such that the stress gate current is I 3 1 10 A/m for all experiments. Stress time is 2000 s.

t

791

a broad distribution of damage. A qualitatively similar behavior was observed at shorter stress times. degradation like the one reported in An analysis of experiFig. 5(a) has been carried out also on the constant ments and consistent results were found. Fig. 8 shows that changes at low (essentially due to the channel degradation) , while at high increase upon application of (sensitive to the damage below the spacers) is reduced for because of the corresponding lower stress . A more severe degradation of the spacer’s region in CHE conditions is also confirmed by a larger substrate current reduction during stress (not shown) than in CHISEL regime. This is caused by an increase of series resistances decrease of across the channel [27]. that reduce the effective V. pMOS DEGRADATION Constant bias stress experiments were performed also on and pMOS devices. Fig. 9 reports the corresponding . The substrate voltage enhances considerably both generation and positive charge trapping in the oxide. Stress conditions correspond approximately to the maximum Secondary ( V, Electron Injection (SEI) for V) and either maximum hole injection ( V,

1

Fig. 9. I (open symbols) and absolute threshold voltage shifts (filled symbols) during stress experiments on non-LDD pMOSFETs biased in the SEGC regime (V V, V : V, squares, and V V, V V, circles) and in the secondary electron injection regime (V V, triangles). For V , V V is positive (electron trapping), while for V ,V V is negative (hole trapping). W=L = : m. Stress drain bias is V : V.

=3 =0 1 1 = 03 5

= 02 5

= 20 0 5

=3 =0

= 04 =3

V) or zero gate current ( V, V) for V [see Fig. 1(b)]. In spite of a substantially [see again Fig. 1(b)], device degradation at high smaller substrate bias (i.e., when substrate hot holes are injected toward pA) is dramatically higher and faster the gate oxide, pA) and also than in electron injection condition ( much larger than in nMOSFETs. At the most critical biases a saturation effect is clearly observed even at relatively short stress times. Threshold voltage shifts have opposite signs in the SEI and SEGC regimes and the positive charge trapping for SEGC (i.e., V) is consistent with the hole injection. The much V) is also larger trapping than in the SEI regime (i.e., consistent with the large trapping cross section of holes in the oxide [28], [29]. Several degradation monitors for stress experiments carried out in the SEGC regime are reported as a function of stress gate bias in Fig. 10. Differently from the nMOSFET case, we observe that worst case degradation does not correspond to the

792


(1 )

(1 ) = 03 5 =3

Fig. 10. Charge-pumping current I , threshold voltage V and drain current I =I degradation of non-LDD pMOSFETs stressed in the SEGC regime. Stress time is 20 s. Stress bias is V : V, V V.

(1

)

maximum of either the electron or the hole gate current [ and in Fig. 1(b)]. On the contrary, the worst case for deV where gate current is vice degradation occurs at approximately zero. This may be explained with the hypothesis that the cooperation of the two type of carriers could enhance the generation of the damage [30], [24], [31] with respect to conditions where damage is generated by only one carrier type. profile of pMOS devices during stress experiments The at the maximum of electron injection current (non-LDD pMOS) and hole injection current (LDD and non-LDD pMOSFETs) are shown in Fig. 11 and have been extracted by means of the same charge-pumping technique used for nMOSFETs [18]. Since one profile of of the assumptions of this technique is that the the virgin and stressed devices are the same, we added a mild hot electron injection phase after the stress phase to annihilate the positive trapped charge. This technique is often used in profiling experiments [16]. However we could not find a combination of injection time and voltages leading to a significant recovery of the trapped charge without simultaneous creation of substantially more traps. Therefore, the mild injection step profiles as was eliminated and we will present here only the measured just at the end of the stress phase. The extracted profiles may thus be influenced by the positive charge trapping induced by hole injection. However, the profiles discussed in the following are at least qualitatively correct because we verified them also for short stress times inducing only negligible oxide charge trapping. Fig. 11 shows that in the SEGC regime, the lateral profile of generated traps extends toward the channel, much more than it does in the SEI stress condition. In addition, differently from the nMOSFET case, no degradation peak is observed in proximity of the drain when p-MOSFETs are stressed in SEGC conditions. The absence of this peak is not simply a consequence of drain engineering options, because it is observed in both LDD and non-LDD pMOS. On the contrary, it is possibly related to the small stress drain voltage compared to the SiO barrier for the V V) that drastically supholes ( presses the injection of holes heated in the channel. In order to confirm the distributed nature of substrate enhanced pMOS degradation, in spite of the uncertainty of the profiles due to uncompensated positive charge trapping, we have after stress in the compared drain current degradation

Fig. 11. Interface trap density along the channel of LDD and non-LDD V, V : V, V V. pMOSFETs stressed in SEGC (bias: V Stress time is 20 s.) and CHC (bias: V V, V : V, V V. Stress time is 20 000 s.) regime.

=3 =0

(1

= 03 5 = 03 5

)

= 04 = 01

Fig. 12. Drain current degradation I =I of the non-LDD pMOSFETs monitored at low and high V versus charge-pumping current increase I . The effect of V is qualitatively similar to that in Fig. 5(a). Squares: stress at V : V and V : V, circles: stress at V : V, and V : V.

j j = 35 j j = 10

j j = 40

j

(1 ) j = 35

SEGC and SEI injection regimes. Fig. 12 shows that, similarly at low (filled symbols) to the nMOSFET case, (open is much more sensitive to substrate bias than at high symbols) indicating a larger degradation toward the center of the channel. VI. CONCLUSION Application of substrate voltage in p-MOSFETs puts in evidence a new substrate hole injection mechanism, complementary to the CHISEL in nMOSFETs. A detailed comparative analysis of gate currents and degradation in n- and p-MOSFETs biased at large substrate voltage is thus possible and has been carried out here. Results at constant bias show higher interface state generation . Differently and charge trapping in the SEGC than at zero from nMOSFETs, the worst case degradation in p-MOSFETs does not occur at the maximum of the gate current, but at a bias corresponding to approximately zero gate current and allowing for simultaneous electron and hole injection in the gate oxide. Accurate analysis of degradation parameters collected during stress experiments on n- and p-MOS shows that for a given drain


and gate bias, stress in the SEGC regime generates a larger and spatially more distributed damage than conventional channel hot carrier stress. Furthermore, injection experiments at constant gate current, especially relevant in the viewpoint of applications in the field of NVM devices, put in evidence a slightly larger degradation rate for CHISEL than for CHE injection conditions, which is absent for constant bias stresses and possibly related to the lower drain bias required to maintain a constant gate current. Overall, in terms of long-term degradation the CHISEL regime is not significantly worse than in the CHE one, because the slightly larger degradation rate is partly compensated by a smaller absolute degradation in the early phase of stress. However, the more distributed nature of the damaged region could lead to interactions between damage during program and erase operations, especially if the latter is performed by tunnel injection through the whole channel area.

ACKNOWLEDGMENT The authors would like to thank D. Peschiaroli, ST Microelectronics, for device fabrication, and Prof. E. Sangiorgi for constant support and encouragement.

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Francesco Driussi received the Laurea degree in engeneering from University of Udine, Udine, Italy, in 2000, working on substrate-enhanced hot carrier reliability effects in Flash memory devices. Since 2000, he has been pursuing the Ph.D. degree at the DIEGM, University of Udine. His research activities are in the field of nonvolatile memory cell reliability and, in particular, his interests are in the characterization of hot carrier device degradation and thin-oxide reliability.

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David Esseni (S’98–M’00) received the Laurea and Ph.D. degrees in electronic engeneering from the University of Bologna, Bologna, Italy, in 1994 and 1998, respectively. In 1999, he became an Assistant Professor with the University of Udine, Udine, Italy. In 2000, he was a Visiting Scientist with Bell Labs, Murray Hill, NJ, now Lucent Technologies. His research interests include characterization techniques for electrical parameters in MOS devices and several aspects related to hot-electron in MOSFETs and Flash EEPROMs. In particular, he has investigated low-voltage and substrate-enhanced hot electron phenomena with an emphasis on their practical implications for Flash EEPROM devices. More recently, he was involved in the experimental characterization and modeling of low-field mobility in ultra-thin SOI MOSFETs and in the experimental investigation of the physical mechanisms responsible for thin oxides degradation.

Luca Selmi (M’01) was born in 1961. In 2000, he became Full Professor of electronics with the University of Udine, Udine, Italy. During 1989–1990, he was a Visiting Scientist with Hewlett Packard’s Microwave Technology Division, Santa Rosa, CA. His research interests include characterization and simulation of silicon devices with emphasis on Monte Carlo transport techniques and hot carrier effects in MOSFETs and Nonvolatile memory cells, leakage currents, and reliability of ultrathin oxides and device optimization. These activities have been conducted in cooperation with international research centers such as Bell Labs, the IBM T. J.Watson Research Center, Philips Research Laboratories, INPG, and LETI Grenoble. He has co-authored approximately 90 papers, including 18 IEDM papers. Dr. Selmi was a Member of the IEDM technical subcommittee on “Modeling and Simulation” in 1995–1996. Since 2001, he has held the same position on the “Circuit and Interconnect Reliability” subcommittee.


Fausto Piazza was born in Mantova, Italy, in 1966. He received the degree in physics from the University of Trento, Trento, Italy, in 1992, working on optics on semiconductor heterostructures, and the Ph.D. degree from the High Magnetic Field Laboratory, University of Nijmegen, Nijmegen, The Netherlands, in 2000, discussing a thesis entitled “Transport in Semiconductors under Strong Electric and Magnetic Field Gradients.” Since 1997, he has been with the Nonvolatile Memory Process Development, Central Research and Development of STMicroelectronics, working on process development of embedded Flash memories. Since 2001, he has been Project Leader for the process development of the 0.18 m generation of embedded Flash.