ASPE Extended Abstract Template

3 downloads 0 Views 302KB Size Report
DOUBLE PATTERNING REQUIREMENTS FOR OPTICAL. LITHOGRAPHY AND PROSPECTS FOR OPTICAL EXTENSION. WITHOUT DOUBLE PATTERNING.
DOUBLE PATTERNING REQUIREMENTS FOR OPTICAL LITHOGRAPHY AND PROSPECTS FOR OPTICAL EXTENSION WITHOUT DOUBLE PATTERNING Andrew J. Hazelton2, Shinji Wakamoto2, Mike Binnard1, Shigeru Hirukawa2, Martin McCallum3, Nobutaka Magome2, Jun Ishikawa2, Céline Lapeyre4, Isabelle Guilmeau4, Sébastien Barnola4, Stéphanie Gaugiran4 1 Nikon Research Corp. of America Belmont, CA 2 Nikon Corporation Tokyo, Japan 3 Nikon Precision Europe GmbH West Lothian, United Kingdom 3 CEA/LETI Grenoble, France ABSTRACT Double patterning (DP) has become part of the development roadmaps of many device manufacturers for half pitches of 32 nm and beyond. Depending on the device layer, many types of DP and double exposure (DE) are being considered. This paper explores requirements of the most complex DP methods: pitch splitting, where line density is doubled through two exposures, and sidewall processes, where a deposition process is used to make the final pattern. Budgets for Critical Dimension (CD) uniformity and overlay are presented with tool and process requirements to achieve these budgets. Experimental results showing 45 nm lines using dry ArF lithography with a k1 factor of 0.20 are presented to highlight some of the challenges.

lithography (reducing λ to 13 nm) continues to be hampered by development challenges. Extending ArF technology using high index fluids and glasses (increasing NA to 1.5 or more) is appealing, but suitable materials do not yet exist. The only mainstream technology that can be ready for the beginning of 32 nm production is double patterning (reducing k1 below 0.25). These processes, where two separate patterning processes are combined to create the final pattern, face challenges due to significant increases in process cost and technical requirements for the exposure tools to achieve the required accuracy of the final pattern. Pitch splitting DP

Sidewall process 1st exposure

INTRODUCTION The resolution of microlithography processes is given by the Rayleigh criterion, R = k1 *

1st etch

λ

2nd exposure

NA

where λ is the wavelength, NA is the numerical aperture of the projection lens, and k1 is a factor related to illumination and other effects. Leading edge lithography systems are now using ArF excimer lasers with λ=193 nm, off-axis illumination to provide k1 between 0.25 (the theoretical minimum for a single exposure) and 0.4, and water immersion for NA=1.3~1.35, providing a resolution around 45 nm. To reach 32 nm resolution, several approaches are under consideration in the industry. EUV

sidewall deposition sidewall etch back

gap fill & CMP 2nd etch final pattern

Resist Hard mask

Base layer BARC

Sidewall Substrate

FIGURE 1. Double Patterning process flow.

The appropriate double patterning process depends on the type of pattern being imaged. In addition, requirements for memory circuits and logic circuits are also different. Because of these different requirements, many double exposure and patterning processes have been proposed.[1][2][3][4] This paper explores two of the processes most likely to be used for 32nm production: pitch-splitting double patterning, and sidewall processing. In pitch-splitting double patterning (DP), after the first exposure, the wafer is developed and some form of processing is performed to maintain the integrity of the first exposure. The wafer is then recoated with photoresist and the second pattern is exposed and developed. Finally, the combined pattern is transferred into the underlying layer. For these processes, either lines or trenches can be printed.[5][6][7] In sidewall processing, the wafer is exposed only once. After developing and etching, sidewalls are conformally deposited on all sides of the pattern. These sidewalls can then be used as a mask (or spacers for another mask material) for subsequent etching.[8] Because the sidewalls are deposited with nominally constant width, and uniformly on all sides of the exposed pattern, there are limitations on the final patterns that can be generated with this process. In addition, trim exposures may be required to eliminate undesired sidewall patterns. 1st exposure

litho O v erla y error

litho C D erro r

2nd exposure

C D e rrors for spa ce s

p osition error for spa ce s

Final pattern

FIGURE 2. Overlay influence on CDU (left) and CD effect on overlay (right) Two of the critical measures of lithography performance are Critical Dimension Uniformity (CDU) and Overlay. CDU is a measure of the variation (within a chip, across a wafer, or throughout a lot of wafers) of the most critical (typically the smallest) features. Overlay is a measure of the alignment accuracy between the current layer and previous layers. Double patterning is a challenge because CDU and

overlay requirements are tighter, and because the effects become intertwined. (Fig 2) CRITICAL DIMENSION UNIFORMITY For pitch splitting processes, the final pattern CD uniformity is not the same as the CD uniformity of a single exposure. Assuming a DP process for printing lines, the final CD uniformity of the lines is a combination of the CD uniformities of the two exposures. For the spaces, any overlay error between the exposures will result in a CD error as shown in the left of Fig 2, and any CD error will result in an overlay error of the two patterns as described below (Fig. 2, right). Trench DP processes have corresponding phenomena, but the affected patterns are the lines. l e1 = ol1 − 1 2 l e2 = ol1 + 1 2 l P e3 = + ol 2 − 2 2 2 l P e4 = + ol 2 + 2 2 2 l e5 = P + ol1 − 1 2

P FIGURE 3. splitting DP.

Definition of variables for pitch

To understand the lithography requirements to achieve the final CD uniformity target, these effects need to be quantified. Consider two exposures with the following characteristics: pattern 1 line width: l1 (mean L1 ; 3σ ∆CD1 ) pattern 2 line width: l2 (mean L2 , 3σ ∆CD2 ) pattern 1 pos. offset: ol1 (mean m1 , 3σ ∆OL1 ) pattern 2 pos. offset: ol 2 (mean m2 ; 3σ ∆OL2 ) The position offset is the shift between the actual position of the pattern from the ideal position. This offset does not include the repeatable grid and distortion error of the tool. Using these definitions, the tool-to-itself overlay (SO, also called single machine overlay) of the lithography tool can be expressed as: m SO = m2 − m1 (1) ∆OLSO = ∆OL2 + ∆OL1 = 2 ∆OL 2

2

(2)

where the variation of overlay error is assumed to be equal for the two exposures, i.e. ∆OL = ∆OL1 = ∆OL2 . The position of the line edges can be calculated and are shown in Fig. 3, where P is the desired pitch. CD uniformity for lines Focusing first on the lines, the width of the lines is simply: L1 = e2 − e1 = l1

(3)

L2 = e4 − e3 = l2

In this case there are two populations of lines with potentially different mean values. The general expression for the pooled variance with individual mean values ( µ1 , µ 2 ) and standard deviations ( σ 1 , σ 2 ) is: σp =

σ 12

σ 22

⎡3 ⎤ + + ⎢ (µ1 − µ 2 )⎥ 2 2 2 ⎣ ⎦

2

[(

∆CD 2 2 + ∆OLLine + 3 m1 − m2 2

∆CDspace =

(

)

2

(9)

CD uniformity for Sidewall Process For the sidewall process, the calculation is somewhat different. In this case, the final pattern is formed with one exposure process and one deposition process. Similar to the pitch splitting process, consider an exposure and deposition process with the following characteristics: pattern line width: llitho (mean L1 ; 3σ ∆CD1 ) pattern pos. offset: ollitho (mean L1 ; 3σ ∆OLlitho ) sidewall width: ldepo (mean L1 ; 3σ ∆CDdepo ) llitho 2 l = ollitho + litho 2

esw1 = ollitho − esw2

esw3 = ollitho −

(4)

llitho + ldepo 2 llitho − ldepo 2 l = P + ollitho − litho 2

esw4 = P + ollitho −

Assuming the CD uniformity is the same for the two exposures: ⎡3 ⎤ ∆CDLine = ∆CD 2 + ⎢ L1 − L2 ⎥ ⎣2 ⎦

)]

esw5

2

(5)

where ∆CD = ∆CD1 = ∆CD2 .

P

CD uniformity for spaces For the spaces, the width of each space is expressed as:

FIGURE 4. Definition of variables for Sidewall Process

l l P + ol2 − ol1 − 1 − 2 2 2 2 l l P S 2 = e5 − e4 = − ol2 + ol1 − 1 − 2 2 2 2

The line edge positions are calculated and shown in Fig. 4. For a process where spaces between the sidewalls define the final pattern:

S1 = e3 − e2 =

(6)

Assuming the CD uniformity and the standard deviation of the overlay is the same for each exposure, and also noting the difference between the width of the spaces is: S1 − S 2 = 2ol2 − 2ol1 (7) The resultant CD uniformity of the two exposures is:

[(

)]

[(

)]

∆CDspace =

∆CD 2 + 2∆OL2 + 3 m1 − m2 2

=

∆CD 2 2 + ∆OLSO + 3 m1 − m2 2

S sw1 = esw 2 − esw1 = llitho S sw 2 = esw 4 − esw3 = P − llitho − 2ldepo

(10)

In this case, the CD uniformity of the first set of lines is simply ∆CDlitho , but the second set of lines includes the additional nonuniformity of the deposited sidewall, with: ∆CDsw 2 = ∆CDlitho + 4∆CDdepo 2

2

(11)

2

(8)

2

Since single machine overlay does not include the overlay error contributed by reticle matching and intermediate processes, as described later, this expression should be replaced by a more general expression for the overlay in double patterning, resulting in:

Defining Llithonominal and Ldeponominal as the respective desired values of Llitho and Ldepo we can define the mean linewidth errors as ∆Llitho = Llithonominal − Llitho

(12)

∆Ldepo = Ldeponominal − Ldepo

Using equation (4) and noting that

(

P = 2 Llithonominal + Ldeponominal

)

(13)

we find the overall CDU of a sidewall process is: ∆CDlitho + 2∆CDdepo 2

∆CDswGap =

(

(

))

⎡3 ⎤ + ⎢ P − 2 Llitho + Ldepo ⎥ ⎣2 ⎦

[(

= ∆CDlitho + 2∆CDdepo + 3 ∆Llitho + ∆Ldepo 2

2

∆S 2

(14)

2

)]

2

(15)

Investigating the term in parentheses above, we can see that if a positive mean error of the printed line CD is offset by a corresponding negative mean error of the deposited layer, it will not contribute to the CD nonuniformity of the final pattern. In the case where the final pattern is defined by the sidewalls themselves, the final CDU only depends on the sidewall uniformity, and not on the lithography CDU and overlay, i.e.: ∆CDswWall = ∆CDdepo (16) OVERLAY The overlay of the final pattern, similarly, is not the same as the overlay of a single exposure. In the case of lines, the final overlay is a combination of the overlays of the 2 exposures, errors between the mask patterns for the two exposures, and errors introduced by the processing between the two exposures.

e3 + e2 P l1 l2 = + − 2 4 4 4 e5 + e4 3P l1 l2 = = − + 2 4 4 4

∆ S1 =

2

(18)

noting that the difference between the position of the spaces is: ∆ S1 − ∆ S 2 = −

P l1 l 2 + − 2 2 2

(19)

The CDU-induced overlay error of the two exposures is: ∆OLCD − space =

(

)

∆CD 2 ⎡ 3 ⎤ + ⎢ L1 − L2 ⎥ 8 ⎣4 ⎦

2

(20)

This contribution can be added to the overlay expression above for the Line DP case resulting in: ∆OLSO + ∆OLreticle + ∆OL process 2

∆OLspace =

+

2

(

)

∆CD 2 ⎡ 3 ⎤ + ⎢ L1 − L2 ⎥ 8 ⎦ ⎣4

2

2

(21)

Overlay for Sidewall Process In the case of sidewall processes, since there is only a single exposure, the requirements for overlay are not as severe as for pitch splitting. In this case, we can assume the overlay requirement is the same as for a single exposure process at the same node.

Overlay for lines To calculate the overlay budget for a pitch splitting process, an extension of the typical single patterning process overlay budget will be used. In addition to the tool overlay contribution, a reticle term is required because the exposure of two different patterns requires two separate reticles with potentially two separate illumination conditions. Also, a process term is included because the wafer is removed from the exposure tool and processed between the two exposures. This results in:

TABLE 1. CD Budget for Pitch Splitting, determined by the requirement of 3.3 nm for Space CDU. Only the first two terms contribute to CDU for lines. Budget Space CDU Line CDU

(17)

32 NM NODE REQUIREMENTS AND EXPOSURE TOOL BUDGET For the 32 nm node, the 2007 version of the ITRS specifies CDU of 3.3 nm, with a significantly tighter specification for transistor gates of 1.3 nm. Since pitch splitting technology is expected to be used for metal layers, we assume a requirement of 3.3 nm for double patterning CDU. Similarly, the ITRS specifies overlay of 6.4 nm. In a single exposure process, the tool-to-itself overlay occupies about 70% of this budget, so a reasonable assumption for the

∆OLLine = ∆OLSO + ∆OLreticle + ∆OL process 2

2

2

Where ∆OLreticle is the 3σ matching error between the two reticles and ∆OLprocess is the 3σ overlay offset induced by processing between the two exposures. CD nonuniformity effect on spaces As shown in the right side of Fig. 2, in the case of spaces, any CD nonuniformity will affect the position of the spaces and result in additional overlay error. The position of each space as a function of the CD is expressed as:

L1 − L2 ∆CD m SO

0.5 nm

∆OLLine

2.3 nm

2.5 nm 0.5 nm

2.6 nm 3.3 nm

lithography portion of the overlay budget in a pitch splitting process is 4.5 nm. CD uniformity budget Starting with the CDU requirement of 3.3 nm for Spaces (because fewer factors contribute to Line CDU), we determine the budget components shown in Table 1. As explained above, the effects of overlay must be included in the CDU budget for spaces. The CDU values in this budget include contributions from the etching process as well as from lithography. As etching is a multiple step process (resist trimming, BARC open, hard mask open), each step must be carefully tuned to minimize its added nonuniformity. For this purpose, multiple adjustments (RF power, Temperature, gas flow, etc.) are available on recent etch tools that allow step by step tuning of the etch uniformity. Recently, CDUs of approximately 1 nm have been reported for leading edge lithography tools [9], so it should be possible to achieve these CDU targets. The difference in average CD between the two exposures can be influenced by topography changes and different etch biases for the two exposures. However, the overlay mean and 3σ budget terms shown in Table 1 are significantly tighter than those of current exposure tools. Achieving these target will require special measures. TABLE 2. CD Budget for Sidewall Process, determined by 3.3 nm allowance for Gap CDU. Budget Gap Wall CDU CDU 2.5 nm ΔCD litho

ΔCD deposition adjustment error

∆Llitho + ∆Ldepo

1.1 nm

1.1 nm 3.3 nm

0.5 nm

The lithography budget for Sidewall Processing (Table 2) is the same as for pitch splitting processes. The requirements for deposition and adjustment error are fairly tight and more investigation is required to ascertain the feasibility of these values.

Overlay budget As shown in equation (17), the overlay budget has contributions from the exposure tool, reticle matching, and the intermediate processing. Based on these three elements, the following overlay budget is specified for the pitch splitting process. The mean plus 3σ overlay target is chosen to be the same as required for the CDU. TABLE 3. Overlay Budget Overlay mean Overlay 3σ Reticle matching Process factors DP overlay mean+3σ

Budget 0.5 nm 1.8 nm 1.0 nm 1.0 nm 2.8 nm

∆OLline 2.3 nm

As the current generation of exposure tools have overlay specifications of around 6.5 nm, the requirement of 0.5 nm + 1.8 nm = 2.3 nm for the 32 nm node is a significant reduction. This requires a detailed review and careful adjustment of the overlay error sources. Three particular areas are targeted: 1. Air fluctuations of the interferometer measurements of the wafer and reticle stage positions. Thermal fluctuations of the air inside the exposure tool change the refractive index along the beam path. Countermeasures include significantly reducing the thermal fluctuations and significantly reducing the length of the beam path. 2. Thermal drift of machine components affecting intra- and inter-lot stability. Frequent calibration of the system through use of the Tandem Stage technology on Nikon’s latest exposure tools can significantly reduce these errors. 3. High-order grid and shot shape correction. Lower order grid order correction is commonly applied, but higher order grid corrections will be required. In addition, shot shape errors caused by reticle distortion will also be necessary. Achieving the matching specifications for the reticle will also be a challenge. For example, reticle writing error should be reduced from current levels of 1.0~1.5 nm to 0.5 nm or less. Further studies are required to confirm the reticle budget, but it seems likely a single mask writer will be required for each pair of masks.

EXPERIMENTAL RESULTS Experiments were performed on a Nikon S307E dry ArF scanner (NA 0.85) connected to a Sokudo RF3 track, and a Lam Versys etching tool. The targeted imaging is similar to an immersion process, however, where 32 nm features imaged at 1.30 NA have a k1 of 0.22, the 45 nm features targeted on the 0.85 NA system have a k1 of 0.20. Reducing k1 to this level while maintaining sufficient process window is a challenge.

k1 factors, and novel double techniques for logic manufacturing.

A critical part of the process is ensuring that the profile of the first hardmask is not overly compromised by the second etch step. An example of this can be seen in Fig. 2 where during transfer into the second hardmask, the first feature is compromised. Further work is required, but this shows etching is not a trivial part of the double patterning process.

FIGURE 6. Etched 45 nm line/space patterns with k1=0.20

2nd feature

1st feature

FIGURE 5. SEM images of initial DP etched patterns. SEM images of etched 45 nm line/space patterns, a k1 of 0.20, can be seen in Fig. 3. The CDU of the (dark) lines is good, but due to some slight pattern misalignment, the (light) space CDU is not as good. Further optimization of the process is required. CONCLUSIONS To meet the requirements for 32 nm processes, several types of double patterning have been proposed. Pitch splitting has the most severe requirements for lithographic processing with overlay accuracy < 3 nm, ΔCD 2.5 nm, reticle matching 1 nm, and process-induced overlay error 1 nm required. These can be achieved in time, but will be very challenging. To delay the need for adopting these technologies, several alternative processing methods are expected to be employed for the 32 nm node including: sidewall processing for memory, pattern layout simplification for logic, further improvements in

x100k

exposure

x300k

REFERENCES [1] M. Burkhardt, et al., “Dark Field Double Dipole Lithography (DDL) for Back-End-ofLine Processes,” Proc. of SPIE Vol. 6520, 65200K (2007). [2] H. Nakamura, et al., “Ultra-low k1 oxide contact hole formation and metal filling using resist contact hole pattern by Double L&S Formation Method.” Proc. of SPIE Vol. 6520, 65201E (2007). [3] Y. Trouiller, et al., “32 nm SOC printing with double patterning, regular design, and 1.2 NA immersion scanner.” Proc. of SPIE Vol. 6520, 65201D (2007). [4] H. Ohki, et al., “Experimental study on nonlinear multiple exposure method.” Proc. of SPIE Vol. 3051, pp. 85-93 (1997) [5] C. Lim, et al., “Positive and Negative Tone Double Patterning Lithography.” Proc. of SPIE Vol. 6154, 615410 (2006). [6] R-H. Kim, et al., “Double Exposure Using 193nm Negative Tone Photoresist.” Proc. of SPIE Vol. 6520, 65202M (2007). [7] RHEM private communication. [8] W. Jung et al., “Patterning with amorphous carbon spacer for expanding the resolution limit of current lithography tool.” Proc. of SPIE Vol. 6520, 65201C (2007). [9] K. Goto, et al., “Adapting Non Topcoat Process to High Volume Manufacturing.” 4th Symposium on Immersion Lithography, PR-02 (2007). [10] A.J. Toprac, "AMD's Advanced Control of Poly-gate Critical Dimension," Process, Equipment, and Materials Control in IC Manufacturing V, A.J. Toprac and Kim Dang (editors), Proceedings of SPIE, 3882, 62 (1999).