AUTOMATIC GA BASED EVOLUTION OF FAULT TOLERANT DIGITAL CIRCUITS A.P.Shanthi, Balaji Vijayan, Manivel Rajendran, Senthilkumar Veluswami and Ranjani Parthasarathi
[email protected] School of Computer Science and Engineering Anna University, Chennai India-600 025.
ABSTRACT Genetic Algorithm based automatic evolution of fault tolerant digital circuits has been examined at three different levels. At the first level, multiple working designs are automatically generated, offline, without additional human design effort and each is documented with the unused resources information. This information is used for fault tolerance. Depending on the number of versions generated, up to 100% single component fault coverage can be achieved. The second level examines the effect of providing additional resources by increasing the dimensionality of the evolved circuit. Finally, the addition of a fault tolerant layer that has been examined guarantees simultaneous single component fault coverage. All these techniques have been tested for gate level, functional level and Configurable Logic Block (CLB) level evolution and the results have been analyzed. The techniques have been tested for simple combinatorial circuits and an ISCAS ’89-benchmark circuit.
1. INTRODUCTION Recently, the idea of evolving hardware has attracted an increasing group of researchers [1]. Evolvable Hardware (EHW) uses software-reconfigurable logic devices like Programmable Logic Devices (PLDs) and Field Programmable Gate Arrays (FPGAs) whose architecture can be reconfigured by a genetic learning algorithm. If new hardware functions are required, EHW can alter its own hardware structure rapidly and accommodate such changes in real time. The possibilities for automatic design of electronic circuits using evolutionary algorithms have been explored in the analog [2] and digital [3,4,5] domains and it has been found that evolutionary algorithms can in practice produce designs that are beyond the scope of conventional methods and are in some sense better [6,7]. There is evidence that evolutionary processes have some inherent fault tolerance properties [8] due to the very nature of their evolution itself. Several standard evolutionary algorithmic approaches have been proposed for fault
recovery of hardware systems. Population based approaches include fault tolerance as a fitness criteria and retain the most fault tolerant of individuals [9]. In another approach, the evolution of designs containing redundant capabilities, without the designer having to explicitly specify the redundant parts has been investigated [10]. To achieve this, ranges of fault cases were introduced throughout the evolutionary process and the individuals were allowed to exploit whatever component behaviors exist, including behaviors known to be faulty. Miller [11] has examined the properties of messy gates whereby, evolved logic functions inherently contain redundant terms as their functional boundaries change and overlap. Canham and Tyrell [12] have compared the fault tolerance of oscillators evolved by including a range of fault conditions within the fitness measure of the evolutionary process. It has also been proven that the evolution of a circuit produces a number of diverse solutions that provide the useful redundancy for fault tolerance [13]. The work reported in this paper manipulates and exploits the useful redundancy to generate fault tolerant digital circuits. Three different techniques have been proposed here. The first one involves the generation of multiple versions of a circuit, which provides a set of circuit configurations to choose from, depending on the faulty component. The fault coverage provided by this method depends on the number of versions generated and can go up to 100% single component fault coverage. The second method extends the fault coverage further by increasing the dimensionality of the evolved circuit. Lastly, a fault tolerant layer has been added to the evolved circuit. This layer guarantees simultaneous single component fault coverage for a set of components. Depending on the thickness of the layer, the number of simultaneous faults covered for each set can be increased. All these techniques also provide additional fault coverage for specific components depending upon the version generated. The details are presented in the following sections. The paper is organized as follows. Section 2 discusses the fundamentals of genetic algorithms and their application to the evolution of fault tolerant digital circuits. The three methods proposed for the design of fault tolerant digital circuits are presented in section 3. The experimental results and discussions are presented in section 4. Section 5
summarizes the techniques proposed and points out future directions of research. 2. EVOLUTIONARY DESIGN OF DIGITAL CIRCUITS AND FAULT TOLERANCE The metaphor underlying genetic algorithms is that of natural evolution. Genetic algorithms have been applied to a wide range of problems, from optimizing the design of mechanical objects to evolving computer programs [14] and EHW. The application of genetic algorithms to design digital circuits has been attempted at various levels [3,4]. Recently they have been applied to evolving fully synthesized, placed and routed reconfigurable circuits [15]. The digital circuit to be designed to satisfy the given input/output combinations are represented as a chromosome. The standard genetic operators such as initialization, recombination and selection are carried out on the chromosomes, till a satisfactory design evolves. By custom tailoring the algorithm, they can be used to create a wide range of circuits. The circuits may be evaluated using software simulation models, as in the case of extrinsic evolution [16], or alternatively evaluated entirely in hardware, as in intrinsic evolution [17]. In both these cases, the evolution process itself is carried out in software. It is also possible to have the evolution process itself done on hardware to speed up the process, which is termed as complete evolution [18]. Fault tolerance is extremely important for electronic components used in critical applications. The traditional fault tolerance techniques are based around simple static redundancy [19], which are expensive in terms of equipment, time and design costs. An alternate approach is to use a form of reconfiguration to bypass the faulty item, which may be a hardware process, a software process, or a combination of the two. All reconfigurable mechanisms are based on either time redundancy or hardware redundancy. The majority of hardware redundancy reconfiguration techniques rely on complex algorithms, either executed by a central controller [20] or done in a distributed fashion [21,22]. The centralized control is solely dependent on a single controller that makes its design very critical. It suffers from very long timing signals that may not be suitable for real-time fault tolerance. On the other hand, the decentralized approach increases the complexity of the reconfiguration algorithm and the communications within the network. It is also difficult to produce useful redundancy. EHW has fault tolerance identified as a significant feature. When evolutionary algorithms are used for circuit design, there is the inherent fault tolerance property of the evolutionary process itself, which provides a key advantage. It is this feature that is being used to advantage in this work. 3. PROPOSED FAULT TOLERANT APPROACHES Three different approaches to design fault tolerant digital circuits that take advantage of the useful redundancy are proposed. Extrinsic evolutionary techniques are used to generate the design of fault tolerant digital circuits,
automatically, without any extra design effort using these three approaches. There is also no additional control and the associated complexities involved. 3.1. Approach 1 The first approach generates multiple circuit configurations that provide the useful redundancy required. Here, each version that is evolved is documented with the unused resources information. The corresponding configuration information is generated using the standard tools available and stored. In case of a fault being detected, the stored version that does not use this resource is considered, and the appropriate configuration information is downloaded. In this case, no extra redundancy is provided and only the available unused resources are made use of to provide fault tolerance. Depending on the number of versions generated, up to 100% single fault coverage may be provided. Apart from the single fault coverage, each version also supports specific multiple fault coverage depending on the unused components. 3.2. Approach 2 The second approach increases the amount of useful redundancy by allowing the circuit to evolve in a higher dimension and the effect of this on fault coverage is examined. The idea here is to provide additional resources for fault tolerance. 3.3. Approach 3 This approach provides a fault tolerant layer on the evolved design. This layer is in the form of unused gates bordering the evolved design. For a two dimensional array structure, this may be in the form of an additional row at the top thus providing one free component per column. This layer guarantees multiple fault coverage, with a minimum of one fault in each column of components, apart from the single component fault coverage that is automatically supported. Figure 1 shows that each fault tolerant layer component handles faults in its respective column, thus supporting multiple fault coverage.
Figure 1: Fault tolerant layer This layer automatically provides 100 % single fault coverage. The thickness of the layer determines the number of minimum faults covered in each column. For example, if the thickness is increased to two, the number of minimum faults covered in each column increases to two. Simulation studies have been carried out to illustrate these ideas. The details of this study are presented in the next section.. 4. EXPERIMENTAL RESULTS AND DISCUSSIONS For simulation purposes, a two dimensional array of components has been considered for evolution. The
components may be basic gates, functional units or CLBs. Gates support fine-grained design whereas functional blocks support higher-level designs. CLBs are more general purpose in nature and are widely used in coarser grained reconfigurable fabrics. Here the three approaches detailed above have been examined for all three types of components. Simulation has been carried out for simple circuits like twobit adder, two bit multiplier and an ISCAS’89 benchmark circuit [23]. The chromosome structure used for evolution is as shown in Figure 2. There are totally N numbers of components with each one of them having the structure indicated here. It is assumed that each column takes its inputs from only the immediately preceding layer or from external inputs. The evolution is carried out for a population size of 75 with a two-point crossover and a probability of mutation 0.02 using elitist selection.
Version 1 2 3 4 Version
1
2 Figure 2: Chromosome Structure 3 G: T: I: O: F: TF: N:
Version 1 2 3 4
Version 1 2 3 4
Gene: Specifies whether the gate is an AND, OR, XOR, NAND, NOR or XNOR gate or an adder or subtractor in the case of functional blocks Type: Specifies whether the inputs are true or complemented Set of Inputs Set of Outputs Specifies the fitness value for the set of outputs Maximum fitness of the circuit Number of components: DimensionOfRow * DimensionOfColumn Number of Unused Fault iterations gates coverage 1064 2/9 3 8 876 3 6 3/9 501 5/9 4 7 947 5 7 6/9 Table 1: Approach 1: 2 bit adder – 3*3 Number of Unused Fault iterations gates coverage 3517 2/9 3 7 4875 4/9 6 8 3902 5 7 5/9 4392 4 6 6/9 Table 2: Approach 1: 2 bit multiplier--3*3
The simulation results for the first approach using gates are shown in Tables 1 and 2. The unused gates indicated for each version represent the useful redundancy available. With four versions, 66.7% of single component fault coverage has been obtained. The amount of useful redundancy restricts the fault coverage provided.
Version
Number of iterations
Unused gates
Fault coverage
2 3 5 7 8 13 8/16 14 15 1 3 5 9 12 14 512 11/16 15 0 1 6 7 10 13 487 14/16 14 15 1 4 8 11 12 13 16/16 526 15 Table 3: Approach 2: 2 bit adder -- 4*4 Fault Number of Unused Gates coverage iterations 1 2 4 5 7 9 11 12 14 15 16 17 18 20 21 22 23 18/25 468 24 3 5 7 12 13 14 15 16 17 18 19 21/25 584 20 21 22 23 24 0 4 5 6 8 10 12 14 15 16 18 25/25 512 20 21 22 Table 4: Approach 2: 2 bit adder -- 5*5 593
Number of iterations
Unused gates
Fault coverage
5 7 9 10 13 6/16 14 0 5 10 11 12 2 512 10/16 13 14 15 1 4 5 8 9 11 13/16 3 718 12 13 14 15 2 3 6 11 12 16/16 4 527 13 14 Table 5: Approach 2: 2 bit multiplier -- 4*4 Number of Version Unused gates Fault coverage iterations 3 4 5 7 8 11 12 13 15 16 17 18 20 17/25 1 322 21 22 23 24 1 4 5 7 8 10 12 14 15 17 18 19 20 21/25 2 221 21 22 23 24 0 2 6 9 12 15 16 19 20 25/25 3 162 21 23 24 Table 6: Approach 2: 2 bit multiplier -- 5*5 1
356
The results of the second approach shown in Tables 3 to 6 indicate that 100% single component fault coverage could be achieved by increasing the dimensionality. The lists of unused gates show that additional fault coverage for specific gates (the ones that are not highlighted) can also be provided in each version.
The increase in dimensionality increases the amount of useful redundancy available. This in turn provides more options for the circuit to evolve. It is because of this flexibility that there is also a good reduction in the time taken to evolve the circuit. Tables 7 and 8 show that there is a marked reduction in the number of iterations as the dimensionality is increased. Dimension Number of iterations 3*3 847 4*4 529 5*5 506 Table 7: Approach 2: 2 bit adder Dimension Number of iterations 3*3 4172 4*4 528 5*5 235 Table 8: Approach 2: 2 bit multiplier The results of the effect of increased dimensionality for a functional level evolution are shown in Tables 9 and 10. The functional units considered for this implementation are full adder and full subtractor. Though the functional evolution of circuits shows a decrease in the number of iterations, such an approach requires a prior knowledge of the basic functionalities needed by the circuit to evolve it. Dimension Number of iterations 3*3 417 4*4 134 5*5 78 Table 9: Approach 2: 2 bit adder Dimension Number of iterations 3*3 2642 4*4 953 5*5 437 Table 10: Approach 2: 2 bit multiplier Tables 11 and 12 show the results for approach three, with the addition of 1ne layer and two layers. It can be seen that, with only one single version, all the single component failures are covered. It also covers one fault in each column. With a layer consisting of two rows, a minimum of two faults in each column is covered and so on. The number of unused gates that indicate the additional, evolution dependent fault coverage is also shown. Number Fault Additional Dimension of tolerant fault Iterations layer coverage 4*4 2148 Layer 1 7, 9,10,11,15 Layers 4*4 2009 11 1 and 2 7, 8, 12, 13, 14, 16, 17, 5*5 1011 Layer 1 18, 19,21,22,23 Layers 9,14,17,18, 5*5 288 1 and 2 22, 24 Table 11: Approach 3: 2 bit adder
Additional fault coverage 4*4 9,13,14,15 7,12,13,14, 5*5 285 Layer 1 16,17,18,21, 22, 23, 24 Table 12: Approach 3: 2 bit multiplier The CLB level simulations shown in Table 13 indicate that it takes a large number of iterations even for simple circuits. This is because of the purely random look-up table nature of the CLBs. This problem can be overcome if the problem can be decomposed and an incremental evolution is used. For example, for a four-input/three-output circuit, a direct mapping to three different four input CLBs can be incrementally considered and the outputs integrated later on. The process of decomposition and the integration techniques used thereafter is not trivial and is dependent on the number of inputs of the CLBs and has to be investigated further. Dimension
Number of Iterations 1010
Dimension
Fault tolerant layer Layer 1
Number of iterations
3*3 36426 4*4 30440 5*5 57111 Table 13: Approach 3:2 bit adder Out of the three types of components used for evolution, the gate level approach looks promising. So a gate level simulation for an ISCAS’89 benchmark data con1 with seven inputs, two outputs and nine product terms was done. The simulation results for a dimensionality of 12*12 are tabulated in Table 14. Fault Coverage/Additional Fault Coverage 1 207605 69/0 2 72766 92/23 3 85675 105/13 Table 14: ISCAS’89 benchmark data con1 The first entry in the fault coverage field indicates the cumulative fault coverage over the versions and the second entry shows the additional fault coverage provided by that version alone, on top of what has been provided by the earlier versions. With three versions, a fault coverage of 72.9% was achieved. With more number of versions, the fault coverage can be increased up to 100%. Version
Iterations
5. CONCLUSION This work has demonstrated three different levels in which fault tolerance can be supported in the evolutionary design of digital circuits. There is no additional control or design effort needed. These initial experiments have just illustrated the power to evolve fault tolerant digital circuits. Further research will be aimed at real time implementations of these techniques for specific families of programmable hardware. The interconnections supported will have to be considered
during the evolution process. Also the decomposition and integration that need to be done in the case of complex problems or CLB level implementations have to be probed further.
11. J. F. Miller and M. Hartmann, “Untidy Evolution: Evolving Messy Gates for Fault Tolerance” in The 4th International Conference on Evolvable Systems(ICES2001), 2001.
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