Backstepping Sliding Mode Current Control for Three ... - ESRGroups

Weipeng Yang1 Aimin Zhang2,*, Hang Zhang1, Jianhua Wang1

J. Electrical Systems 13-4 (2017): 709-722 Regular paper Backstepping Sliding Mode Current Control for Three Phase Voltage Source Rectifier Under Unbalanced Input Voltage Conditions

JES Journal of Electrical Systems

In this paper, a backstepping and sliding mode control-based (BSMC) current control scheme, including both the current control strategy and the control law for three-phase voltage source rectifier (VSR) under unbalanced input voltage conditions is proposed. This scheme takes advantage of the robustness nature of SMC and the systematic design procedure of backstepping, so that satisfactory performance and system robustness can be obtained at the same time. A dual current control structure is adopted to regulate the positive and negative sequence currents in their respective synchronous reference frames. A current control strategy with negative sequence current compensation is adopted to eliminate dc link voltage ripples and ensure sinusoidal ac current. Through instantaneous power flow analysis, relative current references for VSR under unbalanced input voltage conditions are derived. Theoretical analysis is performed and proofs are provided where necessary. Extensive simulation studies are conducted to verify the effectiveness of the proposed BSMC current control scheme.

Keywords: Voltage Source Rectifier; Current Control; Input Voltage Unbalance; Backstepping; Sliding Mode Control. Article history: Received 18 February 2017, Accepted 15 November 2017

1. Introduction In recent years, the application of three-phase voltage source rectifier (VSR) has been increasing drastically in different industrial sectors, owing to its excellent performance in high power quality, flexible power control, and minimization of filters, etc [1-5]. However, three-phase voltage unbalance is common in practical electric power system, especially in a weak power system. Under this condition, performance of VSR will be deteriorated, e.g., producing dc voltage ripples or leading to ac current distortion if the current control scheme is not properly designed. This not only endangers the VSR, but poses threats to the loads on the dc link [6-7]. Although power quality degradation caused by voltage unbalance can be mitigated through use of large capacity filters, this is achieved at the expense of increased cost and size. Therefore, a current control scheme that guarantees both high performance and strong robustness of the VSR is of great importance. Extensive studies have been conducted on the control of VSR under unbalanced input voltage conditions. In [8-10], a dual current control structure is proposed, which regulates the positive and negative sequence (PNS) currents in their respective synchronous reference frame (SRF). As the instantaneous active power consumption in the ac inductors are not zero when the input voltage is unbalanced, strategies that nullify instantaneous active power ripples at the converter pole are proposed to eliminate dc voltage ripples [11-13]. Although accurate current control objectives are achieved in the above studies, their focus is on the instantaneous power flow analysis and relative current reference derivation, conventional *

Corresponding author: Aimin Zhang, School of Electronic and Information Engineering, Xi’an Jiaotong University, 710049, Xi’an, China, E-mail: [email protected] 1 School of Electrical Engineering, Xi’an Jiaotong University, 710049, Xi’an, China 2 School of Electronic and Information Engineering, Xi’an Jiaotong University, 710049, Xi’an, China Copyright © JES 2017 on-line : journal/esrgroups.org/jes

Weipeng Yang et al: Backstepping sliding mode current control for 3-ph voltage source rectifier...

proportional and integral (PI) or PI plus resonant current controllers are often adopted and robustness of the system is not addressed. In [14], one cycle current control for VSR in the presence of input voltage unbalance is proposed. Although the control system design is simplified, it requires two converters to regulate the PNS currents respectively. In [15], an optimal current control strategy with compromise between different objectives for VSC-HVDC system under unbalanced grid voltage conditions is proposed. This strategy is implemented in static two-phase reference, and proportional plus resonant current controller is used. In [16], a model predictive current control strategy with disturbance observer is presented for VSR. Although the robustness can be improved, observers for resistance, inductance and filter delays have to be designed, which complicate significantly the implementation. Besides, high sampling frequency and high strength computation further hinder its usage for more general applications. As popular nonlinear control methods, the backstepping and sliding mode control (SMC) have received wide popularity [17-19]. The backstepping breaks a design problem into a sequence of lower-order problems, and finds proper Lyapunov function for each step in a systematic manner until the results of interest are obtained. As for the SMC, it is insensitive to parameter uncertainty and disturbance, the control objective is achieved through forcing system trajectories to reach the designed lower-order sliding manifold (SM), and thus it is easy to implement. In [20], a backstepping-based direct power control (DPC) strategy for VSC-HVDC system is proposed. In [21], a backstepping-based DPC strategy for VSR under both balanced and unbalanced grid voltage conditions is proposed. However, system robustness is not addressed in [20] and [21]. In [22], a SMC-based current control strategy is proposed for VSC-HVDC system. In [23], a SMC-based DPC strategy with integral SM is proposed for grid-connected inverter. However, the above SMC controllers designed are equivalent to proportional controllers, which cannot drive the steady state errors to zero. To eliminate steady state errors, double integral SM is adopted in [24]. However, this increases the controller complexity and the transient performance is degraded as well. In this paper, a backstepping and SMC-based (BSMC) current control scheme, including both the control strategy and the control law is proposed for VSR under unbalanced input voltage conditions. The integrals of the current errors are firstly augmented into the system dynamic equations. Then, the backstepping method is used to design control laws for each sub-system using the Lyapunov method. At the last step, the SMC is used to ensure system robustness. To simplify controller design, the dual current control structure and the control strategy with negative sequence (NS) current compensation as proposed in [9] is adopted. Besides, through nullifying active power oscillation at the converter pole, the dc voltage ripples and ac current harmonics caused by voltage unbalance can be eliminated. Finally, extensive simulation studies are conducted to verify the effectiveness of the BSMC current control scheme. The paper is organized as follows. In section 2, instantaneous power flow analysis and relative current reference derivation for VSR under input voltage unbalance are conducted. In section 3, the proposed BSMC current control scheme is designed; theoretical analysis and stability proof are performed. In section 4, simulation studies are conducted to verify the effectiveness of the BSMC scheme, and section 5 concludes the paper.

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J. Electrical Systems 13-4 (2017): 709-722

2. Notations The notations used throughout the paper is stated below. Indexes: C ci 0 , ci 1

dc link capacitance [F]

βi

switching gain of the ith current control subsystem

ea , eb , ec

phase voltage at the input terminal [V]

EdN , EqN

negative sequence input voltage in d-q reference frame [V]

EdP , EqP

positive sequence input voltage in d-q reference frame [V]

Edqs

input voltage vector in d-q reference frame

i ia , ib , ic

index of the current control subsystem

I dN , I qN

negative sequence ac line current in d-q reference frame [A]

I dP , I qP

positive sequence ac line current in d-q reference frame [A]

I dNr , I qNr

negative sequence ac line current references in d-q reference frame [A]

I dPr , I qPr

positive sequence ac line current references in d-q reference frame [A]

I dqs

ac line current vector in d-q reference frame

L P0 , P0r

ac line inductance [H]

Ps 2 , Pc 2

oscillating active power terms at the input terminal [W]

Pv 2s , Pv 2c

oscillating active power terms at the converter pole [W]

Pvs 2r , Pvc 2r

oscillating active power references at the converter pole [W]

Q 0 , Q 0r

average reactive power and the reference at the input terminal [VAR]

Qs 2 , Qc 2

oscillating reactive power terms at the input terminal [VAR]

R Rdc

ac line resistance [Ω] dc load resistance [Ω]

s

sliding manifold

S u

apparent power output at the input terminal [VAR] control input vector

udN , uqN

positive sequence input in d-q reference frame

udP , uqP

positive sequence input in d-q reference frame

Vi 0 ,Vi 1

procedure and composite Lyapunov function for the ith current control subsystem

va , vb , vc

phase voltage at the converter pole [V]

controller gains for the ith current control subsystem

ac line current [A]

average active power and the reference at the input terminal [W]

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vdc

dc link voltage [V]

VdN ,VqN

negative sequence converter pole voltage in d-q reference frame [V]

VdP ,VqP

positive sequence converter pole voltage in d-q reference frame [V]

Vdqs

converter pole voltage vector in d-q reference frame

ω

angular frequency [rad/s]

x xdN , xqN

state vector negative sequence state vector in d-q reference frame

xdP , xqP

positive sequence state vector in d-q reference frame

δ δi

vector of lumped uncertainty terms lumped uncertainty term for the ith current control subsystem

zi 0 , zi1

virtual control variables for the ith current control subsystem

3. System dynamic model and current reference calculation 3.1. Dynamic model of ac current in the PNS SRF Single-line schematic of three-phase VSR studied is shown in Fig.1. Research show lowfrequency disturbances, such as voltage distortion, voltage dip; voltage variations in phase and amplitude can be modeled as the sum of the positive, negative, and zero sequence components of the fundamental frequency voltage [25,26]. For the VSR as shown in Fig.1, system model can be described in terms of the PNS components, as there’s no loop for zero sequence current to circulate. Moreover, as the switching frequency adopted in this paper is far higher than the fundamental frequency of the power supply, it’s reasonable to represent the VSR by the fundamental frequency voltage and current components for power flow analysis and controller design.

Fig. 1. Single-line schematic of three-phase VSR For three-phase electrical quantity { X a , X b , X c } without zero sequence components, the space vector representation can be described as: X dqs = e jωt X dqP + e− jωt X dqN (1) where:

X dqs =

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2 X a + X b e j 2π /3 + X c e− j 2π /3 ) ( 3

(2)


 X dqP = X dP + jX qP   X dqN = X dN + jX qN

(3)

In the above equations, e jωt and e − jωt denote rotation factor for the positive sequence (PS) and NS components respectively. In (1), the first term on the right hand side denotes the PS component that rotates counter-clockwise; the second term denotes the NS component that rotates clockwise. In this paper, it is assumed that the nominal frequency is 50 Hz. Dynamic model of ac current is given by:

Edqs = Vdqs + L

dI dqs

+ RI dqs

dt

(4)

where Edqs , Vdqs and I dqs follow the notations defined in (1) to (3). Expand (4) and then the following dynamic equations in the PNS SRF can be obtained.

EdqP = VdqP + L EdqN = VdqN + L

dI dqP dt dI dqN dt

+ RI dqP + jω LI dqP

(5)

+ RI dqN − jω LI dqN

(6)

Equations (5) and (6) together describe dynamics of three-phase VSR under unbalanced input voltage conditions within frequency range far lower than the switching frequency. If the input voltage is balanced, Eq. (5) alone describes the dynamics of the VSR. 3.2. Instantaneous power flow analysis When the input voltage is unbalanced, the apparent power S at the input terminal is: *

S = ( e jωt EdqP + e− jωt EdqN )( e jωt I dqP + e− jωt I dqN )

(7)

where * denotes the conjugate of the complex variable. Expand (7) based on (1) to (3) and combine the like terms, active power P and reactive power Q at the input terminal can be expressed as:

S = P + jQ =  P0 + Pc 2 cos ( 2ωt ) + Ps 2 sin ( 2ωt )  + j Q0 + Qc 2 cos ( 2ωt ) + Qs 2 sin ( 2ωt )  Relationship between the power terms in (8) and I dP , I qP , I dN , I qN is:

 EdP  P0     P  EdN 2 c    Ps 2  3  EqN  =  Q0  2  EqP  Q   EqN c2    Qs 2   − EdN

EqP EqN − EdN − EdP − EdN − EqN

EqN   EdP EqP  − EqP EdP   EqN − EdN   EqP − EdP   EdP EqP 

(8)

EdN

 I dP     I qP  I   dN   I qN 

(9)

From (9), we can see the interaction between 1) the NS voltage and the PS current and 2) the NS current and the PS voltage, contribute to active and reactive power ripples. Eq. (9) also indicates the NS currents are necessary to compensate for the input voltage unbalance in attaining constant dc link voltage.

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The active power passed through the converter determines the dc voltage profile. Studies show constant active power exchange from the ac to dc side by nullifying the active power oscillating terms in (9) cannot be attained, because instantaneous active power consumption in the ac inductors are not zero under voltage unbalance. To remedy this, current reference of the oscillating active power terms can be calculated at the converter poles, i.e.

 Pvc 2  3 VdN VqN VdP  =   Pvs 2  2 VqN − VdN − VqP

 I dP    VqP   I qP   VdP   I dN     I qN 

(10)

3.3. Current reference calculation Current reference designed depends on the specific control objectives, e.g., balanced sinusoidal input current, constant dc link voltage, elimination of reactive power oscillation, etc, or a combination of them. There’re a total of eight candidate control objectives but only four controlled variables in (9) and (10), which means that only four of the objectives can be controlled at the same time. The control objective of this paper is to keep constant dc link voltage and sinusoidal ac line current, and to attain a high power factor at the input terminal. Therefore, the average active power exchange between the power source and the dc side should be controlled, and it’s necessary to eliminate the active power ripple, i.e., nullifying PVc 2 and PVs 2 . In addition, zero average reactive power exchange between the power source and the converter should be reached, i.e., attaining an average unity power factor. Through combining the above control objectives, the power exchange equations for VSR can be obtained as:

 EdP EqP  P0 r     E − EdP Q0 r  = 3  qP  Pvc 2 r  2 VdN VqN    VqN − VdN  Pvs 2 r  

EdN EqN VdP − VqP

EqN   − EdN  VqP   VdP 

 I dPr     I qPr  I   dNr   I qNr 

(11)

Assume the relation matrix between the current and the power reference in (11) is nonsingular. Then, the current reference can be calculated as:

 EdP EqP  I dPr     I 2 qPr    = EqP − EdP  I  3 V VqN  dN  dNr    I qNr  VqN − VdN

EdN EqN VdP − VqP

EqN   − EdN  VqP   VdP 

−1

 P0 r    Q0 r   Pvc 2 r     Pvs 2 r 

(12)

We can see from (11) and (12) the NS current components are necessary in achieving the control objectives, and the reactive power ripples are not controlled.

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4. Design of the BSMC current control scheme

4.1. System dynamic model for controller design Dynamic model of VSR for current controller design can be expressed as:

x& = F ( x ) + G ( x ) u + δ ( t , x ) where x =

T

[ x11 x21 x31 x41 ]

(13)

= [ I dP I qP I dN I qN ]T denotes the state variable, G ( x ) denotes T

T

the control gain matrix, u = [u1 u2 u3 u4 ] = udP uqP udN uqN  denotes the control input, F ( x) =

[ f1 (x)

T

f 2 (x) f 3 (x) f 4 (x) ] denotes the nonlinear function vector, Function δ i1 ( t , x )

denotes the lumped uncertainty introduced by model simplification, parameter uncertainty and external disturbance, etc, with: EqP R  EdP R − I dP + ω I qP , f 2 ( x ) = − I qP − ω I dP  f1 ( x ) = L L L L (14)   f ( x ) = EdN − R I − ω I , f ( x ) = EqN − R I + ω I dN qN 4 qN dN  3 L L L L

 g1 ( x )   g2 ( x) G ( x) =   g3 ( x ) g ( x)  4

 0 0  Vdc L 0    0 Vdc L 0 0     = − 0 0 Vdc L 0      0 0 0 Vdc L    

δ ( t , x ) = δ11 ( t , x ) , δ 21 ( t , x ) , δ 31 ( t , x ) , δ 41 ( t , x ) 

(15)

T

(16)

Assume δ i1 ( t , x ) satisfies: δ i1 ( t , x ) gi ( x ) ≤ ai1 ( x )

(17)

where ai1 ( x ) ≥ 0 is a known and bounded function. T

T

Denote xr1 = [ x1r x2 r x3r x4 r ] =  I dPr I qPr I dNr I qNr  as the current reference vector, and T

denote the integral of xr1 as xr 0 = [ x1r 0 x2 r 0 x3r 0 x4 r 0 ] . Define zi 0 = xi 0 − xir 0 the integral of system state error, we have:

z&i 0 = xi1 − xir1 + δ i 0 ( t , x )

(18)

where δ i 0 ( t , x ) represents the lumped uncertainty introduced by the integral approximation, calculation error, and so on, and it’s assumed: (19) δ i 0 ( t , x ) ≤ ai 0 zi 0 for some ai 0 > 0 . Inequality (19) restricts the upper bound of δ i 0 to depend only on zi 0 . Nevertheless, it’s less restrictive than the matching condition that would have required δ i 0 = 0 . The complete dynamic equations of the VSR for controller design can be represented as:

 z&i 0 = xi1 − xir1 + δ i 0 ( t , x )   x&i1 = f i ( x ) + gi ( x ) ui + δ i1 ( t , x )

(20)

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4.2. Design of the BSMC control law In the following, arguments of various functions will not be written for the sake of convenience. After integral augmentation, system model (20) becomes a cascaded connection of an integrator with the x subsystem. Utilize Vi 0 = zi20 2 as a Lyapunov function candidate, the derivative of Vi 0 along state trajectories can be obtained as: (21) V&i 0 = zi 0 z&i 0 = zi 0 ( xi1 − xir1 + δ i 0 ) If we take xi1 = −ci 0 zi 0 + xir1 , then, we have: V&i 0 = zi 0 ( −ci 0 zi 0 + δ i 0 )

(22)

If ci 0 is chosen such that ci 0 > ai 0 , and thus stabilization of zi 0 can be guaranteed. Take zi1 = xi1 + ci 0 zi 0 − xir1 , where zi1 is a virtual control variable and define si = zi1 as the sliding manifold. Using Vi1 = Vi 0 + 0.5 zi21 = zi20 + zi21 2 as a composite Lyapunov function candidate, it can be obtained: (23) z&i1 = fi + gi ui + δ i1 + ci 0 z&i 0 − x&ir1

(

)

V&i1 = −ci1 zi20 + δ i 0 zi 0 + zi 0 zi1 + zi1 ( fi + gi ui + δ i1 + ci 0 z&i 0 − x&ir1 )

(24)

If the control law ui is designed as:

ui =

−1 ( fi + ci 0 z&i 0 − x&ir1 + ci1 zi1 + zi 0 ) + βi sgn ( si ) gi

(25)

where ci1 > 0 , and βi > ai . Then, we have:

V&i1 = −ci 0 zi20 + δ i 0 zi 0 − ci1 zi21 − βi zi1 + δ i1 ≤ − ( ci 0 − ai 0 ) zi20 − ci1 zi21 − ( βi − ai1 ) zi1 ≤ 0 (26) As x&ir1 = 0 for current regulation, then ui can be expressed as:

ui =

−1 ( fi + ci 0 z&i 0 + ci1 zi1 + zi 0 ) + βi sgn ( zi1 ) gi

(27)

According to Barbalat’s lemma, xi1 → xir1 can be proved according to the definition of z1 . Moreover, each of the SM cannot be zero under steady state due to the integral actions, and thus the chattering problem exist in conventional SMC controller is naturally solved. 5. Simulation studies

5.1. System Configuration The control block diagram of the BSMC current control scheme is as shown in Fig. 2. It mainly consists of an outer dc link voltage control loop and an inner ac current control loop, where the dc link voltage is controlled by a PI controller. Products of dc voltage reference and the output of the dc voltage control loop are taken as the average active power reference, which is to be used to generate the current reference. Input voltages are available from the measurement at the input terminal, the converter pole voltages are obtained from the SVPWM reference of the last control period. The obtained

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control commands in the PNS SRF are used to generate the SVPWM signal to control the switching devices after they’re transformed into the static two-phase reference. Sequence component extraction for ac voltage and current are realized in the PS and NS SRF respectively. They’re firstly passed through low pass filters, and then notch filters to remove high frequency noises and the 2nd-order harmonics produced during reference transformation. Phase-locked loop in the d-q reference with variable frequency mean value function is adopted which can provide accurate synchronous signals even in the presence of harmonics. Notch filters with a characteristic frequency of 100 Hz and a quality factor of 10 are selected, as they can provide satisfactory accuracy with negligible time delays.

Fig. 2. The control block diagram of the BSMC current control scheme 5.2. Simulation results Detailed electrical parameters of the VSR tested are listed in Table 1. For comparison, a PI controller is designed of which the proportional gain and integral gain are set to 12 and 160 respectively. Both of the two current controllers share the same structure and identical voltage control loop parameters. Table 1: Parameters of the VSR designed for simulation study Parameter

Value

Parameter

Value

AC input voltage Nominal DC voltage AC line resistance

380/660 Vrms 1500 V 6.3 mΩ

Rated power AC line inductance DC capacitor

300 kW 0.9 mH 15 mF

Main parameters of the BSMC controller are listed in Table 2. Table 2: Main parameters of the proposed BSMC current control scheme Voltage control loop Parameter

Current control loop

Proportional Gain

Value 1.2

Parameter Coefficient ci0

Value 50

Integral Gain

36

Coefficient ci1

600

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Discrete model with a simulation step length of 1 µs is used. Both the control period and the sampling period are 100 µs. The switching frequency is 2.0 kHz; a dead time of 2 µs is set for the gate on command of each switching device. In addition, considering time delays exist in the control loops in practice, a 100 µs time delay is inserted between the modulation reference output and the SVPWM generator. In the simulation results, the per-unit values are used. The base voltages are 540 V for ac system and 1500 V for dc system. The base power is 300 kVA. The active power is measured at the converter pole; the reactive power is measured at the power input terminal. In Fig. 3 (A)-(B), system responses to load step changes under balanced input voltage condition by the PI and BSMC current controllers are shown respectively. The initial load is 150 kW; it is stepped to 300 kW at 0.05 s and then stepped back to 150 kW at 0.2 s.

(A) (B) Fig. 3. System responses to load step changes under balanced input voltage by (A) PI controller and (B) BSMC controller for (a) dc link voltage, (b) ac current, and (c) active power (solid line) and reactive power (dashed line). We can see from Fig. 3 the transient and steady state responses of the VSR with both the two controllers are satisfactory in balanced input voltage situation. We can also find from the figures the control of the active power and reactive power are almost decoupled, i.e., the load step changes has negligible impacts on reactive power. In Fig. 4 (A)-(B), system responses to power step changes under balanced input voltage condition when the ac line inductance is changed to 0.7 mH are shown. This poses more severe threat to system stability than when the inductance is greater than the nominal value.

(A) (B) Fig. 4. System responses to load step changes under balanced input voltage when the inductance is 0.7 mH by (A) PI controller and (B) BSMC controller for (a) dc link voltage, (b) ac current, and (c) active power (solid line) and reactive power (dashed line).

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We can see from the figures although dc link voltage can be finally stabilized for the PI controller, ac currents become unbalanced due to lack of sufficient damping. Consequently, active and reactive power ripples are produced. For the BSMC controller, both transient and steady state performance are still satisfactory under this operating condition. In the following, the performance of the VSR with the BSMC controller in the presence of input voltage unbalance is investigated. Assume that 1) the neutral point of the input terminal is grounded to prevent the neutral point offset under unbalance, and 2) there exist parameter uncertainty and the ac line inductance is 0.8 mH. Fig.5 (A)-(B) show system responses of the VSR to load step changes under two-phase voltage unbalance. For Fig.5 (A), the amplitudes of three-phase voltage are 486, 540 and 594 V respectively (cond. #1), and for Fig.5 (B), the amplitudes of three-phase voltage are 486, 486 and 540 V respectively (cond. #2). For both of the two cases, the initial load is 150 kW. At 0.05s, the load is stepped to 300 kW, and then stepped back to 150 kW at 0.2 s.

(A) (B) Fig. 5 System responses to load step changes with BSMC controller under unbalanced input voltage cond. #1 (A), cond. #2 (B) for (a) dc link voltage, (b) ac input voltage, (c) ac current, (d) active power (solid line) and reactive power (dashed line). From Fig.5 we can see that both transient and steady state performance of the VSR for the two cases are satisfactory with the BSMC controller. In the mean time, we can observe from the figures the active power at the converter pole is kept constant during steady state, while the reactive power at the input terminal oscillates at twice the fundamental frequency with about a zero average. Next, performance of the VSR under serious single phase voltage dips is investigated. In the first case, the amplitude of phase B is half the nominal value and phase A and C operate normally (cond. #3). The VSR is at an initial steady state with dc load of 150 kW. At 0.05s, the load is stepped to 300 kW and then stepped back to 150 kW at 0.2 s. In the second case, the amplitude of phase B is 30% lower than the nominal value and phase A and C are normal (cond. #4). The VSR is at an initial steady state with no load. At 0.05s, the load is stepped to 300 kW, and it is then shed completely at 0.2 s. Responses of the VSR to load variations under cond. #3 and cond. #4 are shown in Fig. 6(A) and Fig. 6(B) respectively.

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(A) (B) Fig. 6 System responses to load step changes with BSMC controller under unbalanced input voltage cond. #3 (A), cond. #4 (B) for (a) dc link voltage, (b) ac input voltage, (c) ac current, (d) active power (solid line) and reactive power (dashed line). In Fig.7 (A)-(B), responses of the VSR to load step changes with the BSMC controller under unbalanced input voltage caused by phase asymmetry are shown. For Fig.7 (A), the initial phases of three phase voltage are 0, -3π/4, and 2π/3 (cond. #5), and for Fig.7 (B) the initial phases are 0, -13π/18, and 13π/18 (cond. #6), respectively. For both of the two cases, the system is at an initial steady state with dc load of 150 kW. At 0.05s, the load is stepped to 300 kW and it is stepped back to 150 kW at 0.2 s. The amplitudes of three-phase voltage are the nominal values for both of the two cases.

(A) (B) Fig. 7 System responses to load step changes with BSMC controller under unbalanced input voltage cond. #5 (A), and cond. #6 (B) for (a) dc link voltage, (b) ac input voltage, (c) ac current, (d) active power (solid line) and reactive power (dashed line). We can see from Fig.7 the VSR behaves satisfactorily under unbalanced input voltage conditions caused by phase asymmetry. This attributes to the control strategy and the robust control law adopted. As has been pointed out in section 3 that voltage unbalance caused by phase asymmetry can also be represented by the sum of the PS and NS components for the VSR studied. In Fig.8, system responses to serious voltage dip disturbance are shown. In this case, the system is at an initial steady state with rated power and balanced input voltage. At 0.05 s sudden voltage dip of phase B to 0.1 p.u happens and the voltage of phase B restores to the nominal value at 0.25 s (cond. #7). The dc load is 300 kW throughout this period. 720


Fig. 8 System responses to serious voltage sag disturbance with BSMC controller under input voltage cond. #7 for (a) dc link voltage, (b) ac input voltage, (c) ac line current, (d) active power (solid line) and reactive power (dashed line). We can see from Fig.8 the VSR can ride through this serious voltage disturbance with the BSMC current control scheme. Constant dc link voltage and sinusoidal ac line currents can be obtained under steady state, although it takes a long time for the system to reach the steady state. One thing to note is the amplitude of ac currents rise to large values during the transient process and the amplitude of reactive power consumed is close to unity, which deserves serious concern for the design of protection system. In the above simulation studies, degrees of the unbalanced input voltage conditions used are more severe than those specified by relative standards. We can see from the results the VSR behaves satisfactorily under different operating conditions, even in the presence of parameter uncertainties and large load disturbances. 6. Conclusion

This paper proposes a backstepping and SMC-based robust current control scheme for VSR under unbalanced input voltage conditions. The backstepping follows a systematic manner, and therefore the controller design process is simplified. The combined utilization of backstepping and SMC has the following three features. Firstly, the BSMC controller designed is in essence a PI equivalent controller, and thus accurate current control can be achieved. Secondly, as the SMC is adopted, robustness of the control system is guaranteed. Finally, integral action is included in each SM which cannot be zero in steady state, so that the chattering problem is solved. Besides, with the NS current compensation and through nullifying active power oscillation at the converter pole, both constant dc link voltage and sinusoidal ac current are obtained. Extensive simulation results show the proposed BSMC current control scheme can provide satisfactory performance and strong robustness of the VSR over a large range of operating conditions. References [1] Rodriguez J R, Dixon J W, Espinoza J R, et al. PWM regenerative rectifiers: state of the art. IEEE Transactions on Industrial Electronics, 52(1), 5-22, 2005. [2] Kantar, Emre, and A. M. Hava. Optimal Design of Grid Connected Voltage Source Converters Considering Cost and Operating Factors. IEEE Transactions on Industrial Electronics, 63(9), 5336-5347, 2016.

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