Bidirectional Delta-Switch Indirect Matrix Converter: Topologies and Modulation Strategies Thiago B. Soeiro, Tiago K. Jappe, Pedro A. M. Bezerra and Marcelo L. Heldwein Federal University of Santa Catarina (UFSC) Electrical Engineering Department — Power Electronics Institute (INEP) Florian´opolis, SC — BRAZIL Telephone: +(55)48-9721-9204 E-mail: soeiro, tiagokj, pedroandre, [email protected]

Abstract—This work proposes novel three-phase ac-ac indirect matrix converter (IMC) topologies well-suited for voltage stepup operation, e.g. wind energy generation applications. The IMC systems employ a bidirectional delta-switch voltage source converter (VSC) as front-end stage and a bidirectional current source converter (CSC) as the back-end grid connected converter. Two space vector modulation schemes for the studied ac-ac converter featuring commutations under zero current or zero voltage are presented. Finally, in order to demonstrate the advantages of the new delta-switch IMC ( -IMC), a comparison of the proposed solution and conventional IMC rated to 10 kW is given for a permanent magnet synchronous generator based wind power system.

I. I NTRODUCTION Three-phase matrix converters (MCs) are frequently seen as a future concept for a wide range of applications which aim towards high power density with a particular focus on bidirectional variable-speed-drives [1]–[3]. These systems, also suited to voltage step-up applications, allow three-phase acac power conversion from a three-phase grid to a three-phase load with arbitrary voltage amplitude and frequency without any intermediate energy storage element. Accordingly, when compared to a conventional three-phase two-stage ac-dc-ac conversion, i.e. a voltage dc-link PWM back-to-back converter (V-BBC), MCs show higher power density and potentially higher reliability since electrolytic capacitors are not required [4]. Unfortunately, some of the advantages of the MCs are offset by the requirement of more semiconductor devices and regarding overvoltage protection. The conventional matrix converter (CMC) [5], [6] shown in Fig. 1 utilizes nine bidirectional, bipolar (four-quadrant) turn-off switches which perform the ac-ac voltage and current conversions in a single stage. A multi-step commutation strategy is employed to provide reliable current commutations between the switches, avoiding the short circuiting of an input line-to-line voltage or an abrupt interruption of an output phase current. In contrast, Indirect MCs (IMCs) have separate stages for the voltage and current conversions, similar to the V-BBC and the current dc-link BBC (C-BBC), but without an energy storage element in the intermediate link [4]. This provides an additional degree of control freedom that is not available for the CMC and can be used to alleviate the complex multistep

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Fig. 1. (a) Conventional matrix converter; basic ac-dc-ac converters: (b) V-BBC; and (c) C-BBC.

commutation. As proposed in [1], the VSC stage (VSCS) can be switched into a free-wheeling state and then the CSC stage (CSCS) can commutate with zero dc-link current. In this case, the short circuit of an input line-to-line voltage still needs to be avoided in the VSC stage. Alternatively, the commutation logic can be changed and the VSC stage can be set to commutate with zero dc-link voltage during the free-wheeling state of the CSC stage. Reference [4] provides a review of three-phase ac-ac converter topologies where several matrix-equivalent converters are presented based on the structure of the IMC, namely, Sparse MC (SMC), Ultra Sparse MC (USMC), Very Sparse MC (VSMC) [1], [7]–[9] and the Inverting Link MC (ILMC) [10]. These topologies are shown in Fig. 2, where the circuits are deliberately illustrated for step-up operation mode. A new MC concept is shown in Fig. 2(e) which is derived according to the active third harmonic injection converter technology presented in [11]–[13]. This matrix converter, first introduced in the literature by this paper, is named here as the third harmonic injection MC (3HIMC). An unidirectional step-up USMC has been proposed in [14] where the two-level bidirectional six-switch voltage source converter stage (VSC) is replaced by a unidirectional deltaconnected converter ( -VSC) (cf. Fig. 3). This delta-type

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Indirect matrix converter technology: (a) classic IMC; (b) ILMC; (c) SMC; (d) VSMC; e) 3HIMC; and f) USMC.

In this paper a class of delta-type IMCs ( -IMC) is proposed as shown in Fig. 4 exemplarily with the CSCS of Fig. 2(a). The new IMC topologies derive from the use of a VSCS that uses -connected switches. Thus, alternative implementations can be derived from known MCs, such as SMC, ILMC, VSMC, and 3HIMC, by connecting three bidirectional, bipolar (four-quadrant) switches among the phase a, b, and c terminals of the VSCS. When compared to the IMC concepts

used to assemble the -IMCs, the new solutions possess the shortcomings of the requirement of a higher amount of power semiconductors and isolated gate drives, however they can deliver higher efficiency. In Section II, two known multi-step commutation strategies for IMCs are adapted for the proposed -IMC concept. A Space Vector Modulation (SVM) scheme providing zero current or zero voltage commutation for one of the converter stages and high power factor operation are shown. Finally, in order to demonstrate the advantages of the -IMC, a power loss comparison with a conventional IMC rated to 10 kW is given for a permanent magnet synchronous generator (PMSG) based wind energy conversion system (WECS) connected to a 380 V / 50 Hz grid. II.

-IMC S PACE V ECTOR M ODULATION

Fig. 4 shows a power efficient IMC solution assembled by cascading a delta-switch PWM voltage source converter ( -VSC) and two mutually anti-parallel-connected currentlink PWM converters without any intermediate energy storage element. With respect to the principle of operation, this IMC represents a combination of the input stage of a delta-switch V-BBC with the dc-link capacitor moved to the grid side (CSC stage), and the output stage of a C-BBC with the dc-link inductor moved to the -VSC stage. Fig. 5 illustrates the idealized circuit representation of the -IMC. From the output stage only positive line-toline voltages are switched to the link, u, and the desired

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USMC, named here as -USMC, is well-suited for wind power generation systems, where low inductance machines are used because it provides full control of the input currents, i.e. as long as the fundamental phase displacement angle of the voltage and current is lower than ± ⇡6 rad. Interestingly, in contrast to the conventional USMC, the -USMC is bridgeleg short-circuit proof. Thus, recalling that the Current Source Converter (CSC) stage can be commuted with zero dc-link current, a safe multistep commutation method, featuring low complexity, can be employed. Another advantage is that the current circulating through the delta-type switches is smaller than for the VSC. Thus, more robustness and higher efficiency than the USMC is achievable. However, it is advantageous that for large scale (> 100 kW) applications the power conversion system exhibits bidirectional capability in order to drive the wind turbine when it starts and also to perform system testing.

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Fig. 3. Delta-switch ultra sparse matrix converter. a) basic structure; and b) alternative bidirectional, bipolar (four quadrant) switches.

S2p

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ia vt,ab

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vt,ca ic

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Fig. 4.

S3n

Delta indirect matrix converter –

-IMC.

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i S5p/6p/7p

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Fig. 5.

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Idealized circuit representation of the

CSC stage

-IMC.

terminal voltages, vt,abc , used for shaping the input currents ia,b,c , should be formed with two or three different voltage levels within each pulse half period (cf. Fig. 6). The output currents iA,B,C are then formed by segments of ia,b,c with a predetermined phase reference displacement angle, 2 . The switching states available for controlling the VSC and CSC circuit stages of the -IMC are given in Tab. I and II, respectively. As can be seen in Tab. I, the -VSC is able to apply seven different voltage space vectors in the input terminals, Vo V6 , where multiple redundant states are feasible for each one of these vectors. There, the switches assigned with ”*” do not influence the vector definition since this is defined by other switches. However, turning these non-defining switches on provides parallel current paths that potentially reduce conduction losses when compared to a conventional VSC. Therefore, employing high current semiconductors or RBIGBTs in the delta section of the VSC can reduce conduction losses. Unfortunately, these devices present relatively high switching losses. In order to take advantage of the low forward voltage drop of such devices and not to increase the switching losses with respect to a conventional VSC, the -IMC could be operated with a SVM featuring zero-voltage-switching (ZVS) for the VSC stage. Alternatively, a SVM with a special multi-step commutation scheme could be used where the nondefining delta switches could be always turned off prior to a vector transition and every-time it could be turned on later than a defining state switch, thus both transitions for the delta connected devices would occur under zero voltage. In this case, the -IMC could be operated with a SVM featuring zero-current-switching (ZCS) for the CSC stage. Considering the 60o wide interval of the grid period '2 2 [ 30o , 30o ], only the switching states I1 , I2 and I3 or correspondingly the line-to-line voltages uAC , uAB and uBC can be used to generate the required positive dc-link voltage (u > 0). Consequently, the VSC stage can form a different space vector hexagon for each one of these dc-link voltages, resulting in a total of 18 different effective active voltage vectors and a zero vector (cf. Fig. 6(a)). On the other hand, for the VSC stage period interval '1 2 [ 30o , 30o ] (ia > 0, ib < 0 and ic < 0), positive instantaneous dclink current i could be achieved by employing V 1(i = ia ), V 2(i = ic ) and/or V 6(i = ib ), while negative i could be implemented by V3 (i = ib ), V4 (i = ia ) and/or V5 (i = ic ).

Hence, the dc-link current i is translated into output current space vectors according to the switching state of the CSC stage (cf. Fig. 6(b)). Note that during the free-wheeling states V0 and I0 no dc-link voltage/current can be formed, and thus, no input voltage/output current can be generated. In this work the two multi-step commutation schemes for IMCs presented in [4] are adapted to the -IMC. These modulation strategies, which obtain the highest possible dclink voltage/current amplitude available for the formation of the input voltage or output current terminals by employing only the switching states resulting in the largest and medium instantaneous voltage/current are shown in Fig. 7. A power transfer from the CSCS to the VSCS within the intervals 'u1 2 [0o , 30o ] and 'i2 2 [0o , 30o ] is considered. The active sectors are marked in the diagrams depicted in Fig. 6. As shown in Fig. 7(a) it is feasible to command the switches of the CSC stage with a zero-current-switching, as in this structure a change of state occurs only during the freewheeling state of the VSC stage (i = 0). Alternatively, the

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Fig. 6. Space vector diagrams for the a) input and b) output stage of the -IMC. Note that in the dotted region depicted in b), i.e. I4 , I5 and I6 , a positive dc-link voltage u > 0 can only be formed by inversion of the dc-link current, i .

TABLE I S WITCHING STATES AND VOLTAGE SPACE VECTORS FOR THE VSC- STAGE OF THE -IMC. TABLE. I: Switching states and voltage space vectors for the VSC-stage of the -IMC. Vo

V1 Vo V2 V1 V3 V2 V4 V3 V5 V4 V6 V5 V6

Io I1 I2 I3o I4 I51 I62 I3 I4 I5 I6

S1p 0 1 0 S*1p 10 1 10 1* 1 *1 01 01 01 0* 0 0 0 0 0 10 10 *0 0 1 1 *

S5p 1 0 0 S15p 1 0 0 01 01 0 0 0 0

S2p 0 1 0 S*2p 0 01 0 1* *0 10 10 1 1* 1 1 *1 01 01 01 0* 0 0 0 0 0 0

S3p S1n S2n S3n Sab Sbc Sca vt,ab vt,bc 1 1 1 * * * 0 * * * 0 0 0 1 0 0 * of the -IMC. * VSC-stage * 1 space vectors 1 and voltage 1 0 TABLE. I: Switching states for the S*3p S01n S02n S03n S1ab S1bc S1ca vt,ab vt,bc 0 10 1* 10 *1 *1 *0 01 +u 0 *0 *1 *0 0* 01 0 0 0 0 0 * 1 0 1 *0 * * 1 1 0 0 * 1 0 0 0* 1 1 1 0 0 +u 0 0 10 1 01 *0 0 0 0 10 *1 01 10 0 +u 0 0 01 *0 1 0 10 0* -u +u 0 01 0 *0 1* 0 01 0 01 0 +u 0 10 1 0 0* 10 0 0* 10 10 0 01 *0 -u 0 *0 01 0 10 0 1 10 1 0 0 0 1 10 -u +u 0 * 0 0 * 0 1 1 10 1 0 1 0 * 0 -u 1 1 0* 0 01 *0 0 1* 1* 01 0 01 10 0 -u 0 1 10 01 0 0 10 0* +u -u *1 01 0 *0 0 1 10 1 01 0 -u 0 10 0 *1 10 0 0 1 0 1 * 1 * of the -IMC. 0 CSC-stage 0 0 1 and current 0 1 TABLE. II: Switching states space vectors for the +u it,B -u 1 it,A 0 0 0 1 S5n 0S7p S6p * S6n II S7n TABLE 1 0 0 1 1 00 0 1 0 0 00 0 S WITCHING STATES AND CURRENT SPACE VECTORS FOR THE CSCSTAGE OF THE -IMC. 1 0 0 1 0 0 0 states 0and current space 0TABLE. II: Switching 1 0 vectors for 1the CSC-stage0of the -IMC.0 -i S06p S07p S05n S16n S07n i+i it,B t,A 0 0 10 0 01 0 00 +i 0 0 10 01 0 0 1 +i 10 01 0 10 0-i 0 10 +i 01 01 10 0 +i -i0 0 -i 01 0 01 10 +i 0-i 0 0 1 0 0 0 1 0 +i 1 0 1 0 0 -i +i 0 1 1 0 0 -i 0 0 1 0 1 0 0 -i

active switches of the VSC stage can be operated with zerovoltage-switching by performing the switch commutations only when the CSC stage is in a free-wheeling state (u = 0). (cf. Fig. 7(b)). For the SVM featuring ZCS or ZVS depicted in Fig. 7, the -IMC transfer ratio can be determined as a ˆ1/2 function of the input and output ac voltage amplitudes U and the phase displacement between the fundamental output current and voltage, 2 ,

vt,ca

i 0 0 0 i0 +i 0a +i 0a +i 0a -i 0c -iac +i -iac +i +iab +i +i -icb +i -icb -i-ica -iba +i -iba +i +i +ibc +iac -i +iac -i -i-iab -ibc +i -ibc +i +ic -ib u-ib 0-ib 0 0 uuAB 0 uAC u0BC u0BA uuAB CA uuAC CB uBC uBA uCA uCB

0 vt,ca

-u 0 -u -u 0 -u +u 0 +u +u 0 +u it,C 0 0 0 0 0 it,C 0-i 0-i 00 0 +i -i +i -i 0 +i +i

where Iˆ1/2 are the input and output current amplitudes, and 1 is the phase displacement between the fundamental input current and voltage. The relative turn-on times of the ZCS or ZVS commutation schemes depicted in Fig. 7 for sinusoidal SVM can be directly calculated by the combination and multiplication of the relative turn-on times of the CSC and VSC stages. For 30o < 2 < 30o , the relative turn on times can be determined by :

⇣ ⇣ ⇡⌘ ⇡⌘ d(I~ )(V~ ) = M12 cos 'i2 cos 'u1 + (4) 2 1 3 6 ⇣ M12 = p = 0 ... 1 (1) ⇡⌘ ˆ 3U2 cos ( 2 ) d(I~ )(V~ ) = M12 cos 'i2 sin ('u1 ) (5) 2 2 3 ⇣ ⇡⌘ Therefore, ideally the input voltage range of the -IMC for d(I~ )(V~ ) = M12 cos 'i2 + sin ('u1 ) (6) 1 2 3 ⇣ ⇣ sinusoidal modulation, considering M12 = 1 and 2 = 0, is ⇡⌘ ⇡⌘ I5 and'Iu1 positive dcFig. 6. Space vector diagrams for the a) input and b) output stage of the -IMC. Note that in the depicted ini2b),+i.e. I4,cos 6, a+ d(I~dotted = M12 cos ' (7) ~ region 1 )(V1 ) givenlinkbyvoltage u>0 can only be formed by inversion of the dc-link current, i. 3 6 p 3 ˆ semiconductors or RB- The remaining state time equal tothus both Therefore, employing turned on laterrelative than azero defining stateis switch, ˆ1 high U =for0 the ...current U2 and b) output stage of the (2) Fig. 6. Space vector diagrams a)2input -IMC. Note that in the dotted region depicted in b), i.e. I4, I5 and I6, a positive⌘ dc⇣for IGBTs in the delta section of the VSC can reduce conduction transitions the delta connected devices would occur under link voltage u>0 can only be formed by inversion of the dc-link current, i. d0 = 1 d(In + d(I~the + d(I~could + doperated 0 a (8) ~ )( ~ )case, I V losses. Unfortunately, these devices present relatively high zero voltage. this )(V~ )-IMC )(V~ ) be (I~ )(V~ ) with ˆ1 2U

However, in practice the high maximum modulation indexormust Therefore, employing current switching losses. In order to take semiconductors advantage of the RBlow be limited, i.e. M ⇡ 0.98, in order always ensure that 12 section of the VSCtocan IGBTs in the delta reduce conduction forward voltage drop of such devices and not to increase the one switching structure uses the states within the the pulse losses. Unfortunately, these devices present relatively highlosses withfree-wheeling respect to a conventional VSC, switching losses. In order toa soft-switching take advantage of the low period, TPcould , thus a safe IMC bepreserving operated with SVM featuringcommutation zero-voltageforward voltage drop of such devices and not to increase the of the other structure. This leads to a small reduction the switching (ZVS) for the VSC stage. Alternatively, aofSVM switching losses with respect to a conventional VSC, the maximum attainable input voltage. with a special multi-step commutation scheme could be usedIMC could be operated withtransformation a SVM featuring zero-voltagewhere the non-defining delta switches could is begiven always The input-to-output current byturned switching (ZVS) for the VSC stage. Alternatively, a SVM off prior to a vector p transition and every-time it could be with a special multi-step3 commutation scheme could be used ˆ ˆ I2 = delta M12switches I1 cos ( 1could ) (3) where the non-defining be always turned 2 off prior to a vector transition and every-time it could be

2

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turned on later zero-current-switching than a defining state(ZCS) switch,forthus SVM featuring the both CSC o o For 30 > > 30 , the dc-link voltage could become transitions for the delta connected devices would occur under 2 stage. zeroConsidering voltage. this case, -IMC could operated a of negative (u [-30 ,30 ],byonly the switching states I1,a Idifferent 2 and Ispace 3 or 0). given Consequently, the VSC stage can form are , u and u correspondingly the line-to-line voltages u AB BC can vector hexagon for each one of theseACdc-link voltages, ˆ1 dc-link voltage (u > be used to generate 3ˆ 1the required¯ positive U u ¯ = U2 and i = Iˆ1 cos ( 1 ) cos (!2 t) (9) ˆform 0). Consequently, VSC stage can a different space 2 costhe (!2 t) U 2 vector hexagon for each one of these dc-link voltages,

2

,

TABLE III S WITCHING SEQUENCES OF THE -IMC FOR OPERATION WITH SVM FEATURING ZCS OR ZVS COMMUTATION FOR VARIOUS COMBINATION OF TABLE. III: Switching sequences of the -IMC for operation with SVM INPUT AND OUTPUT SECTORS . S EE In /Vn VECTORS IN TAB . I AND II. (10) THEfeaturing ZCS or ZVS commutation for various combination of the input and output sectors. See In/Vn vectors in Tab. I and II. -IMC Sectors

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CSC

tervals are

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Switching Sequence (0 … TP/2)

VSC

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I

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(13)

I

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(14) , these time

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(17) , output space twelve 30oand output he resulting he reference * 2 , sectors ig. 8 shows put, dc-link, modulation

d

SVM with ZCS

SVM with ZVS

…(I2)(V1)-(I2)(V2)-(I2)(V0)(I1)(V0)-(I1)(V2)-(I1)(V1)… …(I2)(V2)-(I2)(V1)-(I2)(V0)(I1)(V0)-(I1)(V1)-(I1)(V2)… …(I2)(V2)-(I2)(V3)-(I2)(V0)(I1)(V0)-(I1)(V3)-(I1)(V2)… …(I2)(V3)-(I2)(V2)-(I2)(V0)(I1)(V0)-(I1)(V2)-(I1)(V3)… …(I2)(V3)-(I2)(V4)-(I2)(V0)(I1)(V0)-(I1)(V4)-(I1)(V3)… …(I2)(V4)-(I2)(V3)-(I2)(V0)(I1)(V0)-(I1)(V3)-(I1)(V4)… …(I2)(V4)-(I2)(V5)-(I2)(V0)(I1)(V0)-(I1)(V5)-(I1)(V4)… …(I2)(V5)-(I2)(V4)-(I2)(V0)(I1)(V0)-(I1)(V4)-(I1)(V5)… …(I2)(V5)-(I2)(V6)-(I2)(V0)(I1)(V0)-(I1)(V6)-(I1)(V5)… …(I2)(V6)-(I2)(V5)-(I2)(V0)(I1)(V0)-(I1)(V5)-(I1)(V6)… …(I2)(V6)-(I2)(V1)-(I2)(V0)(I1)(V0)-(I1)(V1)-(I1)(V6)… …(I2)(V1)-(I2)(V6)-(I2)(V0)(I1)(V0)-(I1)(V6)-(I1)(V1)… …(I2)(V1)-(I2)(V2)-(I2)(V0)(I3)(V0)-(I3)(V2)-(I3)(V1)…

…(I2)(V1)-(I1)(V1)-(I0)(V1)(I0)(V2)-(I1)(V2)-(I2)(V2)… …(I2)(V2)-(I1)(V2)-(I0)(V2)(I0)(V1)-(I1)(V1)-(I2)(V1)… …(I2)(V2)-(I1)(V2)-(I0)(V2)(I0)(V3)-(I1)(V3)-(I2)(V3)… …(I2)(V3)-(I1)(V3)-(I0)(V3)(I0)(V2)-(I1)(V2)-(I2)(V2)… …(I2)(V3)-(I1)(V3)-(I0)(V3)(I0)(V4)-(I1)(V4)-(I2)(V4)… …(I2)(V4)-(I1)(V4)-(I0)(V4)(I0)(V3)-(I1)(V3)-(I2)(V3)… …(I2)(V4)-(I1)(V4)-(I0)(V4)(I0)(V5)-(I1)(V5)-(I2)(V5)… …(I2)(V5)-(I1)(V5)-(I0)(V5)(I0)(V4)-(I1)(V4)-(I2)(V4)… …(I2)(V5)-(I1)(V5)-(I0)(V5)(I0)(V6)-(I1)(V6)-(I2)(V6)… …(I2)(V6)-(I1)(V6)-(I0)(V6)(I0)(V5)-(I1)(V5)-(I2)(V5)… …(I2)(V6)-(I1)(V6)-(I0)(V6)(I0)(V1)-(I1)(V1)-(I2)(V1)… …(I2)(V1)-(I1)(V1)-(I0)(V1)(I0)(V6)-(I1)(V6)-(I2)(V6)… …(I2)(V1)-(I3)(V1)-(I0)(V1)(I0)(V2)-(I3)(V2)-(I2)(V2)…

aturing a) ZCS

as

P

2

P

d(I~ )(V~ ) , t0 = d0 1 1 2

In order to quantify the feasibility of the proposed threephase -IMC concept depicted in Fig. 4, operating with the SVM schemes enabling ZCS or ZVS of one of its converter stages as explained in Section II, a power loss analysis is presented in this section. The converter specifications considered are: P o = 10 kW, uA,rms = 220 V(50 Hz), and switching frequency fP = T1P = 18 kHz. Suitable commercial semiconductors are considered, where were IGBTs IKW40N120H3 is used in the CSCS, while RB-IGBT IXRH40N120 and IGBT IXA20IF1200HB in the VSCS. The computed semiconductor power losses for the two SVM schemes are presented in Fig. 9 for operation in the range of 10% to 100% of the rated power of a WECS that features a low inductance PMSG. Fig. 9 considers only the voltage stepup operation, where the power flows from the VSCS to the CSCS. The SVM featuring the ZCS commutation scheme is the solution facing the lowest semiconductor power losses. The results shows that at full power the -IMC operating under ZCS attains a pure semiconductor efficiency above 97%. IV. C ONCLUSIONS

stages [cf. Section II], a power loss comparison between this system and the IMC shown in Fig. 2(a), is presented in this section. The converter specifications considered are: Po=10 Finally, the time intervals shown in Fig. 7 can be computed uA,rms=220V(60Hz), and switching frequency fP = 1/TP= askW, follows posed three- 18kHz. A suitable commercial semiconductor is considered TP TP TP calculations ng with the in the ta = d(I~ )(V~ (IGBTs , tb = IKW40N120H3). d(I~ )(V~ ) , tc = d(I~ )(V~ ) (10) 2 1) 2 2 1 2 2 2 2 losses In Fig. 10 the pure semiconductor power of the ts converter T T td =

III. C OMPARATIVE E VALUATION

(11)

This work proposes a novel three-phase ac-ac indirect matrix converter well-suited for wind energy generation applications. The IMC system employs a bidirectional delta-switch voltage source converter as front-end and a bidirectional current source converter as back-end converter. In addition, two space vector modulation schemes for the studied ac-ac converter featuring zero current or zero voltage commutations were presented. Finally, the feasibility of the new delta-switch IMC was demonstrated by a power loss analysis for a 10 kW conversion system. The results showed that at full power the

For SVM featuring ZCS these time intervals are distributed t0 TP + t0 and tB = + tc + td 2 2 t1 = ta , t 2 = t1 + tb , t 3 = t2 + t0 , t 4 = t3 + tc , t5 = t4 + 2td , t6 = t5 + tc , t7 = t6 + t0 , t8 = t7 + tb ,

tA = ta + tb +

(12)

u 0

(13) (14)

As presented in Fig. 6, the resulting input and output space vector diagrams of the -IMC can be divided in twelve 30o wide intervals, which gives 144 different input and output sector combinations. For example, Tab. III lists the resulting switching sequences for some combinations of the reference input voltage, ~u⇤1 , and reference output current, ~i⇤2 , sectors for the SVM with ZCS and ZVS commutations. Fig. 8 shows simulation results indicating the characteristic input, dc-link, andb)output waveforms of the -IMC for these modulation and b) ZVS commutations. The -VSC stage is set to operate with half schemes.

-ic

-ic

-ic

ia i 0 uAC u

uAB

I2

0

I1 t1

V1

V2

uAC uAB uAB

time t8

TP

ia

-ic

V1

ia

-ic

1 V1 V2 V0 V0V2V1 2 TP 0 t1 t2 tA t3 t4 t5 t6 tB t7 (b)

time

I2

I1

ia

i

(15) (16) (17)

uAC

uAB

I2

ia

On the other hand, for SVM featuring ZVS these time intervals are distributed as t0 TP + t0 tA = ta + td + and tB = + tb + tc 2 2 t1 = ta , t 2 = t1 + td , t 3 = t2 + t0 , t 4 = t3 + tc , t5 = t4 + 2tb , t6 = t5 + tc , t7 = t6 + t0 , t8 = t7 + td ,

uAC

(a)

uAB

I0 I 0 I 1 I 2 1 T P 2 t2 tA t3 t4 t5 t6 tB t7

time

uAC time

t8

TP

Fig. 7. Formation of the dc-bus voltage u and current i for multi-step commutation schemes featuring: (a) ZCS of the CSC stage, and (b) ZVS of the VSC stage. Note that while the switches of one stage operates with switching period TP the switches of the other stage operate at twice the frequency ( T2P ).

Fig. 8. Characteristic waveforms of the -IMC for SVM featuring a) ZCS and b) ZVS commutations. The period of the output stage (!a = 2!A = 4⇡50 rad/s.)

Fig. 9. Semiconductor power loss comparison between the different topologies of 10 kW IMCs employing commercial semiconductors (operating parameters: unity power factor; output voltage rms value uA,rms = 220 V (50 Hz); and switching frequency fP = 18 kHz.

-IMC operating under ZCS attained a pure semiconductor efficiency above 97%. ACKNOWLEDGMENTS This work is partially funded under grant 004/2010– PRONEX by CNPq/FAPESC. The authors would like to thank Mr. Daniel Collier for computing the generator maximum power operating points. R EFERENCES [1] J. Kolar, F. Schafmeister, S. Round, and H. Ertl, “Novel three-phase AC AC sparse matrix converters,” IEEE Transactions on Power Electronics, vol. 22, no. 5, pp. 1649 –1661, sept. 2007. [2] P. Zanchetta, P. Wheeler, J. Clare, M. Bland, L. Empringham, and D. Katsis, “Control design of a three-phase matrix-converter-based AC AC mobile utility power supply,” IEEE Transactions on Industrial Electronics, vol. 55, no. 1, pp. 209 –217, jan. 2008. [3] R. Gupta, K. Mohapatra, A. Somani, and N. Mohan, “Direct-matrixconverter-based drive for a three-phase open-end-winding AC machine with advanced features,” IEEE Transactions on Industrial Electronics, vol. 57, no. 12, pp. 4032 –4042, dec. 2010.

-VSCS is set to operate with half fundamental

[4] J. Kolar, T. Friedli, J. Rodriguez, and P. Wheeler, “Review of three-phase pwm AC AC converter topologies,” IEEE Transactions on Industrial Electronics, vol. 58, no. 11, pp. 4988 –5006, nov. 2011. [5] P. Wheeler, J. Rodriguez, J. Clare, L. Empringham, and A. Weinstein, “Matrix converters: a technology review,” IEEE Transactions on Industrial Electronics, vol. 49, no. 2, pp. 276 –288, apr 2002. [6] C. Klumpner, P. Nielsen, I. Boldea, and F. Blaabjerg, “A new matrix converter motor (M CM ) for industry applications,” IEEE Transactions on Industrial Electronics, vol. 49, no. 2, pp. 325 –335, apr 2002. [7] J. Kolar, M. Baumann, F. Schafmeister, and H. Ertl, “Novel three-phase AC DC AC sparse matrix converter,” in Seventeenth Annual Applied Power Electronics Conference and Exposition, APEC 2002., vol. 2, 2002, pp. 777 –791 vol.2. [8] L. Wei, T. Lipo, and H. Chan, “Matrix converter topologies with reduced number of switches,” in IEEE 33rd Annual Power Electronics Specialists Conference, 2002., vol. 1, 2002, pp. 57 – 63 vol.1. [9] F. Schafmeister, Sparse und Indirekte Matrix Konverter. Ph.D. dissertation, ETH Zurich, Switzerland, 2007. [10] J. Kolar and H. Ertl, “Status of the techniques of three-phase rectifier systems with low effects on the mains,” in The 21st International Telecommunication Energy Conference, INTELEC ’99., jun 1999, p. 16 pp. [11] T. Soeiro, T. Friedli, and J. Kolar, “Three-phase high power factor mains interface concepts for electric vehicle battery charging systems,” in Twenty-Seventh Annual IEEE Applied Power Electronics Conference and Exposition (APEC), feb. 2012, pp. 2603 –2610. [12] T. B. Soeiro, T. Friedli, and J. W. Kolar, “Design and implementation of a three-phase buck-type third harmonic current injection pfc rectifier sr,” IEEE Transactions on Power Electronics, vol. 28, no. 4, pp. 1608 –1621, april 2013. [13] T. Soeiro, T. Friedli, and J. Kolar, “Swiss rectifier: A novel threephase buck-type pfc topology for electric vehicle battery charging,” in Twenty-Seventh Annual IEEE Applied Power Electronics Conference and Exposition (APEC), feb. 2012, pp. 2617 –2624. [14] T. Jappe, S. Mussa, and M. Heldwein, “Analysis of indirect matrix converter topologies in voltage step-up operation mode,” in Brazilian Power Electronics Conference (COBEP), sept. 2011, pp. 930 –935. [15] T. Friedli, Comparative Evaluation of Three-Phase Si and SiC AC AC Converter Systems. Ph.D. dissertation, ETH Zurich, Switzerland, 2010.

Abstract—This work proposes novel three-phase ac-ac indirect matrix converter (IMC) topologies well-suited for voltage stepup operation, e.g. wind energy generation applications. The IMC systems employ a bidirectional delta-switch voltage source converter (VSC) as front-end stage and a bidirectional current source converter (CSC) as the back-end grid connected converter. Two space vector modulation schemes for the studied ac-ac converter featuring commutations under zero current or zero voltage are presented. Finally, in order to demonstrate the advantages of the new delta-switch IMC ( -IMC), a comparison of the proposed solution and conventional IMC rated to 10 kW is given for a permanent magnet synchronous generator based wind power system.

I. I NTRODUCTION Three-phase matrix converters (MCs) are frequently seen as a future concept for a wide range of applications which aim towards high power density with a particular focus on bidirectional variable-speed-drives [1]–[3]. These systems, also suited to voltage step-up applications, allow three-phase acac power conversion from a three-phase grid to a three-phase load with arbitrary voltage amplitude and frequency without any intermediate energy storage element. Accordingly, when compared to a conventional three-phase two-stage ac-dc-ac conversion, i.e. a voltage dc-link PWM back-to-back converter (V-BBC), MCs show higher power density and potentially higher reliability since electrolytic capacitors are not required [4]. Unfortunately, some of the advantages of the MCs are offset by the requirement of more semiconductor devices and regarding overvoltage protection. The conventional matrix converter (CMC) [5], [6] shown in Fig. 1 utilizes nine bidirectional, bipolar (four-quadrant) turn-off switches which perform the ac-ac voltage and current conversions in a single stage. A multi-step commutation strategy is employed to provide reliable current commutations between the switches, avoiding the short circuiting of an input line-to-line voltage or an abrupt interruption of an output phase current. In contrast, Indirect MCs (IMCs) have separate stages for the voltage and current conversions, similar to the V-BBC and the current dc-link BBC (C-BBC), but without an energy storage element in the intermediate link [4]. This provides an additional degree of control freedom that is not available for the CMC and can be used to alleviate the complex multistep

i

a u

b c A

a (b)

B

b

C

c

i

a

A

b

B

c

(a)

A B C

u

C

(c)

Fig. 1. (a) Conventional matrix converter; basic ac-dc-ac converters: (b) V-BBC; and (c) C-BBC.

commutation. As proposed in [1], the VSC stage (VSCS) can be switched into a free-wheeling state and then the CSC stage (CSCS) can commutate with zero dc-link current. In this case, the short circuit of an input line-to-line voltage still needs to be avoided in the VSC stage. Alternatively, the commutation logic can be changed and the VSC stage can be set to commutate with zero dc-link voltage during the free-wheeling state of the CSC stage. Reference [4] provides a review of three-phase ac-ac converter topologies where several matrix-equivalent converters are presented based on the structure of the IMC, namely, Sparse MC (SMC), Ultra Sparse MC (USMC), Very Sparse MC (VSMC) [1], [7]–[9] and the Inverting Link MC (ILMC) [10]. These topologies are shown in Fig. 2, where the circuits are deliberately illustrated for step-up operation mode. A new MC concept is shown in Fig. 2(e) which is derived according to the active third harmonic injection converter technology presented in [11]–[13]. This matrix converter, first introduced in the literature by this paper, is named here as the third harmonic injection MC (3HIMC). An unidirectional step-up USMC has been proposed in [14] where the two-level bidirectional six-switch voltage source converter stage (VSC) is replaced by a unidirectional deltaconnected converter ( -VSC) (cf. Fig. 3). This delta-type

CSCS A

a

b

B

b

C

c

u

c

i

VSCS

a

(a)

i

i

i VSCS

CSCS

u

VSCS

u

A

a

B

b

C

c

(b)

i CSCS

a

c

(d)

VSCS

B b

u

A B C

u

C c

(e)

(f)

Indirect matrix converter technology: (a) classic IMC; (b) ILMC; (c) SMC; (d) VSMC; e) 3HIMC; and f) USMC.

In this paper a class of delta-type IMCs ( -IMC) is proposed as shown in Fig. 4 exemplarily with the CSCS of Fig. 2(a). The new IMC topologies derive from the use of a VSCS that uses -connected switches. Thus, alternative implementations can be derived from known MCs, such as SMC, ILMC, VSMC, and 3HIMC, by connecting three bidirectional, bipolar (four-quadrant) switches among the phase a, b, and c terminals of the VSCS. When compared to the IMC concepts

used to assemble the -IMCs, the new solutions possess the shortcomings of the requirement of a higher amount of power semiconductors and isolated gate drives, however they can deliver higher efficiency. In Section II, two known multi-step commutation strategies for IMCs are adapted for the proposed -IMC concept. A Space Vector Modulation (SVM) scheme providing zero current or zero voltage commutation for one of the converter stages and high power factor operation are shown. Finally, in order to demonstrate the advantages of the -IMC, a power loss comparison with a conventional IMC rated to 10 kW is given for a permanent magnet synchronous generator (PMSG) based wind energy conversion system (WECS) connected to a 380 V / 50 Hz grid. II.

-IMC S PACE V ECTOR M ODULATION

Fig. 4 shows a power efficient IMC solution assembled by cascading a delta-switch PWM voltage source converter ( -VSC) and two mutually anti-parallel-connected currentlink PWM converters without any intermediate energy storage element. With respect to the principle of operation, this IMC represents a combination of the input stage of a delta-switch V-BBC with the dc-link capacitor moved to the grid side (CSC stage), and the output stage of a C-BBC with the dc-link inductor moved to the -VSC stage. Fig. 5 illustrates the idealized circuit representation of the -IMC. From the output stage only positive line-toline voltages are switched to the link, u, and the desired

i

i

VSCS

a

S1p

u

L1

A B C

a

L2 b

c

L3 c

(a)

CSCS

A a

USMC, named here as -USMC, is well-suited for wind power generation systems, where low inductance machines are used because it provides full control of the input currents, i.e. as long as the fundamental phase displacement angle of the voltage and current is lower than ± ⇡6 rad. Interestingly, in contrast to the conventional USMC, the -USMC is bridgeleg short-circuit proof. Thus, recalling that the Current Source Converter (CSC) stage can be commuted with zero dc-link current, a safe multistep commutation method, featuring low complexity, can be employed. Another advantage is that the current circulating through the delta-type switches is smaller than for the VSC. Thus, more robustness and higher efficiency than the USMC is achievable. However, it is advantageous that for large scale (> 100 kW) applications the power conversion system exhibits bidirectional capability in order to drive the wind turbine when it starts and also to perform system testing.

b

C

i CSCS

A B b C c

u

B

u

(c)

VSCS a

Fig. 2.

A

i

VSCS

b

CSCS

(b)

Fig. 3. Delta-switch ultra sparse matrix converter. a) basic structure; and b) alternative bidirectional, bipolar (four quadrant) switches.

S2p

CSCS

S3p

ia vt,ab

S5p

Sab

ib

S6p

S7p it,B

vt,bc Sbc

vt,ca ic

it,C S5n

S6n

S7n

Sca S1n

it,A

u>0

S2n

Fig. 4.

S3n

Delta indirect matrix converter –

-IMC.

A

B C

p

i S5p/6p/7p

at

a

At

S1p/n

A

Sab bt

b Sbc

c

Sca

Bt

S2p/n ct

Ct

S3p/n

∆−VSC stage

Fig. 5.

B

u>0

C

S5n/6n/7n

n

Idealized circuit representation of the

CSC stage

-IMC.

terminal voltages, vt,abc , used for shaping the input currents ia,b,c , should be formed with two or three different voltage levels within each pulse half period (cf. Fig. 6). The output currents iA,B,C are then formed by segments of ia,b,c with a predetermined phase reference displacement angle, 2 . The switching states available for controlling the VSC and CSC circuit stages of the -IMC are given in Tab. I and II, respectively. As can be seen in Tab. I, the -VSC is able to apply seven different voltage space vectors in the input terminals, Vo V6 , where multiple redundant states are feasible for each one of these vectors. There, the switches assigned with ”*” do not influence the vector definition since this is defined by other switches. However, turning these non-defining switches on provides parallel current paths that potentially reduce conduction losses when compared to a conventional VSC. Therefore, employing high current semiconductors or RBIGBTs in the delta section of the VSC can reduce conduction losses. Unfortunately, these devices present relatively high switching losses. In order to take advantage of the low forward voltage drop of such devices and not to increase the switching losses with respect to a conventional VSC, the -IMC could be operated with a SVM featuring zero-voltage-switching (ZVS) for the VSC stage. Alternatively, a SVM with a special multi-step commutation scheme could be used where the nondefining delta switches could be always turned off prior to a vector transition and every-time it could be turned on later than a defining state switch, thus both transitions for the delta connected devices would occur under zero voltage. In this case, the -IMC could be operated with a SVM featuring zero-current-switching (ZCS) for the CSC stage. Considering the 60o wide interval of the grid period '2 2 [ 30o , 30o ], only the switching states I1 , I2 and I3 or correspondingly the line-to-line voltages uAC , uAB and uBC can be used to generate the required positive dc-link voltage (u > 0). Consequently, the VSC stage can form a different space vector hexagon for each one of these dc-link voltages, resulting in a total of 18 different effective active voltage vectors and a zero vector (cf. Fig. 6(a)). On the other hand, for the VSC stage period interval '1 2 [ 30o , 30o ] (ia > 0, ib < 0 and ic < 0), positive instantaneous dclink current i could be achieved by employing V 1(i = ia ), V 2(i = ic ) and/or V 6(i = ib ), while negative i could be implemented by V3 (i = ib ), V4 (i = ia ) and/or V5 (i = ic ).

Hence, the dc-link current i is translated into output current space vectors according to the switching state of the CSC stage (cf. Fig. 6(b)). Note that during the free-wheeling states V0 and I0 no dc-link voltage/current can be formed, and thus, no input voltage/output current can be generated. In this work the two multi-step commutation schemes for IMCs presented in [4] are adapted to the -IMC. These modulation strategies, which obtain the highest possible dclink voltage/current amplitude available for the formation of the input voltage or output current terminals by employing only the switching states resulting in the largest and medium instantaneous voltage/current are shown in Fig. 7. A power transfer from the CSCS to the VSCS within the intervals 'u1 2 [0o , 30o ] and 'i2 2 [0o , 30o ] is considered. The active sectors are marked in the diagrams depicted in Fig. 6. As shown in Fig. 7(a) it is feasible to command the switches of the CSC stage with a zero-current-switching, as in this structure a change of state occurs only during the freewheeling state of the VSC stage (i = 0). Alternatively, the

Im u1,(I2)(V3)

uAC

IV u1,(I1)(V3)

u1,(I2)(V2)

III

uAB

u1,(I1)(V2)

II

V V3

VI

V2 u1,(I3)(V2)

u*1 ϕu1

u1,(I1)(V4)

u1,(I2)(V4)

uBC

u1,(I3)(V3)

I

φ1 i1 ϕi1

u1,(I2)(V1)

V1

V4 u 1,(I3)(V4) u1,(I0)(V0)

Re

u1,(I3)(V1) u1,(I1)(V1)

XII u1,(I3)(V5)

VII

u1,(I3)(V6)

uBC

V5

V6 u1,(I1)(V6)

u1,(I1)(V5)

VIII

XI

uAB

u1,(I2)(V6)

u1,(I2)(V5)

IX

X

uAC

Im i2,(I3)(V1)

i > 0 & u >0

III

IV

i2,(I3)(V2)

V

ia -ic

i2,(I4)(V4)

I3

i2,(I4)(V5)

i2,(I3)(V6)

i2,(I2)(V2)

-ib

I4

VI

i2,(I2)(V6)

i2,(I4)(V6)

I5

I2 u2

ϕu2 φ2

i2,(I0)(V0)

i2*

i2,(I2)(V1)

I

ϕi2

Re

i2,(I5)(V3)

VII

II

i2,(I1)(V6)

ib

XII

I1 i2,(I6)(V3)

i2,(I5)(V5)

i2,(I1)(V1)

ic

VIII

i0

i2,(I1)(V2)

I6

i2,(I5)(V4)

-ia

IX

XI i2,(I6)(V5)

X i2,(I6)(V4)

Fig. 6. Space vector diagrams for the a) input and b) output stage of the -IMC. Note that in the dotted region depicted in b), i.e. I4 , I5 and I6 , a positive dc-link voltage u > 0 can only be formed by inversion of the dc-link current, i .

TABLE I S WITCHING STATES AND VOLTAGE SPACE VECTORS FOR THE VSC- STAGE OF THE -IMC. TABLE. I: Switching states and voltage space vectors for the VSC-stage of the -IMC. Vo

V1 Vo V2 V1 V3 V2 V4 V3 V5 V4 V6 V5 V6

Io I1 I2 I3o I4 I51 I62 I3 I4 I5 I6

S1p 0 1 0 S*1p 10 1 10 1* 1 *1 01 01 01 0* 0 0 0 0 0 10 10 *0 0 1 1 *

S5p 1 0 0 S15p 1 0 0 01 01 0 0 0 0

S2p 0 1 0 S*2p 0 01 0 1* *0 10 10 1 1* 1 1 *1 01 01 01 0* 0 0 0 0 0 0

S3p S1n S2n S3n Sab Sbc Sca vt,ab vt,bc 1 1 1 * * * 0 * * * 0 0 0 1 0 0 * of the -IMC. * VSC-stage * 1 space vectors 1 and voltage 1 0 TABLE. I: Switching states for the S*3p S01n S02n S03n S1ab S1bc S1ca vt,ab vt,bc 0 10 1* 10 *1 *1 *0 01 +u 0 *0 *1 *0 0* 01 0 0 0 0 0 * 1 0 1 *0 * * 1 1 0 0 * 1 0 0 0* 1 1 1 0 0 +u 0 0 10 1 01 *0 0 0 0 10 *1 01 10 0 +u 0 0 01 *0 1 0 10 0* -u +u 0 01 0 *0 1* 0 01 0 01 0 +u 0 10 1 0 0* 10 0 0* 10 10 0 01 *0 -u 0 *0 01 0 10 0 1 10 1 0 0 0 1 10 -u +u 0 * 0 0 * 0 1 1 10 1 0 1 0 * 0 -u 1 1 0* 0 01 *0 0 1* 1* 01 0 01 10 0 -u 0 1 10 01 0 0 10 0* +u -u *1 01 0 *0 0 1 10 1 01 0 -u 0 10 0 *1 10 0 0 1 0 1 * 1 * of the -IMC. 0 CSC-stage 0 0 1 and current 0 1 TABLE. II: Switching states space vectors for the +u it,B -u 1 it,A 0 0 0 1 S5n 0S7p S6p * S6n II S7n TABLE 1 0 0 1 1 00 0 1 0 0 00 0 S WITCHING STATES AND CURRENT SPACE VECTORS FOR THE CSCSTAGE OF THE -IMC. 1 0 0 1 0 0 0 states 0and current space 0TABLE. II: Switching 1 0 vectors for 1the CSC-stage0of the -IMC.0 -i S06p S07p S05n S16n S07n i+i it,B t,A 0 0 10 0 01 0 00 +i 0 0 10 01 0 0 1 +i 10 01 0 10 0-i 0 10 +i 01 01 10 0 +i -i0 0 -i 01 0 01 10 +i 0-i 0 0 1 0 0 0 1 0 +i 1 0 1 0 0 -i +i 0 1 1 0 0 -i 0 0 1 0 1 0 0 -i

active switches of the VSC stage can be operated with zerovoltage-switching by performing the switch commutations only when the CSC stage is in a free-wheeling state (u = 0). (cf. Fig. 7(b)). For the SVM featuring ZCS or ZVS depicted in Fig. 7, the -IMC transfer ratio can be determined as a ˆ1/2 function of the input and output ac voltage amplitudes U and the phase displacement between the fundamental output current and voltage, 2 ,

vt,ca

i 0 0 0 i0 +i 0a +i 0a +i 0a -i 0c -iac +i -iac +i +iab +i +i -icb +i -icb -i-ica -iba +i -iba +i +i +ibc +iac -i +iac -i -i-iab -ibc +i -ibc +i +ic -ib u-ib 0-ib 0 0 uuAB 0 uAC u0BC u0BA uuAB CA uuAC CB uBC uBA uCA uCB

0 vt,ca

-u 0 -u -u 0 -u +u 0 +u +u 0 +u it,C 0 0 0 0 0 it,C 0-i 0-i 00 0 +i -i +i -i 0 +i +i

where Iˆ1/2 are the input and output current amplitudes, and 1 is the phase displacement between the fundamental input current and voltage. The relative turn-on times of the ZCS or ZVS commutation schemes depicted in Fig. 7 for sinusoidal SVM can be directly calculated by the combination and multiplication of the relative turn-on times of the CSC and VSC stages. For 30o < 2 < 30o , the relative turn on times can be determined by :

⇣ ⇣ ⇡⌘ ⇡⌘ d(I~ )(V~ ) = M12 cos 'i2 cos 'u1 + (4) 2 1 3 6 ⇣ M12 = p = 0 ... 1 (1) ⇡⌘ ˆ 3U2 cos ( 2 ) d(I~ )(V~ ) = M12 cos 'i2 sin ('u1 ) (5) 2 2 3 ⇣ ⇡⌘ Therefore, ideally the input voltage range of the -IMC for d(I~ )(V~ ) = M12 cos 'i2 + sin ('u1 ) (6) 1 2 3 ⇣ ⇣ sinusoidal modulation, considering M12 = 1 and 2 = 0, is ⇡⌘ ⇡⌘ I5 and'Iu1 positive dcFig. 6. Space vector diagrams for the a) input and b) output stage of the -IMC. Note that in the depicted ini2b),+i.e. I4,cos 6, a+ d(I~dotted = M12 cos ' (7) ~ region 1 )(V1 ) givenlinkbyvoltage u>0 can only be formed by inversion of the dc-link current, i. 3 6 p 3 ˆ semiconductors or RB- The remaining state time equal tothus both Therefore, employing turned on laterrelative than azero defining stateis switch, ˆ1 high U =for0 the ...current U2 and b) output stage of the (2) Fig. 6. Space vector diagrams a)2input -IMC. Note that in the dotted region depicted in b), i.e. I4, I5 and I6, a positive⌘ dc⇣for IGBTs in the delta section of the VSC can reduce conduction transitions the delta connected devices would occur under link voltage u>0 can only be formed by inversion of the dc-link current, i. d0 = 1 d(In + d(I~the + d(I~could + doperated 0 a (8) ~ )( ~ )case, I V losses. Unfortunately, these devices present relatively high zero voltage. this )(V~ )-IMC )(V~ ) be (I~ )(V~ ) with ˆ1 2U

However, in practice the high maximum modulation indexormust Therefore, employing current switching losses. In order to take semiconductors advantage of the RBlow be limited, i.e. M ⇡ 0.98, in order always ensure that 12 section of the VSCtocan IGBTs in the delta reduce conduction forward voltage drop of such devices and not to increase the one switching structure uses the states within the the pulse losses. Unfortunately, these devices present relatively highlosses withfree-wheeling respect to a conventional VSC, switching losses. In order toa soft-switching take advantage of the low period, TPcould , thus a safe IMC bepreserving operated with SVM featuringcommutation zero-voltageforward voltage drop of such devices and not to increase the of the other structure. This leads to a small reduction the switching (ZVS) for the VSC stage. Alternatively, aofSVM switching losses with respect to a conventional VSC, the maximum attainable input voltage. with a special multi-step commutation scheme could be usedIMC could be operated withtransformation a SVM featuring zero-voltagewhere the non-defining delta switches could is begiven always The input-to-output current byturned switching (ZVS) for the VSC stage. Alternatively, a SVM off prior to a vector p transition and every-time it could be with a special multi-step3 commutation scheme could be used ˆ ˆ I2 = delta M12switches I1 cos ( 1could ) (3) where the non-defining be always turned 2 off prior to a vector transition and every-time it could be

2

1

2

2

1

1

1

2

turned on later zero-current-switching than a defining state(ZCS) switch,forthus SVM featuring the both CSC o o For 30 > > 30 , the dc-link voltage could become transitions for the delta connected devices would occur under 2 stage. zeroConsidering voltage. this case, -IMC could operated a of negative (u [-30 ,30 ],byonly the switching states I1,a Idifferent 2 and Ispace 3 or 0). given Consequently, the VSC stage can form are , u and u correspondingly the line-to-line voltages u AB BC can vector hexagon for each one of theseACdc-link voltages, ˆ1 dc-link voltage (u > be used to generate 3ˆ 1the required¯ positive U u ¯ = U2 and i = Iˆ1 cos ( 1 ) cos (!2 t) (9) ˆform 0). Consequently, VSC stage can a different space 2 costhe (!2 t) U 2 vector hexagon for each one of these dc-link voltages,

2

,

TABLE III S WITCHING SEQUENCES OF THE -IMC FOR OPERATION WITH SVM FEATURING ZCS OR ZVS COMMUTATION FOR VARIOUS COMBINATION OF TABLE. III: Switching sequences of the -IMC for operation with SVM INPUT AND OUTPUT SECTORS . S EE In /Vn VECTORS IN TAB . I AND II. (10) THEfeaturing ZCS or ZVS commutation for various combination of the input and output sectors. See In/Vn vectors in Tab. I and II. -IMC Sectors

(11)

CSC

tervals are

d

b

c

Switching Sequence (0 … TP/2)

VSC

I

I

I

II

(13)

I

III

(14) , these time

I

IV

I

V

(15)

I

VI

I

VII

I

VIII

I

IX

I

X

I

XI

I

XII

II

I

(12)

(16)

(17) , output space twelve 30oand output he resulting he reference * 2 , sectors ig. 8 shows put, dc-link, modulation

d

SVM with ZCS

SVM with ZVS

…(I2)(V1)-(I2)(V2)-(I2)(V0)(I1)(V0)-(I1)(V2)-(I1)(V1)… …(I2)(V2)-(I2)(V1)-(I2)(V0)(I1)(V0)-(I1)(V1)-(I1)(V2)… …(I2)(V2)-(I2)(V3)-(I2)(V0)(I1)(V0)-(I1)(V3)-(I1)(V2)… …(I2)(V3)-(I2)(V2)-(I2)(V0)(I1)(V0)-(I1)(V2)-(I1)(V3)… …(I2)(V3)-(I2)(V4)-(I2)(V0)(I1)(V0)-(I1)(V4)-(I1)(V3)… …(I2)(V4)-(I2)(V3)-(I2)(V0)(I1)(V0)-(I1)(V3)-(I1)(V4)… …(I2)(V4)-(I2)(V5)-(I2)(V0)(I1)(V0)-(I1)(V5)-(I1)(V4)… …(I2)(V5)-(I2)(V4)-(I2)(V0)(I1)(V0)-(I1)(V4)-(I1)(V5)… …(I2)(V5)-(I2)(V6)-(I2)(V0)(I1)(V0)-(I1)(V6)-(I1)(V5)… …(I2)(V6)-(I2)(V5)-(I2)(V0)(I1)(V0)-(I1)(V5)-(I1)(V6)… …(I2)(V6)-(I2)(V1)-(I2)(V0)(I1)(V0)-(I1)(V1)-(I1)(V6)… …(I2)(V1)-(I2)(V6)-(I2)(V0)(I1)(V0)-(I1)(V6)-(I1)(V1)… …(I2)(V1)-(I2)(V2)-(I2)(V0)(I3)(V0)-(I3)(V2)-(I3)(V1)…

…(I2)(V1)-(I1)(V1)-(I0)(V1)(I0)(V2)-(I1)(V2)-(I2)(V2)… …(I2)(V2)-(I1)(V2)-(I0)(V2)(I0)(V1)-(I1)(V1)-(I2)(V1)… …(I2)(V2)-(I1)(V2)-(I0)(V2)(I0)(V3)-(I1)(V3)-(I2)(V3)… …(I2)(V3)-(I1)(V3)-(I0)(V3)(I0)(V2)-(I1)(V2)-(I2)(V2)… …(I2)(V3)-(I1)(V3)-(I0)(V3)(I0)(V4)-(I1)(V4)-(I2)(V4)… …(I2)(V4)-(I1)(V4)-(I0)(V4)(I0)(V3)-(I1)(V3)-(I2)(V3)… …(I2)(V4)-(I1)(V4)-(I0)(V4)(I0)(V5)-(I1)(V5)-(I2)(V5)… …(I2)(V5)-(I1)(V5)-(I0)(V5)(I0)(V4)-(I1)(V4)-(I2)(V4)… …(I2)(V5)-(I1)(V5)-(I0)(V5)(I0)(V6)-(I1)(V6)-(I2)(V6)… …(I2)(V6)-(I1)(V6)-(I0)(V6)(I0)(V5)-(I1)(V5)-(I2)(V5)… …(I2)(V6)-(I1)(V6)-(I0)(V6)(I0)(V1)-(I1)(V1)-(I2)(V1)… …(I2)(V1)-(I1)(V1)-(I0)(V1)(I0)(V6)-(I1)(V6)-(I2)(V6)… …(I2)(V1)-(I3)(V1)-(I0)(V1)(I0)(V2)-(I3)(V2)-(I2)(V2)…

aturing a) ZCS

as

P

2

P

d(I~ )(V~ ) , t0 = d0 1 1 2

In order to quantify the feasibility of the proposed threephase -IMC concept depicted in Fig. 4, operating with the SVM schemes enabling ZCS or ZVS of one of its converter stages as explained in Section II, a power loss analysis is presented in this section. The converter specifications considered are: P o = 10 kW, uA,rms = 220 V(50 Hz), and switching frequency fP = T1P = 18 kHz. Suitable commercial semiconductors are considered, where were IGBTs IKW40N120H3 is used in the CSCS, while RB-IGBT IXRH40N120 and IGBT IXA20IF1200HB in the VSCS. The computed semiconductor power losses for the two SVM schemes are presented in Fig. 9 for operation in the range of 10% to 100% of the rated power of a WECS that features a low inductance PMSG. Fig. 9 considers only the voltage stepup operation, where the power flows from the VSCS to the CSCS. The SVM featuring the ZCS commutation scheme is the solution facing the lowest semiconductor power losses. The results shows that at full power the -IMC operating under ZCS attains a pure semiconductor efficiency above 97%. IV. C ONCLUSIONS

stages [cf. Section II], a power loss comparison between this system and the IMC shown in Fig. 2(a), is presented in this section. The converter specifications considered are: Po=10 Finally, the time intervals shown in Fig. 7 can be computed uA,rms=220V(60Hz), and switching frequency fP = 1/TP= askW, follows posed three- 18kHz. A suitable commercial semiconductor is considered TP TP TP calculations ng with the in the ta = d(I~ )(V~ (IGBTs , tb = IKW40N120H3). d(I~ )(V~ ) , tc = d(I~ )(V~ ) (10) 2 1) 2 2 1 2 2 2 2 losses In Fig. 10 the pure semiconductor power of the ts converter T T td =

III. C OMPARATIVE E VALUATION

(11)

This work proposes a novel three-phase ac-ac indirect matrix converter well-suited for wind energy generation applications. The IMC system employs a bidirectional delta-switch voltage source converter as front-end and a bidirectional current source converter as back-end converter. In addition, two space vector modulation schemes for the studied ac-ac converter featuring zero current or zero voltage commutations were presented. Finally, the feasibility of the new delta-switch IMC was demonstrated by a power loss analysis for a 10 kW conversion system. The results showed that at full power the

For SVM featuring ZCS these time intervals are distributed t0 TP + t0 and tB = + tc + td 2 2 t1 = ta , t 2 = t1 + tb , t 3 = t2 + t0 , t 4 = t3 + tc , t5 = t4 + 2td , t6 = t5 + tc , t7 = t6 + t0 , t8 = t7 + tb ,

tA = ta + tb +

(12)

u 0

(13) (14)

As presented in Fig. 6, the resulting input and output space vector diagrams of the -IMC can be divided in twelve 30o wide intervals, which gives 144 different input and output sector combinations. For example, Tab. III lists the resulting switching sequences for some combinations of the reference input voltage, ~u⇤1 , and reference output current, ~i⇤2 , sectors for the SVM with ZCS and ZVS commutations. Fig. 8 shows simulation results indicating the characteristic input, dc-link, andb)output waveforms of the -IMC for these modulation and b) ZVS commutations. The -VSC stage is set to operate with half schemes.

-ic

-ic

-ic

ia i 0 uAC u

uAB

I2

0

I1 t1

V1

V2

uAC uAB uAB

time t8

TP

ia

-ic

V1

ia

-ic

1 V1 V2 V0 V0V2V1 2 TP 0 t1 t2 tA t3 t4 t5 t6 tB t7 (b)

time

I2

I1

ia

i

(15) (16) (17)

uAC

uAB

I2

ia

On the other hand, for SVM featuring ZVS these time intervals are distributed as t0 TP + t0 tA = ta + td + and tB = + tb + tc 2 2 t1 = ta , t 2 = t1 + td , t 3 = t2 + t0 , t 4 = t3 + tc , t5 = t4 + 2tb , t6 = t5 + tc , t7 = t6 + t0 , t8 = t7 + td ,

uAC

(a)

uAB

I0 I 0 I 1 I 2 1 T P 2 t2 tA t3 t4 t5 t6 tB t7

time

uAC time

t8

TP

Fig. 7. Formation of the dc-bus voltage u and current i for multi-step commutation schemes featuring: (a) ZCS of the CSC stage, and (b) ZVS of the VSC stage. Note that while the switches of one stage operates with switching period TP the switches of the other stage operate at twice the frequency ( T2P ).

Fig. 8. Characteristic waveforms of the -IMC for SVM featuring a) ZCS and b) ZVS commutations. The period of the output stage (!a = 2!A = 4⇡50 rad/s.)

Fig. 9. Semiconductor power loss comparison between the different topologies of 10 kW IMCs employing commercial semiconductors (operating parameters: unity power factor; output voltage rms value uA,rms = 220 V (50 Hz); and switching frequency fP = 18 kHz.

-IMC operating under ZCS attained a pure semiconductor efficiency above 97%. ACKNOWLEDGMENTS This work is partially funded under grant 004/2010– PRONEX by CNPq/FAPESC. The authors would like to thank Mr. Daniel Collier for computing the generator maximum power operating points. R EFERENCES [1] J. Kolar, F. Schafmeister, S. Round, and H. Ertl, “Novel three-phase AC AC sparse matrix converters,” IEEE Transactions on Power Electronics, vol. 22, no. 5, pp. 1649 –1661, sept. 2007. [2] P. Zanchetta, P. Wheeler, J. Clare, M. Bland, L. Empringham, and D. Katsis, “Control design of a three-phase matrix-converter-based AC AC mobile utility power supply,” IEEE Transactions on Industrial Electronics, vol. 55, no. 1, pp. 209 –217, jan. 2008. [3] R. Gupta, K. Mohapatra, A. Somani, and N. Mohan, “Direct-matrixconverter-based drive for a three-phase open-end-winding AC machine with advanced features,” IEEE Transactions on Industrial Electronics, vol. 57, no. 12, pp. 4032 –4042, dec. 2010.

-VSCS is set to operate with half fundamental

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