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topology operating in Discontinuous Capacitor Voltage Mode. (DCVM) is proposed. The bridgeless topology and the presence of only one or two semiconductor ...

Bridgeless High Power Factor Buck-Converter Operating in Discontinuous Capacitor Voltage Mode Abbas A. Fardoun

Nasrullah M. Khraim

Electrical Engineering Department University of United Arab Emirates P.O. Box 17555, Al-Ain, UAE [email protected]

EOMD/NMD/OP&S/OPL Al Ain Distribution Company P.O. Box 59184, Al-Ain, UAE [email protected]

Esam H. Ismail, Ahmad J. Sabzali, and Mustafa A. Al-Saffar Electrical Engineering Department College of Technological Studies P.O. Box 35007, Al-Shaab, Kuwait 36051 [email protected], [email protected], [email protected] Abstract—In this paper, a new bridgeless single phase ac-dc power factor correction (PFC) rectifiers based on Buck topology operating in Discontinuous Capacitor Voltage Mode (DCVM) is proposed. The bridgeless topology and the presence of only one or two semiconductor switches in the current flowing path during each interval of the switching cycle result in lower conduction losses compared to the conventional DCVM Buck PFC rectifier. The DCVM operation offers additional advantages such as: zero-voltage turn-off in the power switches, zero-voltage turn-on in the output diode, and continuous input current. Hence, the electromagnetic interference (EMI) noise emission is minimized. The converter achieves high power factor naturally with low total harmonic distortion (THD) in the input current. Theoretical analysis and experimental results for 100 W/48 Vdc at 100 Vrms line voltage are provided to evaluate the performance of the proposed scheme. The measured conversion efficiency reached 96.4%.



Power supplies with active power factor correction (PFC) techniques are becoming necessary for many types of electronic equipment to meet harmonic regulations and standards, such as the IEC 61000-3-2 [1]. In an effort to maximize the power supply efficiency, considerable research efforts have been directed towards designing bridgeless PFC circuits where the current flows through a minimum number of switching devices compared to the conventional PFC rectifier. Accordingly, the converter conduction losses can be significantly reduced and higher efficiency can be obtained as well as cost savings. Recently, several bridgeless PFC rectifiers have been introduced to improve the rectifier power density and/or reduce noise emissions via soft switching techniques or coupled magnetic topologies [2]-[7]. However, all of these rectifiers operate in discontinuous inductor current mode (DICM). However,

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DICM suffers from discontinuous input current and higher switch current stresses causing higher conduction losses. On the other hand, DCVM topologies have soft turn-off switch capability; hence IGBTs can be used as the switching device. Also, continuous input current can be obtained with converters operating in DCVM; hence, the electromagnetic interference (EMI) noise emissions can be reduced. Several DCVM topologies with PFC capability have been published in the literature [8]-[12]. However, all of these topologies utilize a full bridge rectifier as a front end which results in lower efficiency. In this paper, a new bridgeless buck converter operating in DCVM mode is presented. The proposed converter has the same advantages as the conventional buck-type converters operating in DCVM such as: inherent inrush current limitation during startup and overload conditions, lower input current ripple, and less EMI noise. However, the conduction losses are significantly reduced. II.


Fig. 1 and 2 show the two proposed bridgeless DCVM PFC Buck converters. Fig. 1 shows the first topology which utilizes two power switches (Q1 and Q2). The two switches can be driven by the same control signal, which significantly simplifies the control circuit. Note that Q1 and Q2 are single quadrant switches hence a diode is added in series with the switch. The second topology utilizes a single switch instead of two switches as shown in Fig. 2. Compared to the conventional full bridge DCVM buck topology, the structure of the proposed topology utilizes one additional inductor and one capacitor which are often described as a disadvantage in terms of size and cost. However, a better thermal performance can be achieved with the two inductors compared to a single inductor. In addition, the continuous


interval ends when voltage across the input capacitor VC1 decreases linearly to zero. Stage 2 [D1Ts ≤ t ≤ DTs]: in this stage, switch Q1 is still turned on and he input capacitor C1 stays discharged. The switch current iQ1 is equal to the input current iL1. The output stage diode Do starts conducting. The diode current during this stage is equal to iLo – iL1. This stage ends when Q1 is turned off. Fig. 1. Proposed bridgeless DCVM PFC topology with two active switches.

Stage 3 [DTs ≤ t ≤ Ts]: this stage starts when switch Q1 is turned off. The input capacitor current iC1 is charged by the input current iL1; hence, the input capacitor voltage VC1 increases linearly and reaches a maximum of VCM at the end of the switching cycle t = Ts. During this interval capacitor C1 is being charged with a constant current (iL1). Fig. 4 illustrates the theoretical steady-state DCVM waveforms over one switching cycle during the positive halfline cycle of the input voltage. A. Voltage Conversion Ratio From Fig. 4 at steady state, the capacitor voltage can be expressed as shown below over one switching cycle.

Fig. 2. The proposed single-switch bridgeless DCVM PFC topology.

 1 i 1 D T  i  i t , 0  t  D T   s  L1 Lo   1 s   C  L1  1   v C1  t   0, D1Ts  t  DTs  i   L1  t  DTs  , DTs  t  Ts   C1 

input current results in low conducted EMI compared to the conventional Buck PFC converter. Also, the return diodes Dp and Dn always provide low-impedance current path for the return current. III.


The converter of Fig. 1 is analyzed. The analysis assumes the proposed converter operates at a steady-state condition in addition to the following assumptions: pure sinusoidal input voltage, ideal lossless components, inductors L1 and L2 are large enough such that the current through them can be considered constant over one switching cycle Ts, and the low-frequency energy storage element Co is large enough such that the output voltage Vo can be considered constant during half-line cycle of the line frequency fL. The input capacitances C1 and C2 have low capacitance value to operate in DCVM. During the positive half-line cycle, L1-C1Q1-Lo-Do, are active through diode Dp, which connects the input ac source to the output ground. During the negative half-line cycle, L2-C2-Q2-Lo-Do, are active through diode Dn, which connects the input ac source to the output ground. Due to the symmetry of the circuit, it is sufficient to analyze the circuit during the positive half-cycle of the input voltage. The circuit operation in DCVM can be divided into three distinct operating stages during one switching period Ts as shown in Fig. 3.


Stage 1.

Stage 2.

The topological stages of the proposed converter over a switching period Ts can be briefly described as follows: Stage 1 [0 ≤ t ≤ D1Ts], in this stage switch Q1 is turned on and capacitor C1 is being discharged. The switch current iQ1 is equal to the output inductor Lo current iLo, while iC1 = iL1 – iLo at the condition iLo > iL1. During this stage the diode Do is reversed biased by the voltage across capacitor C1. This

Stage 3.


Fig. 3. Topological stages over one switching period Ts, during positive half-line cycle.

From (3) and (5) we get the following relation can be obtained Vo D1  VC1 Ts 1  D  D1


By applying capacitor charge balance over one switching cycle for capacitor C1, the following relation is obtained D1 (i L1  i Lo )  (1  D) i L1  0


The switching network has an effective input resistance (Re) that can be obtained by manipulating (2), (3), (6) and (7) and is given by Re 



i L1



i L1

D ' 2 Ts 2 C1

 vac Ts   vac  Vo Ts 

  (8)  

where D=1-D. The steady-state averaged DCVM model (low-frequency model) for the proposed converter is given in [8]. The time-varying rectified input current iL1(t) over the whole line cycle can be obtained from (4) and (8) as i L1  t  

The maximum voltage at the input capacitor C1 can be expressed as i L1 1  D  Ts C1


The average voltage across the input inductor L1 over one switching cycle Ts is zero at steady state condition. Hence, the average voltage across the input capacitor C1 is equal to the input voltage. vac (t)


 VC1


where the input voltage vac(t) is considered to be an ideal sine wave, i.e. (4)

where Vm is the peak amplitude and ω is the line angular frequency. Similarly, by applying volt-second across Lo over switching cycle, the average output voltage Vo can be obtained as Vo 

The voltage conversion ratio M in DCVM operation mode can be obtained using the power balance between the input and output ports and it is given by

1  D 2 

 K  1 sin 1 (M) M  1  M2   2 2   M 

1 D1 VCM 2


  (10)  

where  is the conversion efficiency and the dimensionless parameter K is defined as

1 1 D1 VCM  (1  D)VCM (3) 2 2

vac  t   Vm sin  t


where M is the voltage conversion ratio of the output voltage to the peak input voltage. It shall be noted that the above equation is only valid for vac(t) > Vo. For Vo > vac(t), the input current is zero for the buck converter.

Fig. 4. Characteristic DCVM waveforms over one Ts. for the converter of Fig. 1.


vac (t) 2 C1 Vm   sin  t  M  Re TS D '2


2 R L C1 Ts


B. Boundary Condition Since the input voltage is AC, the normalized discharge time D1 varies a function of time. One can solve for the discharge time as function of the varying ac voltage using (6) and can be expressed as,

  M d1  t   D '    sin   t   M   


The boundary condition between CCVM and DCVM occurs when the duty cycle D and the normalized discharge time d1(t) are equal. However, d1(t) varies as function time.


At t= /2, the boundary condition between DCVM and CCVM occurs at d1(t) = D and similar to a buck converter. Fig. 5 presents the conversion ratio M as function of Duty cycle D assuming lossless converter for different values of K. the dashed line separates both modes for t = /2. The smaller conduction parameter K results in wider range of DCVM over the AC line cycle. In other words, the smaller the value of K, the deeper operation in DCVM. However, the disadvantage of operating deeply in DCVM is the high voltage stress at the active switches and the output diode. Hence, K must be carefully selected to insure DCVM operation with acceptable voltage stress values. It shall be noted that DCVM is lost for Vo > vac(t), as the input current decays to zero in that region. Using (2), (5) and (7), the normalized discharging time D1 for the input capacitor C1 can be found as D1 

4D '2  K  1 1 2 D' K 

   

Fig. 5. Conversion ratio (M) versus duty cycle (D) at 100% Efficiency.


(13) Conventional Full Bridge DCVM Buck PFC

The critical value of K (Kcrit) required for C1 and C2 to be in DCVM is found from d1 < D, and can be found using (10) which gives

K crit

D2 D '  

Proposed Bridgeless DCVM Buck, Fig. 1


C. Comparison Between the Proposed and Full Bridge DCVM Buck Converter The performance of the proposed converter of Fig. 1 is verified by an analytical comparison with a full bridge conventional DCVM buck converter [11] as shown in Table I at an input voltage of 100 Vrms and output voltage Vo of 48 V. The analysis assumes the same operating point (input voltage, output voltage, load and parameter K). Table I compares the proposed bridgeless DCVM buck converter with a full bridge DCVM buck converter at different output power levels 100 W, 200 W and 300 W. The efficiency , THD, and power factor values are improved in the proposed bridgeless topology. PSPICE simulation with real component models was used to perform the simulation. Table II compares the proposed bridgeless DCVM buck converter with a full bridge DCVM buck converter with respect to component count and number of semiconductors in the current path. Fig. 6 shows the simulated harmonic content of the input current at 100 Vrms input voltage for the proposed DCVM topology of Fig. 1 and of the conventional full bridge DCVM buck PFC compared with the limits of EN61000-3-2 Class D standard. It is evident from Fig. 6 that the calculated results for the proposed converter of Fig. 1 are well below the allowable limits of Class D standard and lower than the conventional DCVM buck converter.

Po [W]

 [%]

THD [%]



























Proposed Bridgeless DCVM Buck, Fig. 1


4 slow and 1 fast

3 fast










2 slow diodes and 1 switch

1 fast diode and 1 switch

2 slow diodes, 1 fast diode and 1 switch

2 fast diodes and 1 switch

2 slow diodes, 1 fast diode and 1 switch

1 fast diode

Current conduction path (Stage 1) Current conduction path during DCVM (Stage 2) Current conduction path (Stage 3)


L e 

1  D Ts    C1  2  



E. Components’ Stresses The voltage and current stresses of the converter components are shown in Table III. The peak voltage stresses are normalized to the output voltage Vo, while the rms current stresses are normalized to the load current Io.


Fig. 6. Input line current harmonic content for the proposed topology of Fig. 1 and the conventional DCVM Buck PFC converter compared to EN61000-3-2 class D limits.

D. Components’ Selection Input capacitors C1 and C2 can be calculated from (15) provided that the value of K is less the Kcrit. C1  C2 

K Ts 2 RL


The input inductors L1 and L2 are selected to satisfy constant current source requirement over the whole switching cycle. In addition, L1 and L2 must be small enough to minimize the phase shift between the line voltage and input current. Lower limit: The inductances of L1 and L2 must be large enough to maintain continuous input current and to avoid resonance with the input capacitors C1 and C2 during switchoff time. L1 min  L 2  min 

1  D ' Ts    C1  2  



The proposed topology, shown in Fig. 1, is verified in the laboratory at an operating point of input voltage vac = 100 Vrms @ 50 Hz, Vout = 48 V, Pout = 100 W, and fs = 50 kHz. According to (10), the calculated duty cycle is set to 48.3%. The values of the circuit components are shown in Table IV. The experimental waveforms of the input voltage, input current and output voltage are shown in Fig. 7. The dead zone region of the line current near the zero crossing is the region where Vo > vac(t). The waveforms of the input capacitors’ voltages over the line cycle are shown in Fig. 8. It can be observed that they are shifted by 180 degrees, and C1 is operating during the positive half-line cycle, while C2 is operating during the negative half-line cycle. The measured peak capacitor peak voltage is close 385 V and it matches the stresses of Table III. The waveforms of the voltage across the active switch, and the input capacitor voltage and current over several switching cycle are shown in Fig. 9. It can be observed that the switch voltage is turned off at zero voltage and similarly the diode is turned on at also zero voltage. The capacitor voltage trace of Fig. 9 verifies the converter operation in DCVM. The measured efficiency of the converter reached 96.4% at 100W. It must be noted that the measured efficiency is higher than the simulated one. This could be due to the fact that the loss model of the simulated components is higher than the real components used in the experimental set-up.

Upper limit: The inductances of L1 and L2 must not be very large in order to minimize the phase shift between the input voltage and the input current. Therefore, the reactance of L1 must be less than the converter effective input resistance Re.

L1 max  L2 max 

Re D ' 2 Ts  L 4  C1 f L



The output inductance is also required to be large enough to maintain constant output current during one switching cycle. Assuming constant output voltage (very large output capacitance), then during the switch on-time (first stage in Fig. 3) the converter may operate in a resonant mode due to the presence of resonance circuit between the input capacitor C1 and the equivalent inductors Le (L1 // Lo). To maintain constant current through Lo over the switching period, the resonant frequency of the input capacitor C1 and Le must be much smaller than the switching frequency. In other words, the value of Lo can selected to ensure the following relation



Normalized Peak Voltage (Vin/Vo)

Q1, Q2

2  1 M    D'  M 


2  1 M    D'  M 

C1, C2

2  1 M    D'  M 

2K 1 4  M  M2 MD ' 2 




L1, L2




Normalized Effective Current (Irms/Io) K 2 M D '2



M  4 M2

K M 2 D'4 2MD '2 M 2 D '2 1 4     M  M2 K K 2  MD '2 K2

K 2MD'2


16 M  4M2 





L1 and L2

2.2 mH

Toroidal Inductors (Wilco)


180 H

Toroidal Inductors (Wilco)

C1 and C2

47 nF

Polypropylene Capacitors. (Low ESR)


3000 F

Aluminum Electrolytic Capacitor



STTH5L06 diode [600V, 5A, Vf=1.05V ]

Dp and Dn


SBR10U300CT Diode [300 V, 10 A, Vf = 0.64 V]

Q1 and Q2


IPW60R045CP MOSFETs [650 V, 60 A, 45 m]



A single-phase bridgeless step-down buck PFC converter topology operating in DCVM has been introduced. The proposed converter can achieve natural power factor correction with low line current harmonic distortion while ensuring zero-voltage switching for the active switches and the dc side diode. Expressions for peak component stresses are given, which allow the optimization of the power stage design. The experimental results verify the advantage of DCVM topology of soft switch turn off and continuous input current. The efficiency, power factor and THD of the converter have been improved versus the full bridge DCVM topology. The proposed topology complies with the international standards, i.e. EN 61000-3-2. The new topology has been verified via experimental laboratory prototype. The measured conversion efficiency is 96.4%. ACKNOWLEDGMENT This work was supported in part by the United Arab Emirates University under Contract # Inter-EE-2012.


Fig. 7. Experimental results for the input current, input voltage and output voltage for a 100W load.

Fig. 8. Experimental results for the input capacitors’ voltage.

Fig. 9. Experimental results for the capacitor voltage and switch voltage over switching cycle.

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