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Bridgeless High-Power-Factor Buck-Converter Operating in Discontinuous Capacitor Voltage Mode Abbas A. Fardoun, Senior Member, IEEE, Esam H. Ismail, Senior Member, IEEE, Nasrullah M. Khraim, Ahmad J. Sabzali, Member, IEEE, and Mustafa A. Al-Saffar, Member, IEEE

Abstract—In this paper, a new bridgeless single-phase ac–dc power factor correction (PFC) rectifier based on buck topology operating in discontinuous capacitor voltage mode (DCVM) is proposed. The bridgeless topology and the presence of only one or two semiconductor switches in the current flowing path during each interval of the switching cycle result in lower conduction losses compared with the conventional DCVM buck PFC rectifier. The DCVM operation offers additional advantages such as zero-voltage turn-off in the power switches, zero-voltage turn-on in the output diode, and continuous input current. Hence, the electromagnetic interference noise emission is minimized. The converter achieves high power factor naturally with low total harmonic distortion in the input current. Theoretical analysis and experimental results for 100 W/48 Vdc at 100 Vrms line voltage are provided to evaluate the performance of the proposed scheme. The measured conversion efficiency reached 96.3%. Index Terms—Discontinuous capacitor voltage mode (DCVM), electromagnetic interference (EMI), power factor correction (PFC), total harmonic distortion (THD).

I. I NTRODUCTION

P

OWER supplies with active power factor correction (PFC) techniques are becoming necessary for many types of electronic equipment to meet harmonic regulations and standards, such as the IEC 61000-3-2 [1]. Discontinuous inductor current mode (DICM) and discontinuous capacitor voltage mode (DCVM) are typically suitable for low-power applications (< 300 W); however, both topologies have, in general, inherent PFC properties unlike continuous current mode (CCM) topologies. Active PFC techniques based on basic dc–dc converter topologies have been developed for high power factor (PF) and low input current harmonic ac/dc Manuscript received September 7, 2013; revised December 10, 2013; accepted January 28, 2014. Date of publication February 11, 2014; date of current version September 16, 2014. Paper 2013-IPCC-675.R1, presented at the 2013 IEEE Energy Conversion Congress and Exposition, Denver, CO, USA, September 16–20, and approved for publication in the IEEE T RANSACTIONS ON I NDUSTRY A PPLICATIONS by the Industrial Power Converter Committee of the IEEE Industry Applications Society. This work was supported in part by the Research Affairs at the United Arab Emirates University. A. A. Fardoun is with the Department of Electrical Engineering, University of United Arab Emirates, Al-Ain, UAE (e-mail: [email protected]). E. H. Ismail, A. J. Sabzali, and M. A. Al-Saffar are with the College of Technological Studies, Al-Shaab 36051, Kuwait (e-mail: [email protected]; [email protected]; [email protected]). N. M. Khraim is with the EOMD/NMD/OP&S/OPL, Al Ain Distribution Company, Al-Ain, UAE (e-mail: [email protected]). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TIA.2014.2305771

rectification [2], [3]. However, conventional PFC rectifiers allow the current to flow through two bridge diodes in addition to the switching component of the converter. This results in higher conduction losses increasing the thermal stresses of the converter. In an effort to maximize the power supply efficiency, considerable research efforts have been directed toward designing bridgeless PFC circuits where the current flows through a minimum number of switching devices compared with the conventional PFC rectifier. Accordingly, the converter conduction losses can be significantly reduced, and higher efficiency can be obtained and cost savings. Recently, several bridgeless PFC rectifiers have been introduced to improve the rectifier power density and/or reduce noise emissions via soft switching techniques or coupled magnetic topologies [4]–[10]. However, all of these rectifiers operate in DICM and suffers from high switch current stress causing higher conduction losses. In addition, a more robust input filter must be employed to suppress the high-frequency components of the pulsating input current, which increases the overall weight and cost of the rectifier. Interleaving two bridgeless boost converters can significantly minimize the input current ripple and doubles the transferable power [11]. However, besides the complex control, interleaving PFC boost converters have low efficiency at low power levels due to high component count. Thus, for universal input line and for low-power applications (< 300 W), all of the reported topologies in [4]–[11] suffer from having low efficiency at low input line (vac = 90 Vrms ) due to the high input current, which produces higher conduction losses in the circuit components. Operating the converter at the boundary of DICM/CCM with variable switching frequency [12] can improve the efficiency at low line at the expense of complex control. On the other hand, the buck PFC is an attractive solution for universal input voltages at power levels (< 300 W). The buck PFC can achieve high efficiency over the entire universal input line voltage range with distorted input current that comfortably passes the limits imposed by IEC 61000-3-2 requirements [1]. In addition, the ability of the buck PFC converter to generate output voltages less than the line peak voltage has beneficial effect on the performance of the downstream dc/dc output stage because it allows a more efficient design for the dc/dc stage by using lower voltage-rated semiconductor devices. In [13], a bridgeless buck PFC rectifier operating in CCM with clampedcurrent-mode control is proposed. High efficiency is achieved over the entire load, and input voltage ranges at the cost of complicating the control circuitry.

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Fig. 1. Proposed bridgeless DCVM PFC topology with two active switches.

Fig. 2.

The drawbacks of complex control associated with CCM operation and high current stress associated with DICM operation can be overcome by operating the converter in DCVM mode. This operation mode offers soft turn-off switch capability; the soft turn-off capability allows using insulated-gate bipolar transistor (IGBT) as the switching device that typically has higher turn-off losses due to the tail current of IGBT. In addition, continuous input current can be obtained with converters operating in DCVM; hence, the input filter size is minimized, and the electromagnetic interference (EMI) noise emissions are reduced. Several DCVM topologies with inherent PFC capability have been published in the literature [14]–[18]. However, all of these topologies utilize a full bridge rectifier as a front end that results in lower efficiency. In this paper, a new bridgeless buck converter operating in DCVM mode is presented. Unlike the PFC boost converter, the proposed converter has the same advantages as the conventional full-bridge PFC buck DCVM converter such as inherent inrush current limitation during startup and overload conditions, lower input current ripple, lower diode reverse recovery losses, and less EMI noise. Compared with the conventional full-bridge PFC buck DCVM converter, the proposed converter has lower number of simultaneously conducting semiconductor components; hence, the conduction losses and the thermal stresses on the semiconductor devices are further reduced, and the circuit efficiency is improved. It should be mentioned here that the main drawback of the DCVM operation is the switch voltage stresses, which increase with the load current. Thus, the proposed converter is intended for low-power applications. For high-power applications, then fixed duty-cycle variable frequency control should be used to compensate for load variations in order to avoid an additional increase in the switch voltage stress.

cost. However, a better thermal performance can be achieved with the two inductors compared with a single inductor. In addition, unlike DICM PFC converters, the continuous input current results in low conducted EMI noise, which reduces input filtering requirements dramatically. The return diodes Dp and Dn always provide low-impedance current path for the return current.

II. P ROPOSED B RIDGELESS C ONVERTERS Figs. 1 and 2 show the two proposed bridgeless DCVM PFC buck converters. Fig. 1 shows the first topology, which utilizes two power switches (Q1 and Q2 ). The two switches can be driven by the same control signal, which significantly simplifies the control circuit. Note that Q1 and Q2 are single quadrant switches; hence, a diode is added in series with the switch. The second topology utilizes a single switch instead of two switches, as shown in Fig. 2. Compared with the conventional full-bridge DCVM buck topology, the structure of the proposed topology utilizes one additional inductor and one capacitor that are often described as a disadvantage in terms of size and

Proposed single-switch bridgeless DCVM PFC topology.

III. P RINCIPLE OF O PERATION AND A NALYSIS The converter of Fig. 1 is analyzed. The analysis assumes the proposed converter operates at a steady-state condition in addition to the following assumptions. 1) The input signal is a pure sinusoidal voltage. 2) Inductors L1 and L2 are large enough such that the current through them can be considered constant over one switching cycle Ts . 3) The low-frequency energy storage element Co is large enough such that the output voltage Vo can be considered constant during the half-line cycle of the line frequency fL . 4) The input capacitances C1 and C2 have low capacitance values to operate in DCVM. During the positive half-line cycle, L1 -C1 -Q1 -Lo -Do are active through diode Dp , which connects the input ac source to the output ground. During the negative half-line cycle, L2 -C2 -Q2 -Lo -Do are active through diode Dn , which connects the input ac source to the output ground. Due to the symmetry of the circuit, it is sufficient to analyze the circuit during the positive half-cycle of the input voltage. The circuit operation in DCVM can be divided into three distinct operating stages during one switching period Ts , as shown in Fig. 3. The topological stages of the proposed converter over a switching period Ts can be briefly described as follows. Stage 1 [0 ≤ t ≤ D1 Ts ]: in this stage, switch Q1 is turned on, and capacitor C1 is being discharged. The switch current iQ1 is equal to the output inductor Lo current iLo , whereas iC1 = iL1 − iLo at the condition iLo > iL1 . During this stage, the diode Do is reversed biased by the voltage across capacitor C1 . This interval ends when the voltage across the input capacitor VC1 linearly decreases to zero. Stage 2 [D1 Ts ≤ t ≤ DTs ]: in this stage, switch Q1 is still turned on and the input capacitor C1 stays discharged. The switch current iQ1 is equal to the input current iL1 . The output stage diode Do starts conducting. The diode current

FARDOUN et al.: BRIDGELESS HIGH-POWER-FACTOR BUCK-CONVERTER OPERATING IN DCVM

Fig. 3. Topological stages over one switching period Ts during positive halfline cycle.

during this stage is equal to iLo − iL1 . This stage ends when Q1 is turned off. Stage 3 [DTs ≤ t ≤ Ts ]: this stage starts when switch Q1 is turned off. The input capacitor current iC1 is charged by the input current iL1 ; hence, the input capacitor voltage VC1 linearly increases and reaches a maximum of VCM at the end of the switching cycle t = Ts . During this interval capacitor, C1 is being charged with a constant current (iL1 ). A. Voltage Conversion Ratio From Fig. 4 at steady state, the capacitor voltage can be expressed, as shown below over one switching cycle. Thus, vC1(t)

⎧1 ⎨C1 [iL1 (1−D)Ts +(iL1 −iLo )t] , = 0, ⎩ iL1 C1 (t−DTs ),

⎫ 0 ≤ t ≤ D1 T s ⎬ D1 Ts ≤ t ≤ DTs . DTs ≤ t ≤ Ts ⎭ (1)

The maximum voltage at the input capacitor C1 can be expressed as VCM =

iL1 (1 − D)Ts . C1

(2)

The average voltage across the input inductor L1 over one switching cycle Ts is zero at steady-state condition. Hence, the average voltage across the input capacitor C1 is equal to the input voltage. Thus, vac (t)T s = VC1 T s =

1 1 D1 VCM + (1 − D)VCM . 2 2

(3)

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Fig. 4. DCVM waveforms over one Ts for the converter of Fig. 1.

Fig. 4 illustrates the theoretical steady-state DCVM waveforms over one switching cycle during the positive half-line cycle of the input voltage.The input voltage vac (t) is considered to be an ideal sine wave, i.e., vac (t) = Vm sin ωt

(4)

where Vm is the peak amplitude, and ω is the line angular frequency. Similarly, by applying volt-second across Lo over the switching cycle, the average output voltage Vo can be obtained as Vo =

1 D1 VCM . 2

(5)

From (3) and (5), the following relation can be obtained: Vo D1 = . VC1 T s 1 − D + D1

(6)

By applying capacitor charge balance over one switching cycle for capacitor C1 , the following relation is obtained: D1 (iL1 − iLo ) + (1 − D)iL1 = 0.

(7)

The switching network has an effective input resistance (Re ) that can be obtained by manipulating (2), (3), (6), and (7) and is given by 2 vac T s VC1 T s vac T s D Ts Re = = = (8) iL1 iL1 2C1 vac T s − Vo where D = 1 − D. The steady-state averaged DCVM model (low-frequency model) for the proposed converter can be expressed, as shown in Fig. 5. Referring to Fig. 3, the average voltage over one switching cycle of vC1 (t) and v2 (t) are

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Fig. 5. Large-signal averaged DCVM model of the proposed converter.

presented as VC1 and V2 in Fig. 5, respectively, and they can be expressed as IL1 Ts D (D1 + D ) 2C1

vC1 (t) = VC1 = v2 (t) = V2 =

IL1 Ts D D1 . 2C1

(9) Fig. 6.

(10)

The time-varying rectified input current iL1 (t) over the whole line cycle can be obtained from (4) and (8) as iL1 (t) =

vac (t) 2C1 Vm = (| sin ωt| − M ) Re Ts D2

(11)

where M is the voltage conversion ratio of the output voltage to the peak input voltage. It shall be noted that the above equation is only valid for vac (t) > Vo . For Vo > vac (t), the input current is zero for the buck converter. In other words, the input current is only valid over the range ωt ∈ (α, π − α)

Eout

M 2 (sin(ωt) − M )2 = Kcrit . ηY sin2 (ωt)

(21)

Note that the maximum value of Kcrit occurs at ωt = π/2 and can be expressed as Kcrit- max =

M 2 (1 − M )2 . ηY

(22)

(15)

where η is the conversion efficiency, and the dimensionless parameter K is defined as 2RL C1 . Ts

K

vac (t), as shown Fig 19. The waveforms of the input capacitors’ voltages over the line cycle are shown in Fig. 20. It can be observed that they are shifted by 180◦ , and C1 is operating during the positive half-line cycle, whereas C2

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Fig. 21. Experimental results for the capacitor voltage and switch voltage over switching cycle.

Fig. 23. Experimental results for the input current, input voltage, and output voltage for the full-bridge DCVM buck converter. (vac = 100 Vrms , Vo = 48 V, Po = 100 W).

V. C ONCLUSION

Fig. 22. Calculated harmonic content of the input line current for the converter of Fig. 1. (vac = 100 Vrms , Vo = 48 V, Po = 100 W).

is operating during the negative half-line cycle. The measured peak capacitor voltage is close 385 V, and it matches the stresses of Table IV. The measured waveforms of the voltage across the active switch and the input capacitor voltage over several switching cycles are shown in Fig. 21. It can be observed that the switch voltage is turned off at zero voltage, and similarly, the output diode Do is turned on at zero voltage. The capacitor voltage trace of Figs. 20 and 21 verifies the converter operation in DCVM. The measured efficiency of the converter reached 96.3% at 100 W. It must be noted that the measured efficiency is lower than the simulated one. This could be due to the fact that the loss model of the simulated components is lower than the real components used in the experimental setup. Fig. 22 shows the simulated and measured harmonic content of the input line current at 100 Vrms together with the limits of EN61000-3-2 Class D standard. It is evident from Fig. 22 that the proposed converter is capable of producing a low harmonic distortion in line current that is well below the limits specified in EN61000-3-2 Class D requirements. Finally, a prototype of the conventional full-bridge DCVM buck PFC converter is constructed and tested under the same operating conditions. The circuit parameters used for this prototype are the same as those used for the proposed converter of Fig. 1. The bridge rectifier consists of four slow-recovery diodes similar to the type of diodes Dp and Dn used in Fig. 1. Experimental waveforms and measured efficiency for the conventional full-bridge DCVM buck PFC are depicted in Fig. 23. As a result, the efficiency improvement for the proposed scheme is about 0.6%, compared with the conventional full-bridge DCVM buck converter.

A single-phase bridgeless step-down buck PFC converter topology operating in DCVM has been introduced. The proposed converter can achieve natural PFC with low line current harmonic distortion while ensuring zero-voltage switching for the active switches and the dc side diode. Expressions for peak component stresses and K as a function of gain M and its effect on the converter discontinuous mode are given and allow the optimization of the power stage design. The experimental results verify the advantage of DCVM topology of soft switch turn-off and continuous input current. The efficiency, power factor and THD of the converter have been improved versus the full-bridge DCVM topology. Closed form equations to identify DCVM converter operation over the line period have been developed and verified. The proposed topology complies with the international standards, i.e., EN 61000-3-2. The new topology has been verified via experimental laboratory prototype. The measured efficiency peaks at 96.3%. R EFERENCES [1] Limits-Limits for Harmonic Current Emissions (Equipment Input Current ≤ 16 A per Phase), IEC 61000-3-2, 2010, EMC Part 3-2. [2] F. Musavi, M. Edington, W. Eberle, and W. Dunford, “Control loop design for a PFC boost converter with ripple steering,” IEEE Trans. Ind. Appl., vol. 49, no. 1, pp. 118–126, Jan./Feb. 2013. [3] Y. Ohnuma and J. Itoh, “A novel single-phase buck PFC AC-DC converter with power decoupling capability using an active buffer,” IEEE Trans. Ind. Appl., vol. 50, no. 3, pp. 1905–1914, May/Jun. 2014. [4] H.-Y. Tsai, T.-H. Hsia, and D. Chen, “A family of zero-voltage-transition bridgeless power-factor-correction circuits with a zero-current-switching auxiliary switch,” IEEE Trans. Ind. Electron., vol. 58, no. 5, pp. 1848– 1855, May 2011. [5] B. Su, J. Zhang, and Z. Lu, “Totem-pole boost bridgeless PFC rectifier with simple zero-current detection and full-range ZVS operating at the boundary of DCM/CCM,” IEEE Trans. Power Electron., vol. 26, no. 2, pp. 427–435, Feb. 2011. [6] M. Mahdavi and H. Farzanehfard, “Zero-current-transition bridgeless PFC without extra voltage and current stress,” IEEE Trans. Ind. Electron., vol. 56, no. 7, pp. 2540–2547, Jul. 2009. [7] A. J. Sabzali, E. H. Ismail, M. A. Al-Saffar, and A. A. Fardoun, “A new bridgeless PFC Sepic and Cuk rectifiers with low conduction and switching losses,” IEEE Trans. Ind. Appl., vol. 47, no. 2, pp. 873–881, Mar./Apr. 2011. [8] H. L. Cheng, Y. C. Hsieh, and C. S. Lin, “A novel single-stage high-powerfactor AC/DC converter featuring high circuit efficiency,” IEEE Trans. Ind. Electron., vol. 58, no. 2, pp. 524–532, Feb. 2011. [9] M. Mahdavi and H. Farzanehfard, “Bridgeless SEPIC PFC rectifier with reduced components and conduction losses,” IEEE Trans. Ind. Electron., vol. 58, no. 9, pp. 4153–4160, Sep. 2011. [10] A. A. Fardoun, E. H. Ismail, A. J. Sabzali, and M. A. Al-Saffar, “A comparison between three proposed bridgeless Cuk topologies and

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conventional topologies for power factor correction,” in Proc. IEEE ICSET, Dec. 2010, pp. 1–6. B. Su and Z. Lu, “An interleaved Totem-Pole boost bridgeless rectifier with reduced reverse-recovery problems for power factor correction,” IEEE Trans. Power Electron., vol. 25, no. 6, pp. 1406–1415, Jun. 2010. L. Huber, Y. Jang, and M. Jovanovic, “Performance evaluation of bridgeless PFC boost rectifiers,” IEEE Trans. Power Electron., vol. 23, no. 3, pp. 1381–1390, May 2008. Y. Jang and M. M. Jovanovi, “Bridgeless high power factor buck converter,” IEEE Trans. Power Electron., vol. 26, no. 2, pp. 602–611, Feb. 2011. N. M. Khraim, A. A. Fardoun, and E. Ismail, “Large and small signal analysis for bridgeless high PFC converter operating in DCVM,” presented at the International Conference on Renewable Energies and Power Quality (ICREPQ’13), Bilbao, Spain, Mar. 2013. C. K. Tse and M. H. L. Chow, “New single-stage power-factor-corrected regulators operating in discontinuous capacitor voltage mode,” in IEEE PESC, 1997, pp. 371–377. Y. S. Lee and S. Y. R. Hui, “Modeling, analysis, and application of buck converters in discontinuous-input-voltage mode operation,” IEEE Trans. Power Electron., vol. 12, no. 2, pp. 350–360, Mar. 1997. V. Grigore and J. Kyyrä, “High power factor rectifier based on buck converter operating in discontinuous capacitor voltage mode,” IEEE Trans. Power Electron., vol. 15, no. 6, pp. 1241–1249, Nov. 2000. H. Y. Kanaan and K. Al-Haddad, “A modified Sheppard-Taylor power factor corrector operating in discontinuous capacitor voltage mode,” in Proc. IEEE ISIE , Jun. 2011, pp. 81–88. W. J. Sarjeant, F. W. MacDougall, and D. W. Larson, “Energy storage in polymer laminate structures-ageing and diagnostic approaches for life validation,” IEEE Elect. Insul. Mag., vol. 13, no. 1, pp. 20–24, Feb. 1997. Z. Li et al., “Lifetime evaluation of high energy density capacitor based experimental investigations,” in Proc. IEEE 19th PPC, 2013, pp. 1–4. IC-Illinois Capacitors, Inc., Jul. 10, 2014. [Online]. Available: http:// www.illinoiscapacitor.com/tech-center/lifecalculators.aspx Energy Star, ENERGY STAR Program Requirements for External Power Supplies (Version 2.0). Jul. 10, 2014. [Online]. Available: http://www.energystar.gov/ia/partners/product_specs/program_reqs/eps_ prog_req.pdf R. W. Erickson and D. Maksimovic, Fundamentals of Power Electronics, 2nd ed. Norwell, MA, USA: Kluwer, 2001. B. A. Mather and D. Maksimovic, “A simple digital power-factor correction rectifier controller,” IEEE Trans. Power Electron, vol. 26, no. 1, pp. 9–19, Jan. 2011. D. G. Lamar, J. Sebastian, M. Arias, and A. Fernandez, “On the limit of the output capacitor reduction in power-factor correctors by distorting the line input current,” IEEE Trans. Power Electron., vol. 27, no. 3, pp. 1168– 1176, Mar. 2012. J.-C. Tsai et al., “Triple loop modulation (TLM) for high reliability and efficiency in a power factor correction (PFC) system,” IEEE Trans. Power Electron, vol. 28, no. 7, pp. 3447–3458, Jul. 2013.

Abbas A. Fardoun (M’90–SM’05) received the B.S. degree from the University of Houston, Houston, TX, USA, in 1988 and the M.S. and Ph.D. degrees from the University of Colorado Boulder, Boulder, CO, USA, in 1990 and 1994, respectively. From 1994 to 1996, he was with Advanced Energy Inc., Fort Collins, CO, USA, where he was involved with high-frequency power supply design. From 1996 until 1998, he was with the Delphi Division, Saginaw Steering Systems World Headquarters, Saginaw, MI, USA, where he worked on electrical power steering. From 1998 until 2006, he was with TRW Automotive, Sterling Heights, MI, USA, working on electrical power steering development for column and rack drives. Since 2006, he has been an Associate Professor with the Department of Electrical Engineering, United Arab Emirates University (UAEU), Al-Ain, UAE. He is the Coordinator of the newly found Renewable Energy Laboratory at UAEU. His main interests are ac drives, ac–dc, and dc–dc power supplies for renewable energy applications. He has been involved with modeling and fault diagnostics of photovoltaic and fuel cells and their associated power electronics in high-temperature environments. He holds seven awarded patents related to ac drives and automotive applications. Dr. Fardoun was the recipient of the Hariri Foundation Distinguished Graduate Award in 1994.

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Esam H. Ismail (M’93–SM’08) was born in Kuwait. He received the B.S. (magna cum laude) and M.S. degrees from the University of Dayton, Dayton, OH, USA, in 1983 and 1985, respectively, and the Ph.D. degree from the University of Colorado Boulder, Boulder, CO, USA, in 1993, all in electrical engineering. During 1985–1988, he was with the College of Technological Studies, Al-Shaab, Kuwait as a Lecturer, where he is currently a Full Professor with the Department of Electrical Engineering. From 2000 to 2005, he was an Assistant Deputy Director General with Applied Education and Research, Public Authority for Applied Education and Training (PAAET), Adailiyah, Kuwait. In 2011, he was appointed as a Director of the Quality Assurance and Academic Accreditation Office with PAAET. His research interests include single-phase and three-phase low harmonic rectification, highfrequency power conversion, soft switching techniques, and the development of new converter topologies. His recent research interest has been directed at developing new power converter circuits for renewable energy systems (wind, solar, and fuel cells) and their integration to the ac utility grid. Dr. Ismail is a member of Tau Beta Pi (The Engineering Honor Society).

Nasrullah M. Khraim received the B.S. degree in electrical power and machinery engineering from Yarmouk University, Irbid, Jordan, in 1998 and the M.S. degree in electrical engineering from the United Arab Emirates University, Al-Ain, UAE, in 2013. He was a Laboratory Engineer with Yarmouk University for three years. In 2000, he joined Siemens, Jeddah, Saudi Arabia. From 2003 to 2006, he was with ABB, Dubai, UAE. Since 2006, he has been an Operations Planning Engineer with Al-Ain Distribution Company, Al-Ain. His research interests are in high-efficiency ac–dc converters, power factor correction for utility applications, and renewable energy systems.

Ahmad J. Sabzali (M’85) received the M.Sc. degree from North Carolina A&T State University, Greensboro, NC, USA, in 1986 and the Ph.D. degree from the University of Bristol, Bristol, U.K., in 1996, both in electrical engineering. Since 1983, he has been with the Electrical Engineering Department, College of Technological Studies, Al-Shaab, Kuwait, where he is currently an Associate Professor of Electrical Engineering. His research interests are resonant converters, dc–dc converters, electric machine drives, and control.

Mustafa A. Al-Saffar (M’08) received the B.S. and M.S. degrees in electrical engineering from the University of Dayton, Dayton, OH, USA, in 1983 and 1985, respectively, and the Ph.D. degree from the University of Wisconsin–Madison, Madison, WI, USA, in 1997. Since 1985, he has been with the Electrical Engineering Department, College of Technological Studies, Al-Shaab in Kuwait, where he is currently an Associate Professor. His research interests include advanced control techniques, high-power-factor rectifiers, and electric drive systems.

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Bridgeless High-Power-Factor Buck-Converter Operating in Discontinuous Capacitor Voltage Mode Abbas A. Fardoun, Senior Member, IEEE, Esam H. Ismail, Senior Member, IEEE, Nasrullah M. Khraim, Ahmad J. Sabzali, Member, IEEE, and Mustafa A. Al-Saffar, Member, IEEE

Abstract—In this paper, a new bridgeless single-phase ac–dc power factor correction (PFC) rectifier based on buck topology operating in discontinuous capacitor voltage mode (DCVM) is proposed. The bridgeless topology and the presence of only one or two semiconductor switches in the current flowing path during each interval of the switching cycle result in lower conduction losses compared with the conventional DCVM buck PFC rectifier. The DCVM operation offers additional advantages such as zero-voltage turn-off in the power switches, zero-voltage turn-on in the output diode, and continuous input current. Hence, the electromagnetic interference noise emission is minimized. The converter achieves high power factor naturally with low total harmonic distortion in the input current. Theoretical analysis and experimental results for 100 W/48 Vdc at 100 Vrms line voltage are provided to evaluate the performance of the proposed scheme. The measured conversion efficiency reached 96.3%. Index Terms—Discontinuous capacitor voltage mode (DCVM), electromagnetic interference (EMI), power factor correction (PFC), total harmonic distortion (THD).

I. I NTRODUCTION

P

OWER supplies with active power factor correction (PFC) techniques are becoming necessary for many types of electronic equipment to meet harmonic regulations and standards, such as the IEC 61000-3-2 [1]. Discontinuous inductor current mode (DICM) and discontinuous capacitor voltage mode (DCVM) are typically suitable for low-power applications (< 300 W); however, both topologies have, in general, inherent PFC properties unlike continuous current mode (CCM) topologies. Active PFC techniques based on basic dc–dc converter topologies have been developed for high power factor (PF) and low input current harmonic ac/dc Manuscript received September 7, 2013; revised December 10, 2013; accepted January 28, 2014. Date of publication February 11, 2014; date of current version September 16, 2014. Paper 2013-IPCC-675.R1, presented at the 2013 IEEE Energy Conversion Congress and Exposition, Denver, CO, USA, September 16–20, and approved for publication in the IEEE T RANSACTIONS ON I NDUSTRY A PPLICATIONS by the Industrial Power Converter Committee of the IEEE Industry Applications Society. This work was supported in part by the Research Affairs at the United Arab Emirates University. A. A. Fardoun is with the Department of Electrical Engineering, University of United Arab Emirates, Al-Ain, UAE (e-mail: [email protected]). E. H. Ismail, A. J. Sabzali, and M. A. Al-Saffar are with the College of Technological Studies, Al-Shaab 36051, Kuwait (e-mail: [email protected]; [email protected]; [email protected]). N. M. Khraim is with the EOMD/NMD/OP&S/OPL, Al Ain Distribution Company, Al-Ain, UAE (e-mail: [email protected]). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TIA.2014.2305771

rectification [2], [3]. However, conventional PFC rectifiers allow the current to flow through two bridge diodes in addition to the switching component of the converter. This results in higher conduction losses increasing the thermal stresses of the converter. In an effort to maximize the power supply efficiency, considerable research efforts have been directed toward designing bridgeless PFC circuits where the current flows through a minimum number of switching devices compared with the conventional PFC rectifier. Accordingly, the converter conduction losses can be significantly reduced, and higher efficiency can be obtained and cost savings. Recently, several bridgeless PFC rectifiers have been introduced to improve the rectifier power density and/or reduce noise emissions via soft switching techniques or coupled magnetic topologies [4]–[10]. However, all of these rectifiers operate in DICM and suffers from high switch current stress causing higher conduction losses. In addition, a more robust input filter must be employed to suppress the high-frequency components of the pulsating input current, which increases the overall weight and cost of the rectifier. Interleaving two bridgeless boost converters can significantly minimize the input current ripple and doubles the transferable power [11]. However, besides the complex control, interleaving PFC boost converters have low efficiency at low power levels due to high component count. Thus, for universal input line and for low-power applications (< 300 W), all of the reported topologies in [4]–[11] suffer from having low efficiency at low input line (vac = 90 Vrms ) due to the high input current, which produces higher conduction losses in the circuit components. Operating the converter at the boundary of DICM/CCM with variable switching frequency [12] can improve the efficiency at low line at the expense of complex control. On the other hand, the buck PFC is an attractive solution for universal input voltages at power levels (< 300 W). The buck PFC can achieve high efficiency over the entire universal input line voltage range with distorted input current that comfortably passes the limits imposed by IEC 61000-3-2 requirements [1]. In addition, the ability of the buck PFC converter to generate output voltages less than the line peak voltage has beneficial effect on the performance of the downstream dc/dc output stage because it allows a more efficient design for the dc/dc stage by using lower voltage-rated semiconductor devices. In [13], a bridgeless buck PFC rectifier operating in CCM with clampedcurrent-mode control is proposed. High efficiency is achieved over the entire load, and input voltage ranges at the cost of complicating the control circuitry.

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Fig. 1. Proposed bridgeless DCVM PFC topology with two active switches.

Fig. 2.

The drawbacks of complex control associated with CCM operation and high current stress associated with DICM operation can be overcome by operating the converter in DCVM mode. This operation mode offers soft turn-off switch capability; the soft turn-off capability allows using insulated-gate bipolar transistor (IGBT) as the switching device that typically has higher turn-off losses due to the tail current of IGBT. In addition, continuous input current can be obtained with converters operating in DCVM; hence, the input filter size is minimized, and the electromagnetic interference (EMI) noise emissions are reduced. Several DCVM topologies with inherent PFC capability have been published in the literature [14]–[18]. However, all of these topologies utilize a full bridge rectifier as a front end that results in lower efficiency. In this paper, a new bridgeless buck converter operating in DCVM mode is presented. Unlike the PFC boost converter, the proposed converter has the same advantages as the conventional full-bridge PFC buck DCVM converter such as inherent inrush current limitation during startup and overload conditions, lower input current ripple, lower diode reverse recovery losses, and less EMI noise. Compared with the conventional full-bridge PFC buck DCVM converter, the proposed converter has lower number of simultaneously conducting semiconductor components; hence, the conduction losses and the thermal stresses on the semiconductor devices are further reduced, and the circuit efficiency is improved. It should be mentioned here that the main drawback of the DCVM operation is the switch voltage stresses, which increase with the load current. Thus, the proposed converter is intended for low-power applications. For high-power applications, then fixed duty-cycle variable frequency control should be used to compensate for load variations in order to avoid an additional increase in the switch voltage stress.

cost. However, a better thermal performance can be achieved with the two inductors compared with a single inductor. In addition, unlike DICM PFC converters, the continuous input current results in low conducted EMI noise, which reduces input filtering requirements dramatically. The return diodes Dp and Dn always provide low-impedance current path for the return current.

II. P ROPOSED B RIDGELESS C ONVERTERS Figs. 1 and 2 show the two proposed bridgeless DCVM PFC buck converters. Fig. 1 shows the first topology, which utilizes two power switches (Q1 and Q2 ). The two switches can be driven by the same control signal, which significantly simplifies the control circuit. Note that Q1 and Q2 are single quadrant switches; hence, a diode is added in series with the switch. The second topology utilizes a single switch instead of two switches, as shown in Fig. 2. Compared with the conventional full-bridge DCVM buck topology, the structure of the proposed topology utilizes one additional inductor and one capacitor that are often described as a disadvantage in terms of size and

Proposed single-switch bridgeless DCVM PFC topology.

III. P RINCIPLE OF O PERATION AND A NALYSIS The converter of Fig. 1 is analyzed. The analysis assumes the proposed converter operates at a steady-state condition in addition to the following assumptions. 1) The input signal is a pure sinusoidal voltage. 2) Inductors L1 and L2 are large enough such that the current through them can be considered constant over one switching cycle Ts . 3) The low-frequency energy storage element Co is large enough such that the output voltage Vo can be considered constant during the half-line cycle of the line frequency fL . 4) The input capacitances C1 and C2 have low capacitance values to operate in DCVM. During the positive half-line cycle, L1 -C1 -Q1 -Lo -Do are active through diode Dp , which connects the input ac source to the output ground. During the negative half-line cycle, L2 -C2 -Q2 -Lo -Do are active through diode Dn , which connects the input ac source to the output ground. Due to the symmetry of the circuit, it is sufficient to analyze the circuit during the positive half-cycle of the input voltage. The circuit operation in DCVM can be divided into three distinct operating stages during one switching period Ts , as shown in Fig. 3. The topological stages of the proposed converter over a switching period Ts can be briefly described as follows. Stage 1 [0 ≤ t ≤ D1 Ts ]: in this stage, switch Q1 is turned on, and capacitor C1 is being discharged. The switch current iQ1 is equal to the output inductor Lo current iLo , whereas iC1 = iL1 − iLo at the condition iLo > iL1 . During this stage, the diode Do is reversed biased by the voltage across capacitor C1 . This interval ends when the voltage across the input capacitor VC1 linearly decreases to zero. Stage 2 [D1 Ts ≤ t ≤ DTs ]: in this stage, switch Q1 is still turned on and the input capacitor C1 stays discharged. The switch current iQ1 is equal to the input current iL1 . The output stage diode Do starts conducting. The diode current

FARDOUN et al.: BRIDGELESS HIGH-POWER-FACTOR BUCK-CONVERTER OPERATING IN DCVM

Fig. 3. Topological stages over one switching period Ts during positive halfline cycle.

during this stage is equal to iLo − iL1 . This stage ends when Q1 is turned off. Stage 3 [DTs ≤ t ≤ Ts ]: this stage starts when switch Q1 is turned off. The input capacitor current iC1 is charged by the input current iL1 ; hence, the input capacitor voltage VC1 linearly increases and reaches a maximum of VCM at the end of the switching cycle t = Ts . During this interval capacitor, C1 is being charged with a constant current (iL1 ). A. Voltage Conversion Ratio From Fig. 4 at steady state, the capacitor voltage can be expressed, as shown below over one switching cycle. Thus, vC1(t)

⎧1 ⎨C1 [iL1 (1−D)Ts +(iL1 −iLo )t] , = 0, ⎩ iL1 C1 (t−DTs ),

⎫ 0 ≤ t ≤ D1 T s ⎬ D1 Ts ≤ t ≤ DTs . DTs ≤ t ≤ Ts ⎭ (1)

The maximum voltage at the input capacitor C1 can be expressed as VCM =

iL1 (1 − D)Ts . C1

(2)

The average voltage across the input inductor L1 over one switching cycle Ts is zero at steady-state condition. Hence, the average voltage across the input capacitor C1 is equal to the input voltage. Thus, vac (t)T s = VC1 T s =

1 1 D1 VCM + (1 − D)VCM . 2 2

(3)

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Fig. 4. DCVM waveforms over one Ts for the converter of Fig. 1.

Fig. 4 illustrates the theoretical steady-state DCVM waveforms over one switching cycle during the positive half-line cycle of the input voltage.The input voltage vac (t) is considered to be an ideal sine wave, i.e., vac (t) = Vm sin ωt

(4)

where Vm is the peak amplitude, and ω is the line angular frequency. Similarly, by applying volt-second across Lo over the switching cycle, the average output voltage Vo can be obtained as Vo =

1 D1 VCM . 2

(5)

From (3) and (5), the following relation can be obtained: Vo D1 = . VC1 T s 1 − D + D1

(6)

By applying capacitor charge balance over one switching cycle for capacitor C1 , the following relation is obtained: D1 (iL1 − iLo ) + (1 − D)iL1 = 0.

(7)

The switching network has an effective input resistance (Re ) that can be obtained by manipulating (2), (3), (6), and (7) and is given by 2 vac T s VC1 T s vac T s D Ts Re = = = (8) iL1 iL1 2C1 vac T s − Vo where D = 1 − D. The steady-state averaged DCVM model (low-frequency model) for the proposed converter can be expressed, as shown in Fig. 5. Referring to Fig. 3, the average voltage over one switching cycle of vC1 (t) and v2 (t) are

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Fig. 5. Large-signal averaged DCVM model of the proposed converter.

presented as VC1 and V2 in Fig. 5, respectively, and they can be expressed as IL1 Ts D (D1 + D ) 2C1

vC1 (t) = VC1 = v2 (t) = V2 =

IL1 Ts D D1 . 2C1

(9) Fig. 6.

(10)

The time-varying rectified input current iL1 (t) over the whole line cycle can be obtained from (4) and (8) as iL1 (t) =

vac (t) 2C1 Vm = (| sin ωt| − M ) Re Ts D2

(11)

where M is the voltage conversion ratio of the output voltage to the peak input voltage. It shall be noted that the above equation is only valid for vac (t) > Vo . For Vo > vac (t), the input current is zero for the buck converter. In other words, the input current is only valid over the range ωt ∈ (α, π − α)

Eout

M 2 (sin(ωt) − M )2 = Kcrit . ηY sin2 (ωt)

(21)

Note that the maximum value of Kcrit occurs at ωt = π/2 and can be expressed as Kcrit- max =

M 2 (1 − M )2 . ηY

(22)

(15)

where η is the conversion efficiency, and the dimensionless parameter K is defined as 2RL C1 . Ts

K

vac (t), as shown Fig 19. The waveforms of the input capacitors’ voltages over the line cycle are shown in Fig. 20. It can be observed that they are shifted by 180◦ , and C1 is operating during the positive half-line cycle, whereas C2

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Fig. 21. Experimental results for the capacitor voltage and switch voltage over switching cycle.

Fig. 23. Experimental results for the input current, input voltage, and output voltage for the full-bridge DCVM buck converter. (vac = 100 Vrms , Vo = 48 V, Po = 100 W).

V. C ONCLUSION

Fig. 22. Calculated harmonic content of the input line current for the converter of Fig. 1. (vac = 100 Vrms , Vo = 48 V, Po = 100 W).

is operating during the negative half-line cycle. The measured peak capacitor voltage is close 385 V, and it matches the stresses of Table IV. The measured waveforms of the voltage across the active switch and the input capacitor voltage over several switching cycles are shown in Fig. 21. It can be observed that the switch voltage is turned off at zero voltage, and similarly, the output diode Do is turned on at zero voltage. The capacitor voltage trace of Figs. 20 and 21 verifies the converter operation in DCVM. The measured efficiency of the converter reached 96.3% at 100 W. It must be noted that the measured efficiency is lower than the simulated one. This could be due to the fact that the loss model of the simulated components is lower than the real components used in the experimental setup. Fig. 22 shows the simulated and measured harmonic content of the input line current at 100 Vrms together with the limits of EN61000-3-2 Class D standard. It is evident from Fig. 22 that the proposed converter is capable of producing a low harmonic distortion in line current that is well below the limits specified in EN61000-3-2 Class D requirements. Finally, a prototype of the conventional full-bridge DCVM buck PFC converter is constructed and tested under the same operating conditions. The circuit parameters used for this prototype are the same as those used for the proposed converter of Fig. 1. The bridge rectifier consists of four slow-recovery diodes similar to the type of diodes Dp and Dn used in Fig. 1. Experimental waveforms and measured efficiency for the conventional full-bridge DCVM buck PFC are depicted in Fig. 23. As a result, the efficiency improvement for the proposed scheme is about 0.6%, compared with the conventional full-bridge DCVM buck converter.

A single-phase bridgeless step-down buck PFC converter topology operating in DCVM has been introduced. The proposed converter can achieve natural PFC with low line current harmonic distortion while ensuring zero-voltage switching for the active switches and the dc side diode. Expressions for peak component stresses and K as a function of gain M and its effect on the converter discontinuous mode are given and allow the optimization of the power stage design. The experimental results verify the advantage of DCVM topology of soft switch turn-off and continuous input current. The efficiency, power factor and THD of the converter have been improved versus the full-bridge DCVM topology. Closed form equations to identify DCVM converter operation over the line period have been developed and verified. The proposed topology complies with the international standards, i.e., EN 61000-3-2. The new topology has been verified via experimental laboratory prototype. The measured efficiency peaks at 96.3%. R EFERENCES [1] Limits-Limits for Harmonic Current Emissions (Equipment Input Current ≤ 16 A per Phase), IEC 61000-3-2, 2010, EMC Part 3-2. [2] F. Musavi, M. Edington, W. Eberle, and W. Dunford, “Control loop design for a PFC boost converter with ripple steering,” IEEE Trans. Ind. Appl., vol. 49, no. 1, pp. 118–126, Jan./Feb. 2013. [3] Y. Ohnuma and J. Itoh, “A novel single-phase buck PFC AC-DC converter with power decoupling capability using an active buffer,” IEEE Trans. Ind. Appl., vol. 50, no. 3, pp. 1905–1914, May/Jun. 2014. [4] H.-Y. Tsai, T.-H. Hsia, and D. Chen, “A family of zero-voltage-transition bridgeless power-factor-correction circuits with a zero-current-switching auxiliary switch,” IEEE Trans. Ind. Electron., vol. 58, no. 5, pp. 1848– 1855, May 2011. [5] B. Su, J. Zhang, and Z. Lu, “Totem-pole boost bridgeless PFC rectifier with simple zero-current detection and full-range ZVS operating at the boundary of DCM/CCM,” IEEE Trans. Power Electron., vol. 26, no. 2, pp. 427–435, Feb. 2011. [6] M. Mahdavi and H. Farzanehfard, “Zero-current-transition bridgeless PFC without extra voltage and current stress,” IEEE Trans. Ind. Electron., vol. 56, no. 7, pp. 2540–2547, Jul. 2009. [7] A. J. Sabzali, E. H. Ismail, M. A. Al-Saffar, and A. A. Fardoun, “A new bridgeless PFC Sepic and Cuk rectifiers with low conduction and switching losses,” IEEE Trans. Ind. Appl., vol. 47, no. 2, pp. 873–881, Mar./Apr. 2011. [8] H. L. Cheng, Y. C. Hsieh, and C. S. Lin, “A novel single-stage high-powerfactor AC/DC converter featuring high circuit efficiency,” IEEE Trans. Ind. Electron., vol. 58, no. 2, pp. 524–532, Feb. 2011. [9] M. Mahdavi and H. Farzanehfard, “Bridgeless SEPIC PFC rectifier with reduced components and conduction losses,” IEEE Trans. Ind. Electron., vol. 58, no. 9, pp. 4153–4160, Sep. 2011. [10] A. A. Fardoun, E. H. Ismail, A. J. Sabzali, and M. A. Al-Saffar, “A comparison between three proposed bridgeless Cuk topologies and

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conventional topologies for power factor correction,” in Proc. IEEE ICSET, Dec. 2010, pp. 1–6. B. Su and Z. Lu, “An interleaved Totem-Pole boost bridgeless rectifier with reduced reverse-recovery problems for power factor correction,” IEEE Trans. Power Electron., vol. 25, no. 6, pp. 1406–1415, Jun. 2010. L. Huber, Y. Jang, and M. Jovanovic, “Performance evaluation of bridgeless PFC boost rectifiers,” IEEE Trans. Power Electron., vol. 23, no. 3, pp. 1381–1390, May 2008. Y. Jang and M. M. Jovanovi, “Bridgeless high power factor buck converter,” IEEE Trans. Power Electron., vol. 26, no. 2, pp. 602–611, Feb. 2011. N. M. Khraim, A. A. Fardoun, and E. Ismail, “Large and small signal analysis for bridgeless high PFC converter operating in DCVM,” presented at the International Conference on Renewable Energies and Power Quality (ICREPQ’13), Bilbao, Spain, Mar. 2013. C. K. Tse and M. H. L. Chow, “New single-stage power-factor-corrected regulators operating in discontinuous capacitor voltage mode,” in IEEE PESC, 1997, pp. 371–377. Y. S. Lee and S. Y. R. Hui, “Modeling, analysis, and application of buck converters in discontinuous-input-voltage mode operation,” IEEE Trans. Power Electron., vol. 12, no. 2, pp. 350–360, Mar. 1997. V. Grigore and J. Kyyrä, “High power factor rectifier based on buck converter operating in discontinuous capacitor voltage mode,” IEEE Trans. Power Electron., vol. 15, no. 6, pp. 1241–1249, Nov. 2000. H. Y. Kanaan and K. Al-Haddad, “A modified Sheppard-Taylor power factor corrector operating in discontinuous capacitor voltage mode,” in Proc. IEEE ISIE , Jun. 2011, pp. 81–88. W. J. Sarjeant, F. W. MacDougall, and D. W. Larson, “Energy storage in polymer laminate structures-ageing and diagnostic approaches for life validation,” IEEE Elect. Insul. Mag., vol. 13, no. 1, pp. 20–24, Feb. 1997. Z. Li et al., “Lifetime evaluation of high energy density capacitor based experimental investigations,” in Proc. IEEE 19th PPC, 2013, pp. 1–4. IC-Illinois Capacitors, Inc., Jul. 10, 2014. [Online]. Available: http:// www.illinoiscapacitor.com/tech-center/lifecalculators.aspx Energy Star, ENERGY STAR Program Requirements for External Power Supplies (Version 2.0). Jul. 10, 2014. [Online]. Available: http://www.energystar.gov/ia/partners/product_specs/program_reqs/eps_ prog_req.pdf R. W. Erickson and D. Maksimovic, Fundamentals of Power Electronics, 2nd ed. Norwell, MA, USA: Kluwer, 2001. B. A. Mather and D. Maksimovic, “A simple digital power-factor correction rectifier controller,” IEEE Trans. Power Electron, vol. 26, no. 1, pp. 9–19, Jan. 2011. D. G. Lamar, J. Sebastian, M. Arias, and A. Fernandez, “On the limit of the output capacitor reduction in power-factor correctors by distorting the line input current,” IEEE Trans. Power Electron., vol. 27, no. 3, pp. 1168– 1176, Mar. 2012. J.-C. Tsai et al., “Triple loop modulation (TLM) for high reliability and efficiency in a power factor correction (PFC) system,” IEEE Trans. Power Electron, vol. 28, no. 7, pp. 3447–3458, Jul. 2013.

Abbas A. Fardoun (M’90–SM’05) received the B.S. degree from the University of Houston, Houston, TX, USA, in 1988 and the M.S. and Ph.D. degrees from the University of Colorado Boulder, Boulder, CO, USA, in 1990 and 1994, respectively. From 1994 to 1996, he was with Advanced Energy Inc., Fort Collins, CO, USA, where he was involved with high-frequency power supply design. From 1996 until 1998, he was with the Delphi Division, Saginaw Steering Systems World Headquarters, Saginaw, MI, USA, where he worked on electrical power steering. From 1998 until 2006, he was with TRW Automotive, Sterling Heights, MI, USA, working on electrical power steering development for column and rack drives. Since 2006, he has been an Associate Professor with the Department of Electrical Engineering, United Arab Emirates University (UAEU), Al-Ain, UAE. He is the Coordinator of the newly found Renewable Energy Laboratory at UAEU. His main interests are ac drives, ac–dc, and dc–dc power supplies for renewable energy applications. He has been involved with modeling and fault diagnostics of photovoltaic and fuel cells and their associated power electronics in high-temperature environments. He holds seven awarded patents related to ac drives and automotive applications. Dr. Fardoun was the recipient of the Hariri Foundation Distinguished Graduate Award in 1994.

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Esam H. Ismail (M’93–SM’08) was born in Kuwait. He received the B.S. (magna cum laude) and M.S. degrees from the University of Dayton, Dayton, OH, USA, in 1983 and 1985, respectively, and the Ph.D. degree from the University of Colorado Boulder, Boulder, CO, USA, in 1993, all in electrical engineering. During 1985–1988, he was with the College of Technological Studies, Al-Shaab, Kuwait as a Lecturer, where he is currently a Full Professor with the Department of Electrical Engineering. From 2000 to 2005, he was an Assistant Deputy Director General with Applied Education and Research, Public Authority for Applied Education and Training (PAAET), Adailiyah, Kuwait. In 2011, he was appointed as a Director of the Quality Assurance and Academic Accreditation Office with PAAET. His research interests include single-phase and three-phase low harmonic rectification, highfrequency power conversion, soft switching techniques, and the development of new converter topologies. His recent research interest has been directed at developing new power converter circuits for renewable energy systems (wind, solar, and fuel cells) and their integration to the ac utility grid. Dr. Ismail is a member of Tau Beta Pi (The Engineering Honor Society).

Nasrullah M. Khraim received the B.S. degree in electrical power and machinery engineering from Yarmouk University, Irbid, Jordan, in 1998 and the M.S. degree in electrical engineering from the United Arab Emirates University, Al-Ain, UAE, in 2013. He was a Laboratory Engineer with Yarmouk University for three years. In 2000, he joined Siemens, Jeddah, Saudi Arabia. From 2003 to 2006, he was with ABB, Dubai, UAE. Since 2006, he has been an Operations Planning Engineer with Al-Ain Distribution Company, Al-Ain. His research interests are in high-efficiency ac–dc converters, power factor correction for utility applications, and renewable energy systems.

Ahmad J. Sabzali (M’85) received the M.Sc. degree from North Carolina A&T State University, Greensboro, NC, USA, in 1986 and the Ph.D. degree from the University of Bristol, Bristol, U.K., in 1996, both in electrical engineering. Since 1983, he has been with the Electrical Engineering Department, College of Technological Studies, Al-Shaab, Kuwait, where he is currently an Associate Professor of Electrical Engineering. His research interests are resonant converters, dc–dc converters, electric machine drives, and control.

Mustafa A. Al-Saffar (M’08) received the B.S. and M.S. degrees in electrical engineering from the University of Dayton, Dayton, OH, USA, in 1983 and 1985, respectively, and the Ph.D. degree from the University of Wisconsin–Madison, Madison, WI, USA, in 1997. Since 1985, he has been with the Electrical Engineering Department, College of Technological Studies, Al-Shaab in Kuwait, where he is currently an Associate Professor. His research interests include advanced control techniques, high-power-factor rectifiers, and electric drive systems.