Bridgeless Power Factor Correction Circuits with Voltage-Doubler Configuration Dylan Dah-Chuan Lu and Wenfei Wang Power Engineering Laboratory School of Electrical and Information Engineering The University of Sydney, NSW 2006, Australia
[email protected],
[email protected]
Abstract—This paper presents a generalized approach to deriving single-phase power factor correction (PFC) circuits with bridgeless and voltage-doubler structures. The approach requires two dc/dc converters connected in a parallel-input series-output manner. Compared to conventional full-bridge diode rectified PFC circuit, which has two diodes along the input current path, the PFC circuits derived by this approach have one diode only, hence reducing the converter losses. Through the proposed approach, some recently reported bridgeless PFC circuits have been identified and new possible combinations can be generated. A design example of dual buck dc/dc converters operating in discontinuous-input-voltage mode (DIVM) is presented to demonstrate the usefulness of the proposed approach.
I. I NTRODUCTION Full-bridge diode rectifier has long been used in ac/dc conversion due to its simple and robust circuit. A single dc/dc converter, which is connected after the rectifier, is then able to perform power factor correction (PFC) and output voltage regulation. However as the output power increases, the forward voltage drop across these standard Si diodes will cause significant conduction loss. Bridgeless PFC rectifiers have been introduced to reduce or eliminate the full-bridge rectifier hence its losses [1]. There are a number of approaches to produce bridgeless PFC circuits. One approach is to replace all or partly the full-bridge rectifier by MOSFET which has lower conduction loss if the on-state resistance is small enough [2]. The other approach is to use a pair of MOSFETs to form a bi-directional switch for bi-directional current flow during the positive and negative ac line cycles [3]. For ac/dc conversion, voltage-doubler is usually used in conjuction with a range switch so that the voltage at the doubler is within a narrow voltage range for universal input voltage application. It has also been used in improving power factor in passive ac/dc circuits [4]-[5] and active ac/dc circuits [6]. In [6] it is shown that, as compared to conventional full-bridge rectifier, the rectifier which has a voltage doubler reduces the capacitor voltage by half. This reduces the cost as c Copyright 2011 IEEE. Published in the Proceedings of the 2011 IEEE International Conference on Power Electronics and Drive Systems, 5-8 December 2011, Singapore. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works, must be obtained from the IEEE.
higher voltage electrolytic capacitors (e.g. 400V) are generally more expensive than lower voltage ones (e.g. 250V). Recently there are a number of ac/dc PFC circuits introduced which combined bridgeless and voltage-doubler structures to improve conversion efficiency. Not only the number of semiconductors for input current path is reduced, the voltage stress on the power transistors is also reduced. So far, the bridgeless PFC circuits with voltage-doubler reported are mainly on boost [7]-[9], buck [10] and SEPIC [11] converter topologies. This paper hence explores the possibility of deriving new topologies based on a general bridgeless PFC converter with voltage-doubler structure, and discusses some design considerations of these PFC circuits. A buck topology with discontinuous-input-voltage mode (DIVM) operation is designed and experimented to prove the feasibility of the proposed approach. II. D ERIVING B RIDGELESS PFC C IRCUITS VOLTAGE - DOUBLER
WITH
A. Basic requirement Fig. 1 shows the general structure of bridgeless PFC circuit with a voltage-doubler. Two dc/dc converters are required and are connected in a parallel-input series-output manner. Therefore the output voltage, Vo , can be expressed as Vo = VC1 + VC2
(1)
The two dc/dc converters can be of the same type or of different types. But the PFC control must ensure the input current waveshape and average input current of positive half line cycle and that of the negative half cycle are equal. Otherwise, even current harmonics will be generated. During any half-cycle, only one dc/dc converter is in operation and the other is idle. B. Formation of PFC circuits Fig. 2(a) shows two boost dc/dc converters forming a bridgeless PFC circuit with voltage doubler structure. Note that a common path must be available for both converters to arrange their output voltages in series. Diodes Da and Db are used to force unidirectional current flow and prevent charging up of both inductors at the same time. This is in particular valid for MOSFET switch. As shown in Fig. 2(a), suppose during the positive line cycle S1 is operating and S2 is idle. If
Da and Db are absent, inductor L2 will still be charged up by Vac due to the conduction of body diode even though it is not supposed to be charged during this positive half line period. The common path requirement also applies to other dc/dc converters. Fig. 2(b) shows the PFC circuit formed by two buck dc/dc converters. It has the same structure as that proposed in [10]. Figs. 2(c), 2(d) and 2(e) are the bridgeless PFC circuits with voltage-doubler formed by dual buckboost converters, dual flyback converters and dual SEPIC converters [11] respectively. In fact, based on this general structure, any dc/dc converter can be used to form a bridgeless PFC converter with voltage-doubler. III. D ESIGN E XAMPLE , A NALYSIS R ESULTS
AND
Da L1 D1
C1
S1
+ VC1 −
+ Vo
Vac
−
Db
Common path
E XPERIMENTAL
L2 D2
-
C2
S2
− VC2 +
(a) Dual boost converters [7]
A. Discontinuous input voltage mode (DIVM) buck converter In order to show the usefulness of the proposed PFC converter structure, two buck converters working in discontinuous input voltage mode (DIVM) are put into the structure, as shown in Fig. 3, and studied. The DIVM buck converter provides continuous input current and inherent PFC properties by adding an inductor-capacitor filter [12], [13]. The capacitance (Ca and Cb ) of the filter is small enough to allow discontinuous voltage operation for every switching cycle, i.e., its voltage drops to zero before the switch is turned off.
Da S1
L1 C1 D1
+ VC1 −
Vac
+ Vo −
Db L2
S2
C2 D2
− VC2 +
B. Circuit Operation The operation of the DIVM buck converters within a switching cycle has five stages and is explained, with the aid of Figs. 4 and 5, as follows. Suppose the input ac voltage is at its positive half cycle and the upper DIVM buck converter, as shown in Fig. 3, is operating and the lower one is on idle mode. Prior to t0 , the input capacitor Ca is charging by input voltage and L1 operates in continuous conduction mode. Since the switching frequency is much higher than the AC line frequency, the input voltage v ac (t) is considered as a constant within a switching period. The output load RL with C1 and C2 form their own current loop which does not connect to the main current loops of the two buck converters. The DIVM buck converter behaves the same way as a normal
(b) Dual buck converters [10]
Da S1 D1
C1
L1
− VC1 +
− Vo
Vac
+ Db S2 D2 L2
C2
+ VC2 −
(c) Dual buck-boost converters dc/dc Converter 1
C1
+ VC1 −
+ Vo
Vac
dc/dc Converter 2
Fig. 1.
Fig. 2. Different converter topologies for the proposed bridgeless PFC voltage-doubler structure.
C2
+ VC2 −
−
General structure of bridgeless PFC circuit with voltage doubler.
buck converter in which the input current will flow into the circuit when the input voltage is higher than the output voltage. Therefore the converter will introduce dead angles of input current when Vo > vac (t). The following explanation assumes vac (t) ≥ Vo : Stage 1 (t0 ≤ t < t1 ) [Fig. 4(a)]: At t = t0 , S1 is turned on. Capacitor Ca discharges through the switch and charges
Da
T1
D1
C1 S1
+ VC1 −
Vac
+ Vo
Db
T2
D2 − C2
S2
+ VC2 −
(d) Dual flyback converters
Da
CB1
D1
C1 S1
+ VC1 −
+ Vo −
Vac Db
CB2
D2
C2 S2
− VC2 +
(e) Dual SEPIC converters Fig. 2. Different converter topologies for the proposed bridgeless PFC voltage-doubler structure.
Da La Ca
S1 D1
L1 C1
+ VC1 − RL
Vac
to discharge and vCa drops below VC1 , L1 begins to discharge as the voltage across it would become (vCa − VC1 ) < 0. Stage 3 (t2 ≤ t < t3 ) [Fig. 4(b)]: At t = t2 , Ca is completely discharged and D1 is turned on. vCa is clamped by D1 . La continues to charge and the voltage across it equals (vac − Vo ). Therefore output inductor current iL1 is the sum of two currents, i.e. iLa + iD1 . Stage 4 (t3 ≤ t < t4 ) [Fig. 4(c)]: At t = t3 , S1 is turned off. Both La and Ca are charged by input voltage. The rate of change of voltage on La slows down during this interval as its voltage equals (vac − vCa ) and is decreasing as vCa increases linearly. During this stage, iD1 only carries iL1 . Stage 5 (t4 ≤ t < t5 ) [Fig. 4(c)]: At t = t4 , vCa ≤ vac and thus La begins to discharge but Ca keeps charging as iLa > 0. The period repeats when S1 turns on again at t = t5 . The circuit operation of the upper buck converter can be applied to the lower one, which takes place at the negative half line cycle, as they are identical. C. PFC Capability Suppose the inductance of La is large enough such that the input current ripple is small, the peak voltage of VCa is given by iin (Ts ) × [1 − d(t)]Ts (2) VCa,peak = Ca where iin (Ts ) denotes the average input current per switching period Ts . The average input voltage during one switching period is equal to the average voltage on Ca , which is given by VCa,peak [1 − d(t) + ds (t)] (3) v ac (t) = 2 By combining (2) and (3), and considering the voltage-doubler structure, the voltage conversion ratio of the PFC circuit is expressed as 2ds (t) Vo = v ac (t) 1 − d(t) + ds (t)
+ Vo
From (4), ds (t) can be expressed as
−
Db Lb Cb
S2 D2
L2 C2
− VC2 +
ds (t) =
PFC circuit by dual DIVM buck converters.
Ts [1 − d(t)][1 − d(t) + ds (t)] v ac (t) = 2Ca iin (t)
(5)
(6)
If ds (t)
