Briefs - IEEE Xplore

IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 54, NO. 2, FEBRUARY 2007

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Briefs Enhancement of Memory Performance Using Doubly Stacked Si-Nanocrystal Floating Gates Prepared by Ion Beam Sputtering in UHV Kyu Il Han, Yong Min Park, Sung Kim, Suk-Ho Choi, Kyung Joong Kim, Il Han Park, and Byung-Gook Park

Abstract—Structures of SiO2 /SiOx /SiO2 and SiO2 /SiOx /SiO2 / SiOx /SiO2 have been prepared on Si wafers by ion beam sputtering deposition in ultrahigh vacuum (UHV) and subsequently annealed to form single-layer and doubly stacked Si nanocrystals (NCs). Using these two structures, nonvolatile Si-NC floating-gate nMOSFETs were fabricated at x = 1.6 following 1.5-µm CMOS standard procedures. The Fowler–Nordheim tunneling of the electrons through the tunnel oxide, their storage into NCs, retention, and endurance are all investigated by varying the device structure and the thicknesses of the NC and oxide layers. It is shown that charge-retention time is longer, and program/erase (P/E) speeds are faster in doubly stacked devices than in single-layer devices, which seem to result from the optimization of device structure, the exclusion of unwanted defects due to the nature of UHV, and the suppression of charge leakage by the multiple barriers/NC layers in the doubly stacked devices. It is also found that the threshold voltages in the endurance characteristics anomalously increase with the P/E cycles, more strongly in the doubly stacked NC memories. Index Terms—Doubly stacked, ion beam sputtering (IBS), nonvolatile memory (NVM), Si nanocrystals (NCs), ultrahigh vacuum (UHV).

It has been suggested that the charge storage in Si-NC-based nonvolatile memories (NVM) is influenced by several mechanisms including quantum confinement effect and interface/defect states [7]. Therefore, it is very important to distinguish charge storage in Si NCs from that in interface/defect states for understanding and improving the memory effects of the devices containing Si NCs. It has been demonstrated that the interface traps and defects have a strong influence on the charge-retention characteristics in Si-quantum-dot-based MOS memory structures [8]. These results indicate that unwanted defects should be minimized for long-term data retention in Si-NC NVM devices. One of the most popular methods for Si-NC fabrication is the growth of SiOx or SiOx /SiO2 multilayers and subsequent annealing [9]. In this regard, ion beam sputtering deposition (IBSD) is promising among the various fabrication techniques, because it allows for exact control of the oxygen composition and the deposition rate [10], [11]. IBSD can also minimize unwanted defect states due to its ultrahigh vacuum (UHV) nature and the low-damaging effect during the growth. In this brief, we employ 1.5-µm CMOS fabrication processes for nMOSFET NVM devices containing single-layer or doubly stacked Si NCs with defect states minimally reduced by using IBSD under UHV and present the memory characteristics of the devices, especially prominent retention properties compared to the previously reported data.

I. INTRODUCTION

II. EXPERIMENTAL

Nonvolatile-Si-nanocrystal (NC) memories have recently been of considerable interest as a discrete-trap-type storage medium because they are good candidates to overcome the serious limitations of conventional Flash memories [1]–[4]. The use of discrete-trap storage nodes offers an advantage of preventing lateral charge movement, thereby enhancing the memory data retention [5], [6]. Si-NC memories are attractive in view of their fast writing times, small degradation, long retention times, and inherent scalability. Despite intense work, further elaboration on the device structure is needed to improve the stabilities of Si-NC memories, especially their charge-retention characteristics. Several different device structures, for example, multiply stacked Si dots [2], [3], have been fabricated for better retention characteristics, but remarkable improvement has not been obtained until now.

Manuscript received June 20, 2006; revised October 11, 2006. This work was supported by the National Research Program for the 0.1 Terabit NonVolatile Memory Development sponsored by the Korea Ministry of Science and Technology and the NT-IT Share-ISRC Program through the Inter-University Semiconductor Research Center. The review of this brief was arranged by Editor H. S. Momose. K. I. Han, Y. M. Park, S. Kim, and S.-H. Choi are with the Department of Physics and Applied Physics, College of Electronics and Information, Kyung Hee University, Yongin 449-701, Korea (e-mail: [email protected]). K. J. Kim is with Advanced Industrial Technology Group, Korea Research Institute of Standards and Science, Yusong, Taejon 305-340, Korea. I. H. Park and B.-G. Park are with the School of Electrical Engineering and Inter-University Semiconductor Research Center, Seoul National University, Seoul 151-742, Korea. Color versions of one or more of the figures in this brief are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TED.2006.888674

IBSD was employed in UHV to fabricate charge trap layers with structures of SiO2 /SiOx /SiO2 or (SiO2 /SiOx /SiO2 /SiOx /SiO2 ) for memory devices. An Ar+ beam with ion energy of 750 eV and a Si target were used in a reactive IBSD system with a Kaufman-type dc ion gun. The relative film thickness was controlled using a growth rate calibrated by transmission-electron-microscopy (TEM) measurement of a thin film grown within a given time. The deposition chamber was evacuated to a pressure of 5 × 10−9 torr before introducing argon gas into the system. After introduction to the vacuum chamber, the Si target was ion cleaned in situ prior to deposition by exposing it to the ion beam for 10 min. SiO2 layers were deposited by sputtering Si in an oxygen ambient. The oxygen partial pressure during the deposition of SiO2 layers was 1.2 × 10−4 torr. Details of the system are described elsewhere [11]. The stoichiometry of the SiOx films could be analyzed and controlled with in situ X-ray photoelectron spectroscopy (XPS) using Al kα line of 1486.6 eV. A stoichiometric SiO2 thin film was used as a reference for the determination of the relative sensitivity factors of Si 2p and O 1s peaks. For a charge trap layer with single-layer Si NCs, a tunneling SiO2 layer was first grown on an n-type (100) Si wafer at room temperature. Subsequently, a thin SiOx was grown on top of the oxide layer. In this process, oxygen partial pressures were switched for the SiOx and the SiO2 layers without breaking vacuum. The relative oxygen content was controlled by varying the oxygen-gas pressure. Finally, a control oxide was deposited to form an (SiO2 /SiOx /SiO2 ) sandwich structure. Three different samples (5, 12, 3), (15, 12, 3), and (30, 12, 3) were prepared by changing the thickness of each layer, where the numbers in the parentheses indicate the nanometer-scale thicknesses of the control oxide, the SiOx , and the tunnel oxide, in sequence. Similarly, (d, 2, 4, 6, 3), (d, 4, 4, 4, 3), and (d, 6, 4, 3, 3)

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Fig. 1. P/E characteristics of single-layer device (5, 12, 3).

double-layer structures, where d = 5 or 15, were prepared following the (SiO2 /SiOx /SiO2 /SiOx /SiO2 ) structure scheme. After deposition, the samples were annealed at 1100 ◦ C for 20 min in an ultrapure nitrogen ambient using a horizontal furnace to form Si NCs in the SiOx layers. The density and size of NCs were analyzed through photoluminescence and TEM by changing the x value determined with in situ XPS. Based on these results, nonvolatile Si-NC floating-gate nMOSFETs with channel lengths of 3 to 20 µm were fabricated at x = 1.6 following 1.5-µm CMOS standard procedures. The higher resolution TEM images of similar samples confirmed the presence of Si crystallites of approximately 3-4 nm at x = 1.6, as previously reported [10]. Electrical characterization was performed on the devices by using an Agilent 4156C semiconductor parameter analyzer. The programming and erasing operations were carried out with an Agilent 16440A pulse generator together with the Agilent 4156C and 41501B. III. RESULTS AND DISCUSSION Fig. 1 shows the program/erase (P/E) characteristics of the (5, 12, 3) single-layer device by Fowler–Nordheim (FN) tunneling current. During programming, the electrons directly tunnel from the Si substrate through the tunnel oxide and are trapped in the Si NCs. During erasing, the holes tunnel from the valence band of the Si substrate and recombine with the electrons trapped in the Si NCs. The fully programmed and fully erased states are defined as what were programmed by a pulse of (+15 V, 1 s) and erased by a pulse of (−15 V, 1 s), respectively. Saturation of threshold voltage (Vth ) shift is observed at programming voltages of ∼12–14 V for 0.1–1 s in Fig. 1. This behavior is frequently reported in the NC-based Flash memories [12]–[14]. Electrons may tunnel from the channel into the metal contact through the single oxide barrier during the programming at high voltage. The saturation can be reached when currents from the channel to the NCs and from the NCs to the metal gate are in balance. The saturation can also occur due to the finite number of charge-storage nodes provided by Si NCs [15]. After full-time (1 s) programming/erasing at ±14 V, the Vth shifts reach 1.1/1.4 V, respectively. Fig. 2 shows the Vth shifts of the (15, 6, 4, 2, 3) doubly stacked device. The phenomenon of saturation is not observed in the doubly stacked samples. This seems to be because more electrons can be stored in the two NC layers, and the double barriers prevent the electrons in the lower NC layer from reaching the metal contact. In contrast, the saturation behavior is not observed during the erasing, irrespective of the structure. The programmed/erased Vth shifts are about 2.5/0.8 V at ±16 V, respectively, which are enhanced values compared to the single-layer counterpart, the (15, 12, 3) device,

Fig. 2.

P/E characteristics of doubly stacked device (15, 6, 4, 2, 3).

Fig. 3.

P/E cycling characteristics of the devices (5, 12, 3 ) and (5, 6, 4, 2, 3).

showing 1.0/0.7 V at ±16 V. In the single-layer memory, electrons pass through only one oxide barrier, while in the doubly stacked memory, the tunneling will be governed by the multiple energy barriers, resulting in less leak out of electrons from the NCs, in other words, enhancement of Vth shifts. However, there is almost no difference of the Vth shifts between single-layer and doubly stacked devices with a control oxide of 5 nm, probably resulting from easier tunneling, irrespective of the structure due to the thin barrier. Fig. 3 shows the P/E cycling characteristics of the single-layer and doubly stacked devices (5, 12, 3) and (5, 6, 4, 2, 3). Pulses of (+14 V, 10 ms) and (−14 V, 100 ms) were applied to evaluate endurance characteristics for the P/E operations of the (5, 12, 3) device, respectively. The programmed/erased Vth s of the single-layer device show a gradual drift-up almost in a parallel way. The drift-up is accelerated in the doubly stacked device, in which biases of ±17 V for 10 ms/100 ms were applied for the P/E endurance measurements, respectively. In the doubly stacked device with 15-nm-thick control oxide, the programmed/erased Vth s reach very quickly the saturation values, which are almost invariant with P/E cycles, as shown in Fig. 4. This indicates that the increase of the control oxide accelerates the drift-up. This phenomenon can be attributed to the electron trapping in the control oxide. The Si NCs have a smaller capture cross section than the polysilicon floating-gates, which capture all hot electrons injected toward the gate [13], and therefore, only a portion of the injected electrons are captured by the NCs while the rest are either trapped in the control oxide or reach the gate. During the erasing, an incomplete removal of the trapped electrons from the control oxide leads to an increase in the Vth [16]. More significant drift-up in the doubly stacked devices indicates that more electrons are trapped in the multiple oxide layers/interfaces.


Fig. 4.

P/E cycling characteristics of doubly stacked device (15, 6, 4, 2, 3).

Fig. 5.

Retention characteristics of single-layer device (15, 12, 3).

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charge loss. In contrast, the doubly stacked devices show better charge retention, as shown in Fig. 6. The probability for electrons tunneling out from the Si NCs to the channel during the retention period should be much smaller for the doubly stacked devices because there exist multiple energy barriers for the electrons to overcome. In the doubly stacked NC memory, electrons in one NC layer pass through a double tunnel junction separated by the other NC layer based on the quantum confinement and Coulomb blockade effects while they pass through a single tunnel junction in the single-layer NC memory. This means that the charge loss is much less in the case of the doubly stacked devices, and therefore, a long retention time is expected in a doubly stacked memory. At a high temperature of 85 ◦ C, the retention properties usually degrade significantly due to the enhanced thermal tunneling of electrons from the Si NCs. However, for the Vth s at the P/E states of the (15, 2, 4, 6, 3) device, they remain almost unchanged with time, showing very little charge transfer during the retention measurement. The expected charge loss after ten years is ∼14% for this device, which meets the retention requirement of NVMs. In contrast, the charge losses are 28% and 62% for the (15, 4, 4, 4, 3) and the (15, 6, 4, 2, 3) devices, respectively. These results indicate that the charge loss rate is proportional to the memory window and strongly depend on the thickness of each NC layer. The retention characteristics are the best for the device with the thickest lower NC layer with respect to Si substrate, which can result from less back tunneling into the metal contact by the storage of more charges at the longer distance from the control oxide. This may also mean that the charge leakage into the metal contact is more dominant than that into the Si substrate during the retention period for the doubly stacked samples. On the other hand, the devices all show very excellent retention properties during erasing, as shown in Fig. 6. IV. CONCLUSION We employed 1.5-µm CMOS fabrication processes for nMOSFET NVM devices containing single-layer and doubly stacked Si NCs with defect states minimally reduced by using IBSD under UHV. The NVM characteristics were measured for the MOSFETs by varying the thicknesses of the control oxide and Si-NC layer at a fixed 3 nm of the tunnel oxide. The P/E cycling characteristics showed a gradual drift-up in single-layer devices, which was accelerated in the doubly stacked devices and could be attributed to the electron trapping in the multiple oxides/interfaces. The doubly stacked devices showed more excellent retention properties than the singly stacked ones while the former keeping the P/E speeds faster than the latter. It is suggested that the improvements of the NVM properties result principally from the exclusion of unwanted defects due to the nature of UHV and the suppression of charge leakage by the multiple barriers in the doubly stacked devices.

Fig. 6. Retention characteristics of doubly stacked devices (15, 4, 4, 4, 3 ), (15, 6, 4, 2, 3), and (15, 2, 4, 6, 3).

R EFERENCES

Charge-retention capability in NVM devices has been checked by using high-temperature accelerated tests. Fig. 5 presents retention characteristics of the (15, 12, 3) device measured at 85 ◦ C. Although almost 100% charge losses at 85 ◦ C are expected for the single-layer device by extrapolating the retention data up to ten years, the chargeloss speed is relatively slow compared to those of similar single-layer devices reported in the previous publications. As discussed earlier [16], the trapped charges are distributed uniformly through the entire single-layer Si NCs in the FN P/E regime, which can accelerate the

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Strain Engineering to Improve Data Retention Time in Nonvolatile Memory R. Arghavani, N. Derhacobian, V. Banthia, M. Balseanu, N. Ingle, H. M’Saad, S. Venkataraman, E. Yieh, Z. Yuan, L.-Q. Xia, Z. Krivokapic, U. Aghoram, K. MacWilliams, and S. E. Thompson

Abstract—Experimental data show that tensile stress improves and compressive stress degrades retention time for nonvolatile memory (NVM) devices. External mechanical tensile stress and compressive stress are introduced into the NVM floating-gate and nitride trap based memories via four-point wafer bending. The enhanced retention time under tensile stress results from stress-altered changes in the SiO2 /Si barrier height and out-of-plane conductivity mass for floating-gate memories and from changes in the trap activation energy in nitride based memories. Index Terms—Compressive stress, data retention, nonvolatile memory (NVM), read current, strain, tensile stress.

I. INTRODUCTION Conventional CMOS logic device scaling beyond 90-nm node requires local strain engineering to increase electron and hole mobilities and enhance transistor performance [1]–[4]. In addition to increasing mobility, which has some advantages in nonvolatile memory (NVM), strain also alters the SiO2 /Si barrier height, the conductivity mass perpendicular to the SiO2 interface, and electron trap energy levels, all of which will alter the retention time. The charge retention characteristics of an NVM cell are set by the leakage of stored electrons under the specified environmental and operational conditions including power-off mode. For the NVM NAND cell, electrons are generally stored on a floating poly-Si gate, while for NOR , electrons are stored on a floating gate or in nitride traps. With NVM technology in the nanoscale regime, many process steps from cell isolation formation to packaging introduce both intentional and unintentional strain in the floating gate, insulating layers, and channel. There have been early reports on compressive stress being important to minimize since it degrades the retention time [5], [6]. In this brief, we investigate the effect of tensile and compressive stress on floating-gate and nitride trap based NVM retention time. This has applications for intentionally engineering “good” types of strain and removing “bad” types from an NVM process flow. II. EXPERIMENTAL SETUP A flexure-based four-point bending setup is used in applying large (up to 600 MPa) tensile and compressive stress, as shown in Fig. 1(a). A flexure is a long beam with a notch on one end, which gives the beam only one degree of freedom and suppresses the others [7]. The setup has a system of eight such flexure beams, which provide uniaxial upward displacement to the bottom rods in a traditional four-point

Manuscript received May 25, 2006; revised October 17, 2006. The review of this brief was arranged by Editor S. Kimura. R. Arghavani, V. Banthia, M. Balseanu, N. Ingle, H. M’Saad, S. Venkataraman, E. Yieh, Z. Yuan, L.-Q. Xia, and K. MacWilliams are with Applied Materials, Santa Clara, CA 95054 USA. N. Derhacobian is with Adesto Technologies, Belmont, CA 94002 USA. Z. Krivokapic is with Advanced Micro Devices, Sunnyvale, CA 94088 USA. S. E. Thompson is with the College of Engineering, University of Florida, Gainesville, FL 32611 USA. Color versions of one or more of the figures in this brief are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TED.2006.888827 0018-9383/$25.00 © 2007 IEEE