Building an On-Chip Spectrum Sensor for Cognitive ... - IEEE Xplore

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INTEGRATED CIRCUITS FOR COMMUNICATIONS

Building an On-Chip Spectrum Sensor for Cognitive Radios Bodhisatwa Sadhu, Martin Sturm, Brian M. Sadler, and Ramesh Harjani

ABSTRACT Next generation cognitive radio networks require an RF and mixed signal hardware architecture that can achieve low-energy, very wideband spectrum sensing. We survey state-of-the-art low-power CMOS building blocks as potential candidates for realizing such an architecture. For the critical analog-to-digital converter, we compare time-interleaved and frequency-interleaved architectures, including system-level simulations, and frequency-interleaving is shown to provide significant advantages. Measurement results from a 3.8 mW 5 GHz bandwidth analog domain frequency interleaver are presented to confirm the possibility of a very low-energy frequency domain digitizer. Coupled with DSP for calibration and signal feature extraction, this architecture has significant promise for cognitive spectrum sensing.

INTRODUCTION

Bodhisatwa Sadhu is with the IBM T. J. Watson Research Center. Martin Sturm and Ramesh Harjani are with the University of Minnesota. Brian M. Sadler is with the Army Research Laboratory.

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Increasing cognition in wireless networks has the potential to dramatically enhance network performance and enable multiple networks to coexist. Fundamental to this is the development of an intelligent sensor. While it is possible to task the receiver as a sensor, this takes up resources and may compromise radio functionality, especially because the desired spectrum sensing bandwidth may be dramatically larger than the instantaneous receiver channel bandwidth. Fast broadband spectrum sensing is often needed to enable dynamic spectrum access. Additional functionality is desirable to enhance the cognitive possibilities beyond signal detection, including estimation of signal features, identification of known signal types, and blind modulation classification. Ultimately, it is also desirable to report network features, including medium access control (MAC) characteristics such as spectrum access formats. In this article we describe a mixed-signal approach for an on-chip sensor, with an emphasis on the RF/analog and analog-to-digital conversion portion (Fig. 1), and we contrast this with other more traditional narrowband

0163-6804/14/$25.00 © 2014 IEEE

approaches. The design methodology is focused on low power consumption to enable large-scale deployment in a small form factor. We survey the state-of-the-art component blocks that might satisfy the architectural requirements. Our discussion includes a unique parallel front-end incorporating an analog fast Fourier transform (FFT) channelizer, integration of parallel analog-to-digital converters (ADCs), and coupling with digital signal processing (DSP). As a suitable analog FFT channelizer candidate, hardware results from the Charge Reuse Analog Fourier Transform (CRAFT) implementation [1] are also presented.

COGNITIVE RADIO The idea of revolutionary communications devices, referred to as cognitive radio, was proposed by Joseph Mitola III in 1999 [2] based on the software radio architecture he proposed in 1992. Mitola’s software radio required the entire wideband RF input to be digitized as close to the antenna as possible. Similarly, on the transmit side, the data would be processed and configured in the digital domain and converted to analog just prior to transmission. This would lead to a highly reconfigurable radio with software control. However, the idea proved ahead of its time. Among various challenges, this architecture requires a wideband ADC that could consume on the order of 1 kW of power when designed in a complementary metal oxide semiconductor (CMOS) process [3]. Additionally, to enable cognition of its spectral environment for dynamic spectrum access [4], the cognitive radio would need to perform blind signal detection. This is difficult due to networking and propagation issues such as the hidden terminal problem, multipath fading, and shadowing [4]. With the proliferation of wireless networks and the growing problem of spectral congestion, cognitive radio was soon recognized as a potential panacea for multi-frequency and multi-protocol wireless communications. Moreover, with the scaling of silicon technology auguring a largely digital future, these ideas seemed more

IEEE Communications Magazine • April 2014


ENERGY EFFICIENT SPECTRUM SENSOR Figure 1 shows an example system architecture for a software defined radio (SDR) spectrum sensor. The RF portion comprises a notch filter in the front-end to remove large jammers, a wideband low noise amplifier (LNA), and an automatic gain control (AGC) amplifier. This is followed by a wideband, high speed, high resolution ADC. The ADC can be implemented as a frequency- and/or time-interleaved design (Fig. 1 shows a frequency-interleaved design). The digitized output is then corrected and normalized in the digital domain before further signal detection and classification. These blocks are explained further in this section.

PROGRAMMABLE RF NOTCH FILTERS The wideband input signal to the spectrum sensor may contain large jammer signals. Unlike narrowband radios, these signals fall inside the receiver bandwidth and threaten to saturate the RF front-end and the ADC. In many cases these signals have properties that are known a priori (friendly jammers). As a result, front-end filters with programmable notches can be used to eliminate such blockers. Moreover, once unknown jammer frequencies are estimated (despite frontend saturation), the front-end notch filter can be tuned to reduce their impact. Recently, filters inspired by the N-path concept that translate a DC impedance to a high frequency using mixing have been proposed [6]. Using an extension of this technique, a low Q high-pass filter can be used to design a high Q RF notch filter, the notch frequency of which is regulated by the mixer local oscillator (LO) frequency. Since this technique primarily relies on switches, scaled CMOS technologies are suit-


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practicable. As shown in Fig. 2, which plots the number of IEEE publications in a particular area of research since 2000, cognitive radio research picked up around 2004 after five years in dormancy, and has seen exponential growth ever since. In fact, cognitive radios as a research topic is now more common than even VLSI and DSP. Most of the initial research effort on cognitive radio hardware focused on trying to bridge the gap between a truly wideband software radio type solution and the traditional narrowband heterodyne radio architectures. As a result, a number of wide-tuning but narrowband approaches emerged [5]. While this is sufficient to achieve signaling in a cognitive radio, the spectrum sensing challenge was not fully addressed. However, with the persistent research thrust on reconfigurable and energy-efficient on-chip analog/RF, the technology (especially CMOS) is maturing to a point where the Mitola architecture is coming closer to being realized. In the following sections, we explore practicable manifestations of the Mitola type receiver. We consider the spectrum sensing system architecture, and focus on various energy-efficient CMOSbased analog/RF blocks that make this feasible.

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Figure 1. An envisioned wideband spectrum sensing architecture that achieves spectrum sensing functionality similar to Mitola’s visionary software radio concept. able. The phase noise of the LO used for frequency translation remains critical for jammer rejection. Techniques to achieve low phase noise in scaled CMOS technologies are discussed later in this section.

LNA Unlike traditional narrowband architectures, spectrum sensing requires a wideband LNA that ideally does not use tuned elements [7]. The LNA circuits are based on MOS transistors and resistors (broadband elements) but typically suffer from a noise figure higher than 5 dB when power matched at the input. Such a high noise figure does not satisfy the stringent requirements of an SDR. Using global feedback improves the noise figure, but at the expense of stability. Noise canceling schemes have been proposed to improve the noise figure below 2.5 dB for wideband architectures [8] and are a promising candidate for SDRs. However, wideband architectures provide little suppression for out-of-band blockers. Consequently, their broad input bandwidth increases the linearity requirements significantly.1

AUTOMATIC GAIN CONTROL Due to the large dynamic range of RF input signal levels that need to be accommodated, the signal selection block is followed by a set of variable gain amplifiers (VGAs) [9], realizing automatic gain control (AGC). The signal selection block is realized as a low pass filter in broadband systems. The VGA amplifies the input signal to fill the full-scale input range of the ADCs, enabling small signals to be digitized with maximum resolution. Traditionally, AGCs were implemented as all-analog blocks, but increasingly they are realized as mixed signal blocks, where the VGA is still analog but the signal level detection is achieved via a combination of analog and digital circuits [10]. A wideband VGA with a large dynamic range is desirable. With the increasing transit frequency (f T ) with CMOS technology scaling, larger bandwidths are becoming feasible. However, achieving large dynamic range in the face of a shrinking supply voltage remains extremely challenging.

1 Mixer first designs, where the LNA is completely eliminated and the RF signal is applied directly to a passive mixer, provide higher linearity and the ability to handle large out-of-band jammers because they can be removed before amplification. The current state of the art is focused on narrowband systems, although this architecture has some promise for broadband systems.

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FREQUENCY SYNTHESIZER The accuracy of the notch filter and the ADC sampler are limited by clock jitter. For instance, a 10 Gsamples/s 10-bit ADC requires a clock with a root mean square (rms) jitter of less than ~30 femtoseconds, which is 3–4× lower than current state-of-the-art CMOS frequency synthesizers. The phase noise of frequency synthesizers is mainly limited by that of the voltage controlled oscillator (VCO) at medium and large offsets. Unfortunately, with technology scaling, the supply voltage has been reduced, making it difficult to obtain a large voltage swing and therefore low phase noise. Recently, device linearization and decoupling techniques have been shown to improve the voltage swing even in scaled CMOS technologies providing good on-chip jitter performance of ~70 femtoseconds [11]. The VCO is housed within a phase locked loop (PLL) for reliable frequency generation. For spectrum sensing applications, digital or hybrid architectures have become popular, replacing traditional analog PLLs. These architectures allow improved reconfigurability, and enable the benefits from CMOS technology scaling.

DIGITIZER The digitizer is a principal component of the SDR receiver architecture. In fact, the rest of the receiver front-end is built to facilitate the ADC. While the notch filter reduces the ADC dynamic range significantly, the large bandwidth contains well-spread signals of moderate amplitudes. The sum total of these signals can result in a large peak-to-average power ratio in the time domain, and consequently require a large ADC dynamic range [1]. A prime example of this occurs with orthogonal frequency-division multiplexing (OFDM) multi-carrier transmission, composed of a sum of randomly phased equalamplitude carriers. Through a central limit theorem effect, the time domain signal will tend to

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follow a Gaussian distribution, with significant excursions in amplitude. Progress on wideband architectures has seen a steady improvement in ADC speed and resolution (~2× in four years [12]). As a result, some promising architectures that can target Mitolatype receivers have evolved [12].

TIME-INTERLEAVED ADC In this architecture, as shown in Fig. 3a, the input signal is sampled at a rate of f s following which the samples are interleaved in time into N different streams. Each sample stream is now at a lower sampling rate of fs/N and is digitized by a sub-ADC. The digitized sub-ADC outputs are de-interleaved to reconstruct the full sample rate in the digital domain. Time-interleaving (TI) reduces the speed requirements of the sub-ADCs by N, and is a popular high-speed architecture [12]. However, the dynamic range and the sampler bandwidth requirements of the sub-ADCs remain high. In a TI-ADC, each of the sub-ADCs still requires an input dynamic range matched to the full wideband signal. For example, consider a 10 Gsamples/s 10 bit effective number of bits (ENOB) ADC digitizing an input with a 4 GHz bandwidth. Even if the samples are interleaved in time by N, each sub-ADC still needs to have a 10 bit ENOB. Similarly, the sampler input bandwidth is unaltered. In its simplest form, a sampler comprises a transistor switch (on-resistance, R on ) sampling onto a capacitor (C). The input bandwidth of the sampler is determined by the wp = 1/(RonC) pole of this sampler. For a 4 GHz bandwidth input signal, the sampler bandwidth should be at least ~10–15 GHz to allow for sufficient settling and to reduce the impact of nonlinear switch resistance. While time-interleaving increases the time between samples for each sub-ADC, the sampler on-period is still t on = 1/(4 GHz); therefore, the sampler bandwidth requirement (wp) is not relaxed. The large bandwidth necessitates a lower capacitance at the



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Figure 3. Time-interleaved and frequency-interleaved ADC architectures (top), and two types of frequency-interleaved ADC architectures, continuous-time (CT) and discrete-time (DT) (bottom). cost of noise and other analog circuit nonidealities or a smaller resistance at the cost of a large nonlinear switch parasitic capacitance. Fortunately, CMOS technology scaling has provided vastly improved switch performance by improving the on-resistance and reducing their parasitic capacitance. This has enabled high-resolution samplers in modern scaled technologies [1]. Despite the dynamic range and bandwidth limitations, TI-ADCs theoretically enable high resolution by increasing the sub-ADC count. In practice, however, TI-ADC resolution is limited by matched routing between the sub-ADCs.

FREQUENCY-INTERLEAVED ADC In a frequency-interleaved ADC, the input bandwidth is divided in frequency, and each frequency band is digitized by a sub-ADC (Fig. 3b). The overall desired time samples are then reconstructed in the digital domain. In contrast to time-interleaving, the dynamic range of each sub-ADC is proportionally reduced by frequency channelization. In effect, for an interleave-by-N design, each sub-ADC not only runs at 1/N of the total speed, but also sees only 1/N of the total input bandwidth. For well spread signals, this approximates to only 1/N of the total dynamic range. Therefore, for our earlier example of a 10 Gsamples/s 10 bit ENOB ADC with a 4 GHz input bandwidth, an interleave-by-16 design reduces the input bandwidth of each sub-ADC to 250 MHz. Moreover, for spread signals, the dynamic range, and therefore the ENOB requirement for each of these ADCs, is reduced by log2(16) = 4 by using a 4-bit VGA (gain steps from 1–16×). As a result, the sub-ADCs need to handle an input of only 250 MHz with an ENOB of 6 bits to implement a 10 GHz 10 bit ENOB digitizer! Note that frequency channelization reduces


the output amplitude (as well as the dynamic range) for each channel. For kT/C noise limited ADCs, the LSB is fixed. Therefore, in order to exploit the dynamic range reduction, a VGA/AGC is required to fill each sub-ADC input range. These VGAs are shown in the architecture diagram in Fig. 1. The sampler input bandwidth requirements for a frequency-interleaved design depends on whether it is implemented prior to or after frequency-interleaving. If the frequency-interleaving is implemented in the continuous time domain, the samplers are implemented after frequency-interleaving, one per frequency channel. These samplers now see only 1/N of the input bandwidth of the ADC, greatly reducing the input bandwidth requirement. If the frequencyinterleaver is implemented in the discrete time domain, the sampler needs to be implemented prior to frequency-interleaving, and sees the full input bandwidth. These two categories of frequency-interleaved ADCs with their relative advantages and disadvantages are discussed below. Continuous-Time Frequency-Interleaved ADC — An N-path filter can be implemented in the continuous time domain followed by samplers and sub-ADCs. One technique to achieve this uses a filter-bank approach, as shown in Fig. 3c.2 This architecture achieves an N-path filter using an array of mixers and low pass filters [13]. The filters are followed by samplers for each sub-ADC. This reduces the sampler input bandwidth requirements for each sub-ADC by N. The clock jitter requirements for the sampling clock are also relaxed. Moreover, due to the frequency channelization, the dynamic range requirements for each sub-ADC are reduced. While this architecture reduces the sub-ADC

2 Note that, in principle, a continuous time N-path filter can be implemented by other techniques as well, although these generally do not lend themselves well to an analog implementation and are not easily programmable. Therefore, only the filterbank approach is discussed in this survey.

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Being completely passive, the discrete time processor consumes negligible power. For example, the CRAFT design, shown to achieve 7bit resolution 16point FFT for a 5 GHz input signal bandwidth in 65 nm CMOS, consumes only 3.8 mW power at full rate.

and sampler requirements, it shifts the problem to the design of the frequency-interleaver. The mixers in this architecture see a large bandwidth and require a large dynamic range[1]. In order to reduce the problem of harmonic mixing that typically plagues such wideband systems, harmonic reject mixers can be used [14]. Despite this, the dynamic range is limited to only about 7 bits. Also, multiple LO frequencies with adequate phase noise performance need to be generated and routed to the interleaver. All frequency-interleaved channels need to be well matched. Due to their on-chip proximity, the coupling of the LO frequencies from one channel to the next limits channel-to-channel isolation and reduces dynamic range. Consequently, to obtain the best performance from the interleaver requires significant power and large area consumption. Moreover, being composed of analog blocks, it is not expected to respond well to technology scaling. Note also that the DSP needs to de-interleave the sub-ADC outputs in order to provide the full rate signal samples. For the continuous time filter-bank approach, reconstruction involves accurate modeling of the filter bank. Being composed of analog components subject to process variation, accurate reconstruction requires complex digital calibration and correction techniques. Running at full rate, such correction techniques are expected to consume significant power in DSP. Discrete-Time Frequency-Interleaved ADC — As shown in Fig. 3d, this architecture samples the signal and uses discrete time signal processing to achieve an N-path filter. A convenient Npath filter can be implemented using a time to frequency domain transform or a discrete Fourier transform (DFT) [1]. In this architecture, the sampler is identical to that used in the time domain interleaving architecture. Therefore, the sampler input bandwidth requirements are not relaxed. After sampling, the samples are manipulated using passive-charge-based operations that add or scale charges on the input capacitors. At the end of these manipulations, the voltages on these capacitors represent FFT outputs. As a result, the original time-interleaved samples are now transformed into frequency-interleaved samples that feed into the sub-ADCs. The discrete time Fourier transform approach has the advantage of being suitable for scaled technologies. As discussed above, due to the rapid improvement of switches with CMOS technology scaling, high-speed high-resolution samplers are becoming feasible. Moreover, the discrete time processing block primarily comprises switches and capacitors; as a result, performance is also expected to improve with process scaling. Being completely passive, the discrete time processor consumes negligible power. For example, the CRAFT design, shown to achieve 7-bit resolution 16 point FFT for a 5 GHz input signal bandwidth in 65 nm CMOS, consumes only 3.8 mW power at full rate [1]. A linear transformation such as the DFT has the additional advantage of allowing easy reconstruction in the digital domain. Optimized IFFT imple-

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mentations can be utilized for high-speed lowpower digital reconstruction. Moreover, capacitor mismatch errors in the discrete time processor show up as linear errors in the FFT and can be corrected relatively easily. In fact, the IFFT can incorporate the correction using slightly modified coefficients in the IFFT calculation, enabling IFFT and digital calibration to be merged into a single operation. Moreover, orthogonality between the channels helps by limiting cross-channel noise correlation and scaling offsets. Note that the passive implementation causes signal attenuation during processing, which affects the noise figure. Sufficient gain in the front-end LNA and AGC ensures that this does not affect the overall receiver noise figure.

DIGITAL SIGNAL PROCESSING The mixed-signal analog and sampling portion is preparation for the DSP that follows. We stress that analog/digital co-design offers significant advantages in throughput, power reduction, and adaptation. In almost any mixed-signal design, it is also important to include calibration. We can roughly divide the DSP sensor tasks into detection, feature extraction, and classification [15]. Detection may amount to thresholded spectrum estimation, and the DSP will almost surely include a DFT for further fine-grained spectrum resolution. If the signal format or significant features of the signal are known a priori, this can be exploited through known pilot symbols, network identifiers, and authentication mechanisms. The range of possibilities runs from verifying rough features, such as frequency and time duration, to full demodulation. If only spectrum occupancy is to be determined, pilots or other known features can readily be exploited to detect the signal, without the complexity of equalization, demodulation, or decoding. In a more general setting, when the signal is unknown (the fully blind problem) or perhaps restricted to a known set of signal types, the DSP is more challenging. Detection can be difficult at lower signal-to-noise ratio (SNR), and different signal types may require different types of processing (e.g., detection of a direct sequence spread spectrum signal as compared to a multicarrier signal). Each of these may require a dedicated detection algorithm. Generally, detection of known signal types is simpler and has better performance than detection with more a priori uncertainty. Modulation classification is often of interest to identify the user or network. This problem is particularly challenging in the wideband case when multipath fading is present, because of the presumed need for a blind equalizer. Statistical tests built on cumulants or cyclic features may be employed, which are less complex than a full acquisition step before mod-class, but these generally require larger data size, and their performance can be conditional on first obtaining good estimates of basic features such as the carrier frequency and bandwidth. For a detailed discussion of these and related issues, such as resampling and DSP complexity vs. performance trade-offs, see [15]. Also, as discussed earlier, digital calibration



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Figure 4. The system architecture simulated using MATLAB® Simulink contrasting frequency- and time-interleaved ADC approaches.

for analog imperfections needs to be incorporated into the DSP.

SIMULATIONS AND MEASUREMENT SYSTEM-LEVEL SIMULATIONS System-level behavioral simulations in Matlab Simulink were performed to demonstrate the effectiveness of the frequency-interleaved technique. The simulation setup is shown in Fig. 4. The setup comprises a direct conversion receiver with a wideband intermediate frequency (IF). The LNA gain is 20 dB, and the system noise figure is set at 6 dB. The wideband IF includes a low-pass filter and an AGC. The AGC ensures that the digitization process always sees a full bandwidth maximum input signal of 2 V peakto-peak (Vpp). The I/Q outputs of the IF are digitized using the two interleaving techniques, FFT-based frequency interleaving and traditional time domain interleaving. The resolution for both sets of sub-ADCs are maintained at 6 bits for an apples-to-apples comparison. A lower resolution of 6 bits and a reasonably low system noise figure is maintained for visual clarity so that the effects of the digitization process are dominant. For all simulations, the ADCs are assumed to be ideal (i.e., ENOB = 6 bits and no integral nonlinearity/differential nonlinearity (INL/DNL). For the frequency interleaved ADC, the output of the IF stage is followed by an 8-point analog discrete time FFT. The output of each FFT is then amplified using an additional VGA, and input to 6-bit sub-ADCs. The VGA ensures that the input to the sub-


ADCs occupies the ADC full-scale. A digital IFFT is performed on the ADC outputs to reconstruct the original signal. The system can now be tested with a variety of input waveforms to evaluate its performance. For the time interleaved ADC, the IF output is fed directly to separate (I/Q) time-interleaved 6-bit ADCs. The left side of Fig. 5 shows the two interleaved ADC topologies being considered. In this example simulation, we use a typical scenario where a small signal needs to be detected amid many medium-sized blockers (about 50 dB larger than the signal). For a dynamic spectrum access application, this level of detection in the presence of blockers largely ensures that the spectrum sensor does not falsely identify spectrum holes and interfere with primary user communications. The top right side of this figure shows highresolution power spectral density plots for the signals reconstructed at the output of the two different interleaved ADCs, with green for timeinterleaved and blue for frequency-interleaved. As expected, the quantization noise for the timeinterleaved ADC (or any sufficiently fast single ADC) is white and frequency-independent. In contrast, the quantization noise for the frequency-interleaved ADC is colored. The ADC functions by channelizing the signal in frequency and dynamically amplifying each channel to fill the sub-ADC range. For example, when the signal output from a particular frequency channel is small, the VGA that follows the FFT increases the signal level to fill the sub-ADC input range. The output of the ADC is then reduced by the inverse of this gain before being stitched togeth-

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er by the IFFT. The VGA gains are assumed to be controlled by the DSP (not shown in the figure). The gains for the individual VGAs before the sub-ADCs are shown in the bottom right corner of Fig. 5. As shown, the gains corresponding to the second and third bins of the FFT are largest, corresponding to the smallest signals at those frequencies. As a result of the channelization followed by the VGA, the sub-ADC quantization noise in the critical channels (e.g., potential spectrum holes) is suppressed. This allows the small signal in our example to be reliably detected. In contrast, as shown in Fig. 5, detection of this signal is much more challenging for the time-interleaved ADC architecture. As noted earlier, we have used the discrete time FFT as a frequency channelizer that does not provide a “brick-wall” characteristic per bin, but has a sinc filter rolloff. However, this finite rolloff allows the FFT to provide spreading, which improves blocker rejection through dithering of the individual sub-ADCs input. No information is lost due to spreading as the IFFT theoretically reconstructs the signal perfectly. Spreading is detrimental only when we want to shut out a particular bin to improve power efficiency, in which case the brick-wall filter approach provides better filtering.

CRAFT MEASUREMENT RESULTS As discussed above, the time-to-frequency domain conversion is a challenging aspect of the frequency-interleaved ADC architecture. In this section, we discuss the implementation and measured performance of a prototype analog domain

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FFT example that might be used in this context. The Charge Reuse Analog Fourier Transform (CRAFT) design is based on a pseudo-differential passive switched capacitor network in order to achieve higher linearity while consuming minimal power. The design first samples the signal on capacitors, thereby converting it from the continuous time domain into the discrete time analog domain. The sampled charge on these capacitors are shared with each other in a specific order using switches. Note that the DFT is a linear operation comprising addition operations and multiplication with fixed operands. Consequently, charge sharing can be used to implement both these operations. After the charge sharing operations, the manipulated charge on each capacitor represents discrete outputs of an FFT. Further implementation details of the CRAFT circuit are provided in [1]. After sampling, the only power dissipated by this circuit is in operating the switches of the switched capacitor network. As a result, very low power dissipation can be achieved. Moreover, the speed of operations is limited only by the RC settling time of the switched capacitors enabling very fast time-to-frequency transformation. Additionally, unlike many other analog blocks, both the switching speed and power dissipation are expected to improve with CMOS technology scaling. While passive switched capacitor processing helps to reduce the power and increase operation speed, the circuit also becomes more vulnerable to typical analog-switched capacitor nonidealities such as noise, incomplete settling,



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Figure 6. IBM 65 nm CMOS die photo of the CRAFT test site IC (left) and results from a one-tone test showing single-tone outputs on bin 1 across varying amplitudes (right). charge injection, and clock feedthrough. In the CRAFT implementation, novel techniques such as correlated noise cancellation and RF crossconnect (RCX) settling error cancellation were developed to mitigate noise and settling error, respectively, while optimized switching schemes were developed for reducing clock-feedthrough and charge injection, as well as minimizing settling error [1]. A die micrograph of the CRAFT site along with other test structures is shown on the left of Fig. 6. As shown on the right of Fig. 6, for a single-tone input corresponding to the bin 1 frequency, the CRAFT processor outputs show large amplitude on bin 1 and small residual errors on the other bins, as expected. For small input amplitudes, the residues are due to the noise floor of the circuit, while for larger amplitudes, the analog nonlinearities show up on the other bins. Table 1 presents a summary of the measurement results from the first prototype design of the CRAFT circuit in IBM 65 nm CMOS. The circuit operates on a 5 GHz bandwidth signal and performs a 16-point complex-valued FFT providing a 16-fold channelization benefit as discussed earlier. The entire CRAFT processor, excluding the sampler, consumes 3.8 mW of power, achieving a 12.2 pJ/conversion FFT. A signal-to-noise-plus-distortion ratio (SNDR) of 47 dB and spurious free dynamic range (SFDR) of 41 dB (after digital calibration) are obtained corresponding to ~7 bits of digital resolution. The resolution is expected to improve with technology scaling for the same speed of operation.

CONCLUSIONS In this article we explore a hardware architecture that can achieve low energy spectrum sensing using current CMOS technology. The state of research advancement for the various blocks in the architecture is reviewed in the light of CMOS technology scaling trends. The wideband digitizer, arguably the most critical component


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12.2 pJ

Table 1. CRAFT performance summary. of the mixed signal architecture, is discussed in detail, contrasting time-interleaved and frequency-interleaved approaches. These are compared using Matlab® Simulink simulations, and the performance advantage of the frequency-interleaved approach is demonstrated. Measurement results confirm the ability to achieve very-lowpower implementations of the frequency-interleaved approach in future spectrum sensors. Based on this survey of state-of-the-art components and system simulations using these specifications for a very wideband cognitive spectrum sensor, the dream of a Mitola-type cognitive radio architecture is expected to become a reality in the coming decade.

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BIOGRAPHIES B ODHISATWA S ADHU [S’08, M’12] ([email protected]) is currently a research staff member at IBM T. J. Watson Research Center, New York. He received his B.E. (Hons.) degree from Birla Institute of Technology and Science, Pilani, India, in 2007, and his Ph.D. degree from the University of Minnesota, Minneapolis, in 2012, both in electrical engineering. He is the recipient of the University of Minnesota Graduate School Fellowship, 2007, 3M Science and Technology Fellowship, 2009, and the University of Minnesota Doctoral Dissertation Fellowship, 2011. M ARTIN S TURM [S’11, M’13] received his B.S. and Ph.D. degrees in electrical engineering in 2006 and 2013 from the University of Minnesota, Minneapolis. For his Ph.D., he worked on passive switched-capacitor circuits for wideband radio. He is currently a post-doctoral researcher at the University of Minnesota, where his research includes passive charge-domain processing for high dynamic range sensing and digitization. B RIAN M. S ADLER [S’81, M’81, SM’02, F’07] is a Fellow of the Army Research Laboratory (ARL) in Adelphi, Maryland. He received Best Paper Awards from the IEEE Signal Processing Society in 2006 and 2010, and has received several ARL and Army R&D awards. His research interests include information science, networked and autonomous systems, sensing, and mixed-signal integrated circuit architectures. R AMESH H ARJANI [S’87, M’89, SM’00, F’05] is the Edgar F. Johnson Professor in the Department of Electrical and Computer Engineering at the University of Minnesota. He received his Ph.D. degree from Carnegie Mellon University in 1989. He co-founded Bermai, Inc., a CMOS wireless multimedia startup in 2001. He has been a visiting professor at Lucent Bell Labs, Allentown, Pennsylvania, and the Army Research Laboratory. His research interests include analog/RF circuits for wired and wireless communications.
