Built-in Jitter Measurement Circuit With Calibration ... - Semantic Scholar

IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 19, NO. 8, AUGUST 2011

1325

Built-in Jitter Measurement Circuit With Calibration Techniques for a 3-GHz Clock Generator Kuo-Hsing Cheng, Member, IEEE, Jen-Chieh Liu, Student Member, IEEE, Chih-Yu Chang, Shu-Yu Jiang, and Kai-Wei Hong

Abstract—This paper proposes a 3-GHz built-in jitter measurement (BIJM) circuit to measure clock jitter on high-speed transceivers and system-on-chip (SoC) systems. The proposed BIJM circuit adopts a high timing resolution and self-calibration techniques. To eliminate process variation effects in 3 GHz systems, this study proposes an auto-calibration technique for the self-refereed circuit and other calibration techniques for the time amplifier (TA) and vernier ring oscillator (VRO), respectively. These calibration techniques can reduce the timing resolution variation of the vernier ring oscillator and the gain variation of the TA by 66% and 65%, respectively. This reduces the timing resolution variation of BIJM by 60%. Because the vernier ring oscillator and time amplifier achieve a small timing resolution, the BIJM circuit does not need an additional jitter-free reference signal using the self-refereed circuit. This study fabricated the BIJM circuit using the UMC 90-nm CMOS process. The BIJM circuit has a power consumption measuring 11.4 mW, and its core area is 120 m 320 m. The BIJM circuit measured the Gaussian distribution jitter at a 1.8 ps timing resolution with a 3-GHz input clock frequency. Index Terms—Auto-calibration, built-in jitter measurement (BIJM), measurement error, time amplifier, vernier ring oscillator (VRO).

I. INTRODUCTION

I

NCREASING demand for data processing is driving the demand for high-speed serial links on system chips. These links may connect memory, network, or graphic devices. High-speed serial link transceivers build links to other devices. Researchers have proposed many designs for highly integrated system-on-chip (SoC) devices with high-speed serial link transceivers [1], [2]. In a serial link transceiver, these clocks are typically based on phase-locked loop (PLL) or delay-locked loop (DLL). PLLs and DLLs multiply a low-speed reference signal to a specified frequency. Unfortunately, PLL or DLL may generate power supply noise and introduces the timing jitter into the specified frequency. Timing jitter consists of timing shift or variation in clock signals, and can cause the Manuscript received August 27, 2009; revised March 17, 2010; accepted May 13, 2010. Date of publication June 28, 2010; date of current version July 27, 2011. This work was supported by National Science Council, Taiwan, under Grant NSC 96-2221-E-008-111-MY3. K.-H. Cheng, J.-C. Liu, and K.-W. Hong are with the MSIC Laboratory, Department of Electrical Engineering, National Central University, Taoyuan 32001, Taiwan (e-mail: [email protected]; [email protected]. tw; [email protected]). C.-Y. Chang is with Elan Microelectronics Corporation, Hsinchu 300, Taiwan. S.-Y. Jiang is with Acer Incorporated, Taipei 10479, Taiwan. Digital Object Identifier 10.1109/TVLSI.2010.2052377

Fig. 1. BIJM circuit with calibration technique.

received data to fall outside the design boundary. A high-speed serial link transceiver is important to analyze these effects of the clock jitter. Fig. 1 presents a built-in jitter measurement (BIJM) circuit capable of measuring clock jitter. The BIJM circuit is a very popular system for analysing clock jitter. Traditional clock jitter analyzers include automatic test equipment (ATE), a real-time sampling oscilloscope, and dedicated jitter instrumentation [3]. However, increasing clock frequencies make instrument-based clock jitter measurements more difficult. Researchers have developed many BIJM methods to measure on-chip signal jitter distribution for this constraint [4]–[12]. However, the timing resolution of BIJM is not easy to determine, because all the information on the test chips. Obtaining the timing resolution of BIJM is very useful for jitter measurement circuit. Unfortunately, process variation is an important factor in multi-gigahertz systems. Therefore, it is necessary to determine the timing resolution of BIJM and calibration techniques. The adjustable delay line (DL) structure of a BIJM circuit employs non-inverting logic gates [5]. Although DL structures can measure PLL clock jitter, the delay time of DL limits the timing resolution. The proposed BIJM circuit uses a vernier delay line (VDL) to eliminate the timing resolution requirements [6]. The VDL structure employs the timing difference between delay cells, and digitizes the tested signal jitter. Although the VDL structure increases the timing resolution of BIJM, it requires twice the area. Therefore, the proposed design adopts a vernier ring oscillator (VRO) structure to reduce the area [7]. VRO uses the timing difference between oscillators to digitize tested signal jitter. However, the testing time is increased obviously. For narrow time interval measurements, previous research proposes a BIJM circuit amplified by a DLL-based TA report in [12]. A time-to-digital converter (TDC) uses the time amplifier (TA) to extend the timing resolution [13]. The TA-based TDCs are useful for all digital PLL applications [14], [15]. This work proposes a 1.8 ps timing resolution BIJM for a 3 GHz serial advanced technology attachment-II (SATA-II) and SoC applications. The proposed design offers three benefits.

1063-8210/$26.00 © 2010 IEEE

1326


Fig. 2. Block diagram of the architecture of the proposed BIJM.

TABLE I SPECIFICATIONS OF BIJM FOR SATA-II AND SOC SYSTEM

A. Jitter Analysis for SATA-II The following section describes the specifications of for a SATA-II. (1) shows that the RMS jitter is 4.3 ps ( projection) at 3 GHz [17] 4.3 ps.

(1)

Therefore, the peak-to-peak jitter is 25.8 ps (6 4.3 ps), and the measurement resolution is 3.3 ps (1% UI) for BIJM. The worst case of the jitter measurement range for a BIJM circuit is 60.2 ps (14 4.3 ps). First, auto-calibration and calibration techniques in the self-refereed circuit, time amplifier circuit, and VRO reduce process effects. TA and VRO are particularly sensitive circuits in a BIJM circuit. The proposed calibration techniques are useful for TA and VRO. Second, the TA structure increases the timing resolution. For 3 GHz systems, the timing difference is small. Using a TA can increase the timing resolution of BIJM. Finally, VRO can reduce the area cost much more than a traditional delay line. These three benefits ensure the success of implementing a 3 GHz BIJM in a serial-link transceiver. The rest of this paper is organized as follows. Section II introduces BIJM specifications for SATA-II and SoC applications. Section III explains the architecture of the proposed BIJM and discusses measurement errors. Section IV addresses circuit implementation Section V presents experimental results. Finally, Section VI provides conclusions. II. DESIGN FOR SATA-II AND SOC SYSTEM Most companies require their gigahertz signal pins to deliver less than one BER in 10 bits, but some companies are now or better. For jitter to have a Gaussian claiming a BER of 10 probability distribution function (PDF), the peak-to-peak value , 68%, of the must be less than two standard deviations time. The standard deviation is also the RMS jitter. The 10 BER specification corresponds to . Thus, the peak-to-peak value of jitter is much less than 14 times of its RMS value. In general, the peak-to-peak jitter is approximately 6 to 14 times the RMS jitter. Hence, to keep BER less than 10 , measurement accuracy must be less than 1% of a unit interval (UI) [15].

B. SoC Jitter Analysis Table I shows the specifications of BIJM for SATA-II and SoC systems. For a 3-GHz PLL or a clock generator on SoC systems, the peak-to-peak jitter must be less than 5% of the clock period. This equals a peak-to-peak value of less than 16.7 ps (0.05 333 ps) in a 3 GHz system. The RMS jitter is one-sixth of the peak-to-peak jitter, and the value of RMS jitter is around 2.8 ps. Thus, the BIJM timing resolution must be less than 2.8 ps. The worst case of the jitter measurement for a BIJM circuit is 39.2 ps (14 2.8 ps). III. ARCHITECTURE DESCRIPTION Fig. 2 presents a block diagram of proposed BIJM, which consists of two modes: the pre-procedure mode and jitter measurement mode. The pre-procedure mode consists of a self-refereed circuit with the auto-calibration technique, and TA and VRO with the calibration techniques, respectively. A self-refereed circuit, a TA, a VRO, and a write/read (W/R) counter control the jitter measurement mode. Fig. 3 shows the BIJM timing diagram. and signals control the operation of BIJM into the pre-procedure or the jitter measurement modes. In the jitter and are the input measurement mode, signals of the time amplifier and VRO circuit, respectively. The following two operations are the jitter measurement procedure. A. Pre-Procedure Mode Fig. 4 shows the flowchart of pre-procedure mode. The preprocedure mode includes an auto-calibration circuit and two

CHENG et al.: BUILT-IN JITTER MEASUREMENT CIRCUIT WITH CALIBRATION TECHNIQUES FOR A 3-GHZ CLOCK GENERATOR

1327

Fig. 3. Timing diagram of the jitter measurement mode.

Fig. 4. Flowchart of the pre-procedure mode.

calibration circuits. To make sure that the self-refereed circuit can delay one time period in an external environment affected by noise, temperature and process, the auto-calibration circuit . The time amplifier gain corrects one period delay time and the timing resolution of VRO easily change with process variations. Thus, BIJM is necessary to calibrate and . In the proposed BIJM, the is 5 and is 10 ps. The calibration circuit can correct and to obtain a total timing resolution equal to 2 ps.

directly proportional to the measurement error. The measurement error of the self-refereed circuit primarily comes from the supply noise. 2) Time Amplifier: The measurement error of TA includes three main factors. First, the gain of TA amplifies both the measured timing pulse and the measurement error from the supply noise. Second, the linearity of TA gain is an important factor in measurement error. Different timing pulses may have different TA gains. Finally, TA adopts a differential pair to amplify the timing difference, since device mismatch and layout style produce the measurement error. The linearity, device mismatch, and layout style all increase the measurement error. 3) VRO: The VRO timing resolution adjusts according to the frequencies between the two ring oscillators. The supply noise and timing jitter of ring oscillator cause the varying timing resolution in the VRO and produce measurement error. If the timing jitters of the ring oscillators are larger than the VRO timing resolution, the timing jitter will influence the measured timing resolution. Thus, the VRO timing resolution must be larger than the timing jitter of the ring oscillators. 4) Timing Resolution of BIJM: The pre-procedure mode measures the BIJM timing resolution. The delay time of the inverter and the timing resolution of the VRO and the TA gain induce the timing error for each measured data. Section V discusses these measurement errors. By analysing the measurement error, the equation of BIJM output with measurement errors can be expressed as

(2)

B. Jitter Measurement Mode Fig. 3 shows the timing diagram of the jitter measurement and mode. The self-refereed circuit creates two signals ( ) from the reference signal . The difference of delay time between and is one clock cycle. The and . For example, time amplifier then magnifies and the time difference between second rising edge of is , and the timing difference first rising edge of of the time amplifier output signals ( and ) is . The VRO and W/R counter count the TA output signals. This method measures the jitter value of the reference signal in a histogram. C. Measurement Error Analysis The measurement error sources include the following. 1) Self-Refereed Circuit: The self-refereed circuit only gives the delay time for the BIJM circuit. Since the self-refereed circuit produces a constant delay time, the self-refereed circuit is

where is the varying delay time of self-refereed circuit is the variation in TA gain. The term repreand sents the varying VRO timing resolution. and have 20% toleration in BIJM, Suppose that as shown Fig. 5. The error ratio is almost constant when the is increasing. timing difference IV. CIRCUIT IMPLEMENTATION A. Self-Refereed Circuit With an Auto-Calibration Circuit Traditional jitter measurement methods, such as vernier delay line and vernier ring oscillator, require a jitter-free reference clock. A self-refereed circuit [8], it can solve this problem, but the delay chain is very sensitive to process variation. Hence, this study proposes an auto-calibration technique for the cell delay of the self-refereed circuit to reduce process variations. When

1328


Fig. 7. Block diagram of the auto-calibration circuit.

Fig. 5. BIJM measurement error with varying timing resolution.

Fig. 8. Simulated results of the auto-calibration circuit.

Fig. 6. Block diagram of the self-refereed circuit.

the timing difference, in Fig. 3, is large and is offset timing value. BIJM wastes the digital output codes for this offset timing value. Fig. 6 presents the block diagrams of self-refereed circuit, which operates at a 3-GHz output frequency. Fig. 7 shows the block diagram of auto-calibration circuit, which consists of a phase comparator, a divider, a 5-bit up/down counter, a DFF, and a NOR gate. The phase comparator detects and . If leads , the the phase difference between digital-controlled varactor increases the capacitor loading. Otherwise, it decreases the capacitor of loading. When the phase difference is smaller than the comparator window, Lock is high, and the auto-calibration is complete. The auto-calibration circuit alters the delay time of delay cell in the pre-procedure mode. The digital-controlled varactor maintains one period delay time in the jitter measurement with the digital code mode. Fig. 8 shows the results for simulation environment with varying temperature and process. Without auto-calibration circuit, the delay time of the delay cell is easily varying by corner environments. However, calibrating the delay cell synchronizes and increases the accuracy in the jitter the delay time to measurement mode. B. Time Amplifier With a Calibration Circuit Fig. 9 shows the schematic of time amplifier circuit [19]. The BIJM circuit employs a time amplifier for high timing resoluof self-refereed outputs ( tion. The time difference and ) is very small. Thus, with the time amplifier, the time difference between and can increase to

Fig. 9. Schematic of the time amplifier circuit.

. In Fig. 9, M1 turns on when the rising edge of arrives at the input of M1. Thus, is low and is high. is still low, and and keep the preturns on, is low and is vious state. When high. The resistor and capacitor effects of output loading inand . Therefore, crease the time difference between increases and the gain of the small input time difference . Fig. 9 also shows that the latch circuit is time amplifier is the second stage of time amplifier. Fig. 10(a) presents the simulated results of the first stage of the time amplifier, as described in [19]. Thus, the gain of TA is correlated to the loading capacitances of the first stage TA and TA current . is and output the currents of M1 and M3 can control . For the same reason,


1329

Fig. 11. Variation of output time difference with reference frequency varying from 150 to 150 ps.

0

Fig. 10. (a) Voltage waveform at the drain terminals of M1-4. (b) Simulated varying. the gain of TA with C and I Fig. 12. Simulated the TA gain with process variation.

is expressed as

. Thus, the equation of TA gain could be

(3) According to (3), has a direct proportion relationship with . has an inverse proportion relationship with since and depends on . Fig. 10 (b) presents the simulated results of TA gain under varying TA current and loading capacitances. In pre-procedure mode, the calibration circuit corrects the time amplifier. Fig. 11 shows the simulation results. The linearity range of the time amplifier is around 80 ps in the process variations. Calibrating the current source reduces the process effects for the time amplifier in pre-procedure mode. Fig. 12 shows the simulation results of TA gain with process variations. Under these conditions, the gain variation range of TA without a calibration circuit is approximately 1.7, but decreases to 0.6 with a calibration circuit. Thus, a TA calibration circuit can reduce the gain variation range by 65%.

C. VRO With a Calibration Circuit As Fig. 13 shows, VRO can reduce the area cost of the delay cells. The timing resolution is 10 ps at a 3-GHz clock signal

Fig. 13. VRO block diagram.

system. Fig. 14 shows the programmable delay cell designed for tuning delay time. Fig. 14(a) shows the programmable delay . Fig. 14(b) shows cell for low operational frequency the delay cell for high operational frequency . Utilizing two different frequencies of oscillators can obtain a higher timing resolution. The phase detector (PD) and W/R counter when the starts to record the cycle number of signal is low. Once lags behind , the signal is high and W/R counter stops counting the code value. can reduce the process Using calibrating code effects for the timing resolution of VRO.

1330


Fig. 16. (a) Block diagram of the W/R counter. (b) Timing diagram of the W/R counter.

Osc

Fig. 14. Schematic of the delay cell: (a)

; (b)

Osc

.

Fig. 17. Block diagram of calibration circuit. Fig. 15. Simulated the timing resolution of VRO with process variation.

In the pre-procedure mode, the calibration circuit can correct the VRO. Fig. 15 shows the simulation results. The timing resolution variation range of VRO without a calibration circuit is around 15 ps, and decreases to 5 ps with a calibration circuit. Thus, a VRO calibration circuit can reduce the timing resolution variation range by 66% and the simulation results are under the process variations. D. W/R Counter Fig. 16(a) and (b) show the block diagram and timing diagram of the W/R counter. This counter has two modes: write and read modes. When is Low, the W/R counter writes the counted is High, W/R counter reads value from VRO circuit. When the signal by serial type. This technique can reduce can use a low operational frethe area of output pads. and . quency to read E. Calibration Circuit in the Pre-Procedure Mode Fig. 17 shows a block diagram of the calibration circuit. and can control and When Sel is Low,

, as input signals of the time amplifier and VRO, respectively. Thus, the pre-procedure mode measures the time amplifier gain and the VRO timing resolution. The calibration circuit also uses a ring oscillator to define the delay time of . When Sel is high, the ring oscillator the inverter gate uses two MUXs to choose 31- or 35-stage inverters to change and ), and uses a divider to the output frequency ( measure the output signal at low operational frequencies. The signal can control the short path (31-stage) or long path (35-stage) to change the output frequency of the ring oscillator. The delay time of an inverter gate is (4) where and represent the frequency of short path and long path, respectively. When the delay time of an inverter gate is measured, the calibration procedure is toward the next step. As Fig. 17 shows, gives a low-to-high rising edge input signal. The calibration circuit defines the VRO timing resolution , and represents the VRO input signal. The time interval


1331

Fig. 20. Simulated results of the proposed BIJM. (a) Input jitter with uniform distribution. (b) BIJM output jitter probability density function (PDF) with uniform distribution.

Fig. 18. Simulated the timing resolution of BIJM with process variation.

Fig. 19. Simulated the DNL and INL of BIJM.

between and is tenfold the delay time of the from inverter, and the BIJM output shows the result . connects to the VRO inputs. The time interval and is the delay time of ten inverter between . After gates, and the BIJM output obtains the result , can be the previous calculation, the resolution of circuit, written as

(5) When determining and is the input signal of TA. The time interval between and is twice the delay time of the inverter, and the BIJM output from . The gain of the time shows the result amplifier circuit can then be calculated as

Fig. 21. Simulated results of the proposed BIJM. (a) Input jitter with Gaussian distribution. (b) BIJM output jitter PDF with Gaussian distribution.

F. Jitter Histogram in the Jitter Measurement Mode To verify the results of the proposed BIJM in the jitter measurement mode, Fig. 19 shows that the simulated results of DNL and INL with LSB is 1.6 ps. This figure also shows that DNL and INL are 0.6 LSB and 1.6 LSB, respectively. Fig. 20(a) presents the input signal with a uniform distribution. The RMS jitter of input tested signal is 8.51 ps. Fig. 20(b) shows the simulation result of proposed BIJM circuit. Measuring the uniform distributed jitter histogram shows that the RMS jitter is 7.72 ps. Fig. 21(a) presents the input signal with a Gaussian distribution. The RMS jitter of the input signal is 4.85 ps. Fig. 21(b) shows the simulated result of BIJM output. The BIJM circuit is distributed as a Gaussian jitter function, and the RMS jitter is 4.71 ps. The BIJM test time using the HSPICE tool is approximately 98.5 ns for each hit. This test time also includes the delay time of the I/O buffer.

(6) V. EXPERIMENTAL RESULTS The total timing resolution of BIJM

is A. Pre-Procure and Jitter Measurement Modes (7)

The BIJM timing resolution can be calibrated by the TA gain and the VRO timing resolution with process variations. In the best case (FF at 0 C), the BIJM timing resolution is 1.5 ps, and 4.0 ps in the worst case (SS at 100 C). The timing resolution variation is 2.5 ps without calibration techniques. Using calibration techniques, the timing variation decreases to 1 ps. Thus, the calibration circuit in Fig. 18 can reduce process effects by 60%.

Fig. 22 shows the die photograph and layout. We fabricated an experimental prototype using the UMC 90-nm CMOS process. The core area is 120 m 320 m. This study evaluated the accuracy of the BIJM circuit by comparing the PC output results with results for jitter transience obtained with an off-chip realtime oscilloscope. Fig. 23 shows the measurement flowchart of the proposed BIJM circuit. In pre-procedure mode, the and are 22.6, 8.7, and 4.8 ps, respectively. In the jitter measurement mode, the input signal of BIJM is 3 GHz with

1332


Fig. 24. Pre-procedure mode: (a) output frequency of the 31-stage ring oscillator (F ) and (b) output frequency of the 35-stage ring oscillator (F ). Fig. 22. Microphotograph and layout of BIJM test chip.

Fig. 25. Measurement results of the timing resolution in the pre-procedure mode.

Fig. 23. Flowchart of measurement for BIJM.

a Gaussian distribution jitter. Recording the data of can obtain the jitter histogram. Fig. 24(a) and (b) show the output frequencies of the 31- and 35-stage ring oscillators. (4) shows that the delay time of inusing a calverter is 22.6 ps in Step 1. Step 2 measures ibration circuit and W/R counter. Measurement results in this is 26. study indicate that Thus, (5) shows that the timing resolution of VRO is 8.7. The calibration circuit and W/R counter measure in is 25. Therefore, (6) shows that Step 3, and the value of is 4.8. According to (7), the total the time amplifier gain timing resolution of the proposed BIJM circuit is 1.8 ps. Fig. 25 shows the timing resolution in the pre-produce mode. By calibrating the timing resolution of VRO and the current of TA , the BIJM timing resolution can

Fig. 26. Measurement result of the proposed BIJM: (a) input jitter with Gaussian distribution and (b) BIJM output jitter PDF with Gaussian distribution.

drop below 2 ps. The timing resolution of chip2 is 2.65 ps when is 01. The calibration circuit shows that the timing


1333

TABLE II PERFORMANCE COMPARISONS

Fig. 28. Performance comparison for operation frequency and measurement error.

Fig. 27. Measurement errors. (a) VRO timing resolution. (b) TA gain.

resolution of chip 2 is 1.96 ps. However, the timing resolution variation decreases 35% in chip2. Fig. 26(a) shows a 4.15 ps RMS jitter and 32.0 ps peak-to-peak jitter in the 3 GHz input signal with a Gaussian distribution. BIJM input signal uses an Agilent 81142A generator to create the input source that mixed an extra sin wave at 1 MHz. Fig. 26(b) presents the jitter histogram of output frequency of BIJM. The RMS jitter and peak-to-peak jitter are 3.78 and 23.4 ps at 1k-hit, respectively. B. Measurement Errors Fig. 27(a) presents the measurement results of VRO measurement error. The BIJM circuit counts the VRO output from 24 to 33 at 65-khits, when the delay time of inverter is 22.6 ps in Step 2. (5) shows that the minimum and maximum timing resolutions of VRO are 6.85 and 9.42 ps, respectively. However,

the mean value of timing resolution is approximately 26. The peak-to-peak jitters of the two ring oscillators and I/O buffer with bonding wires are the main factors produces the measurement error. Fig. 27(b) shows the measurement results of TA measurement error. In Step 3, the TA gain is from 23 to 33 at 94-khits. In the worst case, if the minimum and maximum timing resolutions of VRO are 6.85 and 9.42 ps, the minimum and maximum TA gain are 3.49 and 6.88, respectively. The TA gain variation includes the error sources from VRO, TA and I/O buffer effects in the pre-produce mode. To define the delay time of inverter, the measurement error also cause from the I/O buffer with bonding wire and delay buffer with supply noise. The inverter delay time can induce the time error of inverter. (7) shows that the minimum and maximum BIJM timing resolutions are 1.00 and 2.70 ps, respectively. Table II shows the performance comparisons of the proposed BIJM circuit with conventional BIJM designs [6], [8], [10], [18], [20]–[22]. Fig. 28 compares the operation frequency and measurement error of the proposed BIJM circuit with previously proposed BIJM circuits. The error ratio represents the difference error between the input jitter source and the measured jitter. In the multi-gigahertz operation frequency, the proposed design achieves lower error than other designs. We implemented the proposed BIJM circuit in the UMC 90-nm CMOS process and measured the jitter range from 1.8 to 80 ps at 3 GHz. The core area is 0.038 mm , and the power consumption is 11.4 mW. The proposed architecture employs a time amplifier and VRO to

1334


achieve a total timing resolution of 1.8 ps. The proposed VRO minimizes the area of the delay cell. VI. CONCLUSION This study proposes a 3-GHz BIJM for a serial-link transceiver and SoC system. This study also proposes high timing resolution and calibration techniques. The time amplifier increases the BIJM timing resolution, and the VRO reduces the area of the delay cell. To control process variations, the self-refereed circuit adopts the auto-calibration technique, and the time amplifier and VRO implement other calibration techniques. We verified the performance of these calibration techniques in a test chip. The BIJM timing resolution decreased 60% under process variations. The proposed BIJM circuit utilizes time amplifier and VRO-based techniques to achieve a 1.8 ps timing resolution at 3 GHz. The measurement error is less than 8.9%. The self-refereed circuit creates a reference source to be sampled signal. Thus, the proposed BIJM circuit can measure a 3-GHz input signal without an additional jitter-free clock signal. ACKNOWLEDGMENT The authors would like to thank the United Microelectronics Corporation (UMC) for chip fabrication and S.-H. Chen for his editorial assistance.

[12] R. Rashidzadeh, R. Muscedere, M. Ahmadi, and W. C. Miller, “A delay generation technique for narrow time interval measurement,” IEEE Trans. Instrum. Meas., vol. 58, no. 7, pp. 2245–2252, Jul. 2009. [13] M. Lee and A. A. Abidi, “A 9 b, 1.25 ps resolution coarse-fine time-todigital converter in 90 nm CMOS that amplifies a time residue,” IEEE J. Solid-State Circuits, vol. 43, no. 4, pp. 769–777, Apr. 2008. [14] M. Lee, M. E. Heidari, and A. A. Abidi, “A low-noise wideband digital phase-locked loop based on a coarse-fine time-to-digital converter with subpicosecond resolution,” IEEE J. Solid-State Circuits, vol. 44, no. 10, pp. 2808–2816, Oct. 2009. [15] S.-Y. Lin and S.-I. Liu, “A 1.5 ghz all-digital spread-spectrum clock generator,” IEEE J. Solid-State Circuits, vol. 44, no. 11, pp. 3111–3119, Nov. 2009. [16] S. Sunter and A. Roy, “On-chip digital jitter measurement, from megahertz to gigahertz,” IEEE Des. Test Comput., vol. 21, no. 4, pp. 314–321, Jul.–Aug. 2004. [17] Agilent, “Serial-ATA international organization, Version 1.0RC 2.11” Jan. 2007, pp. 51–52. [18] T. Xia, H. Zheng, J. Li, and A. Ginawi, “Self-refereed on-chip jitter measurement circuit using vernier oscillators,” in Proc. IEEE Comput. Soc. Annu. Symp. VLSI, Tampa, FL, 2005, pp. 218–223. [19] M. Oulmane and G. W. Roberts, “A CMOS time amplifier for femtosecond resolution timing measurement,” in Proc. IEEE Int. Symp. Circuits Syst., 2004, pp. 1416–1420. [20] M. A. Abas, G. Russell, and D. J. Kinniment, “Embedded high-resolution delay measurement system using time amplification,” IEE Proc. Comput. Digit. Tech., vol. 1, no. 2, pp. 77–86, Mar. 2007. [21] J. C. Hsu and C. C. Su, “BIST for measuring clock jitter of chargepump phase-locked loops,” IEEE Trans. Instrum. Meas., vol. 57, no. 2, pp. 276–284, Feb. 2008. [22] K. A. Jenkins, A. P. Jose, and D. F. Heidel, “An on-chip jitter measurement circuit with sub-picosecond resolution,” in Proc. IEEE Euro. Solid-State Circuits Conf., Grenoble, France, 2005, pp. 157–160. [23] N. Abaskharoun and G. W. Roberts, “Circuits for on-chip sub-nanosecond signal capture and characterization,” in Proc. IEEE Conf. Custom Integr. Circuits, San Diego, CA, 2001, pp. 251–254.

REFERENCES [1] J. F. Bulzacchelli, M. Meghelli, S. V. Rylov, W. Rhee, A. V. Rylyakov, H. A. Ainspan, B. D. Parker, M. P. Beakes, A. Chung, T. J. Beukema, P. K. Pepeljugoski, L. Shan, Y. H. Kwark, S. Gowda, and D. J. Friedman, “A 10-Gb/s 5-tap DFE/4-tap FFE transceiver in 90-nm CMOS technology,” IEEE J. Solid-State Circuits, vol. 41, no. 12, pp. 2885–2900, Dec. 2006. [2] V. Balan, J. Caroselli, J. G. Chern, C. Chow, R. Dadi, C. Desai, L. Fang, D. Hsu, P. Joshi, H. Kimura, C. Y. Liu, T. W. Pan, R. Park, C. You, Y. Zeng, E. Zhang, and F. Zhong, “A 4.8–6.4-Gb/s serial link for backplane applications using decision feedback equalization,” IEEE J. Solid-State Circuits, vol. 40, no. 9, pp. 1957–1967, Sep. 2005. [3] B. Kaminska, “BIST means more measurement options for designers,” News EDN, pp. 161–166, Dec. 2000. [4] T. Rahkonen and J. Kostamovaara, “The use of stabilized CMOS delay lines for the digitization of short time intervals,” IEEE J. Solid-State Circuits, vol. 28, no. 8, pp. 887–894, Aug. 1993. [5] S. Sunter and A. Roy, “BIST for phase-locked loops in digital applications,” in Proc. IEEE Int. Test Conf, Atlantic, NJ, 1999, pp. 532–540. [6] A. Chan and G. Roberts, “A jitter characterization system using a component-invariant vernier delay line,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 12, no. 1, pp. 79–95, Jan. 2004. [7] S. Tabatabaei and A. Ivanov, “Embedded timing analysis: A SoC infrastructure,” IEEE Des. Test Comput., vol. 19, no. 3, pp. 22–34, May–Jun. 2002. [8] K. Nose, M. Kajita, and M. Mizuno, “A 1-ps resolution jitter measurement macro using interpolated jitter oversampling,” IEEE J. Solid-State Circuits, vol. 41, no. 12, pp. 2911–2920, Dec. 2006. [9] S.-Y. Jiang, K.-H. Cheng, and P.-Y. Jian, “A 2.5-GHz built-in jitter measurement system in a serial-link transceiver,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 17, no. 12, pp. 1698–1708, Dec. 2009. [10] T. Hashimoto, H. Yamazaki, A. Muramatsu, T. Sato, and A. Inoue, “Time-to-digital converter with vernier delay mismatch compensation for high resolution on-die clock jitter measurement,” in Proc. IEEE Symp. VLSI, Honolulu, HI, 2008, pp. 166–167. [11] R. Rashidzadeh, M. Ahmadi, and W. C. Miller, “An all-digital selfcalibration method for a vernier-based time-to-digital converter,” IEEE Trans. Instrum. Meas., vol. 59, no. 2, pp. 463–469, Feb. 2010.

Kuo-Hsing Cheng (S’89–M’93) was born in Taipei, Taiwan, in 1962. He received the B.S. degree from the Department of Electrical Engineering, National Central University, in 1985, and the M.S. and Ph.D. degrees from the Institute of Electronics Engineering, National Chiao-Tung University, Taiwan, in 1987 and 1992, respectively. During 1987–1992, he studied in the development of high performance digital integrated circuits and systems. During 1992–1993, he was an Associate Researcher with the Chip Implementation Center, Nation Science Council, Taiwan. From 1993 to 2003, he was an Associate Professor with Tamkang University, Taipei, Taiwan. In 2003, he joined the faculty of the National Central University, Chung-Li, Taoyuan, Taiwan. He is currently a Professor with the Department of Electrical Engineering. He has published over 100 IEEE technical papers on integrated circuits. He also has received four patents on integrated circuits. His research interests include LV/LP high-speed mixed-signal integrated circuits and systems, clock synchronization circuits and ultra-high-frequency mixed signal circuits for wire communications.

Jen-Chieh Liu (S’07) was born in I-Lan, Taiwan, Republic of China, in 1981. He received the B.S. and M.S. degree from the Department of Electrical Engineering, Fu-Jen Catholic University, Taipei, Taiwan, in 2004 and 2006, respectively. Currently, he is pursuing the Ph.D. degree in electrical engineering from National Central University, Taiwan. His research interests include all digital PLL, built-in jitter measurement circuits, and low power/low supply voltage for clock synchronization circuit and system. Mr. Liu is a member of Phi Tau Phi honorary scholar society. He is a recipient of the Best Paper Award at the 18th VLSI Design/CAD Symposium, Hualien, Taiwan, in 2006.


Chih-Yu Chang was born in Taipei, Taiwan, Republic of China, in 1983. He received the B.S. degree from the Department of Electrical Engineering, Tamkang University, Taipei, Taiwan, in 2006, and the M.S. degree from National Central University, Taiwan, in 2008. His research interests include PLL and built-in jitter measurement circuits.

Shu-Yu Jiang was born in Changhua, Taiwan, Republic of China, in 1979. He received the B.S. and the M.S. degree from the Department of Electrical Engineering, Tamkang University, Taiwan, in 2001, and 2003, respectively. He is currently pursuing the Ph.D. degree in electrical engineering from National Central University, Taoyuan, Taiwan. In 2006, he joined the Liteon Technology Corporation, Hsinchu, Taiwan. His research interests include PLL, TDC, built-in jitter measurement circuits and high-speed interfaces.

1335

Kai-Wei Hong was born in Taichung, Taiwan, in 1980. He received the B.S. degree from the Department of Electrical Engineering, Feng-Chia University, Taichung, Taiwan, in 2002, and the M.S. degree from the Department of Electronic Engineering and Graduate Institute of Computer and Communication Engineering, National Taipei University of Technology, Taipei, Taiwan, in 2004. Currently, he is pursuing the Ph.D. degree in electrical engineering from National Central University, Taoyuan, Taiwan. His research interests include PLL, DLL, clock synchronization circuits, and high-speed interfaces.