BZK.SAU.FPGA10.1: A Modular Approach to FPGA-Based Micro Computer Architecture Design for Educational Purpose HALIT OZTEKIN,1,2 FEYZULLAH TEMURTAS,1 ALI GULBAG2 1
Department of Electrical and Electronics Engineering, Bozok University, 66200 Yozgat, Turkey
2
Institute of Science Technology, Computer Engineering, Sakarya University, 54187 Adapazari, Turkey
Received 2 February 2011; accepted 18 May 2011 ABSTRACT: This article describes a modular approach to FPGA-based micro computer architecture design for supporting undergraduate courses in computer science and related discipline. We have adopted the modular approach to the second FPGA version of the BZK.SAU[6] named BZK.SAU.FPGA10.1. The BZK.SAU.FPGA10.1 platform has modular units that enable development of their own micro computer designs, particularly arithmetic and logic unit (ALU), memory and system bus, by integrating of simple building blocks. So the proposed modular approach will create high level interest in the faculty teaching computer organization and architecture course and produce significant contribution in the education of engineers. Also, such an approach could greatly increase the understanding of the architectural concept of the Microcomputer Architecture. All the modules in the BZK.SAU.FPGA10.1 design are entirely realized using schematic structure on Altera’s Cyclone II Development board. So, students can implement on a hardware platform to test their own designs by downloading since it is an affordable cost for the institution. ß 2011 Wiley Periodicals, Inc. Comput Appl Eng Educ 22:272– 282, 2014; View this article online at wileyonlinelibrary.com/journal/cae; DOI 10.1002/cae.20553 Keywords: computer architecture and organization; field-programmable gate arrays (FPGAs); educational tool for microcomputer design
INTRODUCTION Computer architecture and organization course is one of the main courses in the computer engineering and computer science curricula [1,2]. This course covers the basic concepts like the processor, the memory, the input/output system, Arithmetic and Logic Unit (ALU), and the bus design. The nature and background of undergraduate students in computer science and related areas have changed significantly in recent years. Traditional pedagogical methods teaching theory do not adequately address the needs of today’s students [3,4]. In Ref. 5, Djordjevic et al. discuss the challenges of teaching computer architecture. The open literature offers a variety of designs and simulators
Correspondence to F. Temurtas (
[email protected]). ß 2011 Wiley Periodicals Inc.
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suitable for teaching courses in computer architecture and organization. In order to provide readers with the complete features of these simulator and designs, more data are given in Refs. 67. In our previous study [8], we have designed a computer architecture simulator named BZK.SAU in an effort to appeal to this new generation of engineering students, promote higher retention rates, and increase motivation in undergraduate students. This simulator is designed using the George Mills’ Multimedia Logic (MML) emulator which is free software [9]. It has same features as in BZK.SAU.FPGA10.0. Also it was the first computer architecture simulator that has touched on interrupts and stacks as hardware. The assembler program has been designed for this and it is still being used for FPGA versions of BZK.SAU. The students have obtained a chance of testing the working of simulator with written program codes using these tools. Since the clock unit in this simulator is adjustable, students can watch step by step the working of their program codes and see the states of registers at any moment.
BZK.SAU.FPGA10.1
Because of the virtual nature of designing with this simulator, projects in an introductory laboratory are limited. Fieldprogrammable gate arrays (FPGAs) offer a design platform that allows students to implement more meaningful projects with tens of thousand of gates on actual hardware [10,11]. More educational applications in reconfigurable design were found at literature in recent years [12–22]. In Ref. [12], Gusˇtin and Bulic´ introduced computer architecture learning through the development of a very simple, non-pipelined FPGA-based microprocessor named MOVE. Their idea of a MOVE processor is based on the fact that most instructions in high level languages (HLLs) are of the ‘‘assign’’ type. In Ref. [13], Bulic´ et al. presented an integrated environment used in computer architecture education. The environment consists of the FPGA-based system named HIP microprocessor and a GUI application running on a PC. In Ref. [14], Gusˆtin presented the use of the programmable logic circuit in computer architecture education as an example of configuring the CPU. In Ref. [15], Hatfield et al. proposed that a 16-instruction RISC processor was designed and downloaded in an FPGA board with 70.000 gate-count Altera chip. She emphasized on the utilization of each logical module in the design of a sequence of simulation and implementation projects for teaching computer organization and architecture. In Ref. [16], Ochi proposed a 10instruction 16-bit RISC processor. He emphasized on an effective and practical education approach for understanding and developing pipelined RISC processor. In Ref. [17], Tiejun et al. proposed a 47-instruction 8-bit microprocessor. It was designed and implemented on Xilinx FPGA chip. He emphasizes that the modular, hierarchical design method adopted makes it is to modify. In Ref. [18], Pearson et al. proposed a 32-bit simplified MPIS-liked [20] CPU design. In Ref. [19], Nakano and Ito proposed a 16-bit processor named TINYCPU. It is designed using Verilog HDL. He emphasizes that the students were able to learn digital circuit design using processor architectures. In Ref. [21], Mazei and Malbasa proposed a 40 instructions 16- and 32-bit microcomputer named Edulent. In Ref. [22], Romero-Troncoso et al. proposed an 8-bit microprocessor named Micro-FIMEE-08. It has the advantage to be an open core which benefits the students with the hands-on experience on microprocessor design. In Ref. [6], an earlier article of ours, we have designed the first FPGA version of BZK.SAU[6] named BZK.SAU.FPGA10.0. It has same features as in BZK.SAU. BZK.SAU was designed by using Multimedia Logic (MML) emulator in 2008. This emulator program and Altera’s schematic design interfaces are same. In this first FPGA version, the system obtained using this emulator program is transported to the Altera’s FPGA development board Table 1
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without any changes. Table 1 summarizes the basic properties of selected FPGA-Based Microprocessor Architecture Designs. The main concerns of these educational FPGA applications were to introduce the concepts handled in Computer Architecture and Organization course, especially CPU design concept. Almost every application was designed using any hardware description language and very few are educationally oriented. The studies mentioned in the literature do not have an interface unit that the users can include their own designs. The user may increase the accumulation of knowledge about the architecture in these studies. However, it is not possible to intervene to these systems. Also the big time will be required to learn a complete system. Since our work has modular nature, the users do not need to learn a complete system. The users can easily include their own units to our system and see their work by making small changes in our system. Modular design is an important factor for the educational training of CPU design. We took the approach of modularization in order to avoid having students be overwhelmed by the complexity of a complete computer system design. This article presents a modular approach designed to improve motivation towards learning computer architecture subjects, particularly memory and ALU design subjects. The designed computer architecture using modular approach was named as BZK.SAU.FPGA.10.1. This architecture was entirely designed at logic gate level using Altera’s Quartus II CAD software tool. Additionally, this architecture design is free and can be downloaded from our website [23]. Since all modules are designed at logic gate level, the students can easily examine the internal structure of all modules in the design and use the required modules in the courses like Introduction to Logic Circuits, Digital Electronics, etc. The intention of this pedagogical proposition is that students should realize that they will be able to apply these subjects to the improvement of hardware performance. Since this approach has modular nature, students do not have to build a microcomputer architecture from scratch. In this approach, it is quite simple to include their designs like adding unit, subtraction unit, etc. to our system. So they can see the operation of their own designs on our system. In other words, our modular approach is plug&see. Therefore, teachers can teach more productive course by applying this approach to their teaching methods since our approach aims to learn piece by piece rather than complete system. The rest of this article is organized as follows. The second section describes the proposed modular approach to Microcomputer architecture design. Finally, the third section presents the future of the reported work, as well as a few conclusions.
The Basic Properties of FPGA-Based Microprocessor Architecture Designs Found at Literature in Recent Years [6]
System name a
BZK.SAU.FPGA.10.0 MOVE[11] HIP[12] No-Name[13] SIMPLE RISC COMPUTER[14] ASAP-0/f0,f1,f2[15] No-Name[16] TINYCPU[18] Edulent[20] Micro-FIMEE-08[21]
HW or SW
#Instruction
#Addressing modes
Type of development board
Fully HW SW HW and SW SW HW SW SW SW HW and SW SW
51 1 52 8 16 10 47 28 40 100
6 4 NA NA 3 NA 7 NA 4 4
Altera Cyclone DE2 Xilinx Spartan II Xilinx Spartan 3 Vantis MACH211 Altera UP2 ASAver.1(Xilinx XC52156 PQ208) Xilinx Spartan II Xilinx Spartan 3A and 3E Starter Kit Xilinx Spartan IIE Xilinx Spartan3 Starter Kit
NA, not available; HW, hardware; SW, software. a Available free.
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OZTEKIN, TEMURTAS, AND GULBAG
THE BASIC STRUCTURE OF BZK.SAU.FPGA.10.1 The BZK.SAU.FPGA10.1 is the new version of BZK.SAU.FPGA10.0 [6]. We have adopted the modular approach to memory and ALU design, particularly division operation, in this version. Also we did not use any unit supplied by Altera Cyclone. All units in BZK.SAU.FPGA10.1 architecture are our own specific designs and we built these units using only schematic design at logic gate level. A detailed block diagram that shows the components of the BZK.SAU.FPGA10.1 design is shown in Figure 1. The common features of both versions are listed as follows: (1) Support six addressing modes: immediate, direct, indirect, index, relative, and inherent mode. (2) It has eight registers: Address Register (AR), Data Register (DR), Accumulator (AC), Program Counter (PC), Stack Pointer (SP), Index Register (IX), and Temporary Register (TR) are 16-bit; Instruction Register (IR) is 8-bit. (3) 16-bit data bus and address bus. (4) The instructions which have relative and index addressing modes need an effective address. A unit was designed to calculate this address. (5) The instruction set consists of 51 instructions: 21 instructions for memory and accumulator, 8 instructions on index and stack registers, and 22 instructions for branching.
Modular Memory Approach In this work, two methods have been developed on how to design memory of any size with modular on FPGA development kits. The first method for modular memory design can be divided into three steps. The first step is to design one-bit memory cell. The inner structure and block diagram of this unit obtained using Quartus Web Edition Software from Altera Corporation are shown in Figures 2 and 3, respectively.
Figure 1
In Figure 2, the signal naming system is as follows: – – – – – –
Adr to represent an address line. W_R to represent a write or read enable input. D to represent a data input. Clr to represent a clear enable input. Clock to represent a system clock input. Q to represent a data output.
The second step is to decide the number of bits in a word. n-bit word has n one-bit memory cell block diagram as shown in Figure 4. Figure 5 shows the block diagram of this structure. Data bits D0, D1, . . ., Dn1 represent the data inputs of the first, second, etc. one-bit memory cell block, respectively. Similarly, output bits Q0, Q1, . . ., Qn1 represent the data outputs. The pins like Adr, W_R, Clr, and Clock are the common pins of one-bit memory cell blocks. The third step is to use a structure that is composed of a 1-to-2 decoder with enable input, two n-bit memory cells, and n 2-to-1 multiplexer (Mux). Figure 6 summarizes this structure. The last step is to build the structure in exactly the same way as the third step. In other words, a 1-to-2 decoder with enable input, two k n-bit memory cells (Fig. 6), where k represents the number of word in latest memory cell block, and n 2-to-1 multiplexer are needed. The outputs of 1-to-2 decoder should be connected to input En of 2 n-bit memory cell, respectively. The least significant bit to the above memory cell block, the most significant bit to below memory cell block as shown in Figure 6. The most significant bit of the address line will be connected to the input of decoder, the rest bits to inputs Adr of k n-bit memory cell blocks. Input pins Clr, W_R, Clock are common pins. The outputs of k n-bit memory cell blocks will be connected as shown in Figure 6. After making the connections between blocks, the block diagram of this structure should be created using Altera’s Quartus II software program. The processes in the last step should be repeated until the desired memory size is obtained. An example of memory of
Block diagram of BZK.SAU.FPGA10.1.
BZK.SAU.FPGA10.1
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Figure 2 The inner structure of one-bit memory cell. [Color figure can be viewed in the online issue, which is available at wileyonlinelibrary.com.]
Figure 3 One-bit memory cell block. [Color figure can be viewed in the online issue, which is available at wileyonlinelibrary.com.]
256 8-bit of BZK.SAU.FPGA10.1 is available on our website [23]. Its inner structure can be discovered. Table 2 shows requirements for the different sizes of memory. The second method is to design only using any of blocks in Table 2. The following equations should be used as a guideline for designing any size of memory. To obtain k n-bit memory cell block, where k and n represent the number and length of word, respectively. One log2
k k to decoder m m
Figure 4
n-Bit memory cell.
Figure 5 The block diagram of n-bit memory cell. [Color figure can be viewed in the online issue, which is available at wileyonlinelibrary.com.]
k m n-bit memory cell block m
(2)
k to1 multiplexer m
(3)
n
(1)
Figure 6
2 n-Bit memory cell.
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Table 2
OZTEKIN, TEMURTAS, AND GULBAG
Number of the Requirements for Desired Memory Size
Desired memory size 2 n-bit 4 n-bit 8 n-bit 16 n-bit ...
Decoder (1 2) 1 1 1 1 ...
Block 2(1 2(2 2(4 2(8
n-bit block) n-bit block) n-bit block) n-bit block) ...
Mux (2 1) n n n n ...
where m ¼ 2k ; 4k ; 8k ; . . . ; 1 represents the number of words in memory cell block to be used. For example, let us design 128 n-bit memory only using 8 n-bit memory cell block, where m and k equal 8 and 128, respectively. According to the above equations, a 4-to-16 decoder, sixteen 8 n-bit memory cell block, and n 16-to-1 multiplexer are needed. The connections between these units are structured in exactly the same way as the final step in the first method. The length of address line is 7-bit since the number of words of desired memory cell block is 128. Three of the most significant bits will be connected to the inputs of decoder, the rest bits to the inputs Adr2, Adr1, and Adr0 of 8 n-bit memory cell blocks.
Modular ALU Approach The proposed ALU has four units: Sys_Usr_Ctrl Unit, ALU_Interface, Sys_ALU, User-defined ALU. The top level view of ALU architecture is shown in Figure 7.
The first unit is Sys_Usr_Ctrl unit. It decides how to deal with ALU processes by controlling Sys_Usr_Ctrl register in this unit. Only this unit was written in VHDL language instead of schematic design since it is very simple. The content of this unit is given in Table 3. If the user wants to implement which process and processes on their own unit, S/he must make logic ‘‘1’’ the related bit or bits of Sys_Usr_Ctrl register. Table 3 summarizes ALU processes according to the related bits of Sys_Usr_Ctrl register. The second unit is ALU_Interface. This unit has the necessary control signals. The third unit is the own ALU of BZK.SAU.FPGA10.1. The last unit is used to connect the user’s own ALU. ACOUT[15..0] and DROUT[15..0] pins in this unit are Accumulator(AC) and Data Register outputs of BZK.SAU.FPGA10.1. Usr_ALUOUT[15..0] pins are the outputs of User-defined ALU. User_S[4..0] pins are the selector pins which select any operation in the User-defined ALU. Usr_Cin and Usr_Cout pins are carry bits. The following procedure briefly summarizes how to connect their own designs: Step 1: Make your ALU design in HDLs or schematic design in Altera’s Quartus Development Environment. (Important note: The operation order in your ALU must be like Table 3.) If your ALU has three operations such as multiplication, division, and add, selector pins in your ALU must be ‘‘01,’’ ‘‘10,’’ ‘‘00’’ selector pins, respectively.
Figure 7 Top level view of the modular ALU. [Color figure can be viewed in the online issue, which is available at wileyonlinelibrary.com.]
BZK.SAU.FPGA10.1
Table 3
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The Decision Unit and Operations Implemented in ALU According to the Bits Sys_Usr_Ctrl Register
The decision unit library IEEE; use ieee.std_logic_1164.all; entity Sys_Usr_Control is port(Sys_Usr_Ctrl:out std_logic_vector(17 downto 0)); end Sys_Usr_Control; architecture Sys_Usr_Control of Sys_Usr_Control is Begin Sys_Usr_Ctrl Register Sys_Usr_Ctrl
