Capacitor-Current-Feedback Active Damping With ... - IEEE Xplore

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IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 29, NO. 7, JULY 2014

Capacitor-Current-Feedback Active Damping With Reduced Computation Delay for Improving Robustness of LCL-Type Grid-Connected Inverter Donghua Pan, Student Member, IEEE, Xinbo Ruan, Senior Member, IEEE, Chenlei Bao, Weiwei Li, Student Member, IEEE, and Xuehua Wang, Member, IEEE

Abstract—This paper investigates the capacitor-currentfeedback active damping for the digitally controlled LCL-type gridconnected inverter. It turns out that proportional feedback of the capacitor current is equivalent to virtual impedance connected in parallel with the filter capacitor due to the computation and pulse width modulation (PWM) delays. The LCL-filter resonance frequency is changed by this virtual impedance. If the actual resonance frequency is higher than one-sixth of the sampling frequency (fs /6), where the virtual impedance contains a negative resistor component, a pair of open-loop unstable poles will be generated. As a result, the LCL-type grid-connected inverter becomes much easier to be unstable if the resonance frequency is moved closer to fs /6 due to the variation of grid impedance. To address this issue, this paper proposes a capacitor-current-feedback active damping with reduced computation delay, which is achieved by shifting the capacitor current sampling instant towards the PWM reference update instant. With this method, the virtual impedance exhibits more like a resistor in a wider frequency range, and the openloop unstable poles are removed; thus, high robustness against the grid-impedance variation is acquired. Experimental results from a 6-kW prototype confirm the theoretical expectations. Index Terms—Active damping, grid-connected inverter, grid impedance, LCL filter, open-loop unstable poles.

I. INTRODUCTION OWADAYS, distributed power generation systems (DPGSs) based on renewable energy, such as wind energy and solar energy, are attracting more and more attention for their environmental friendly features. As an interface between the DPGSs and power grid, a grid-connected inverter plays an important role in injecting high-quality power into the grid [1]. In the grid-connected inverter, an L filter or LCL filter is usually

N

Manuscript received April 15, 2013; revised June 26, 2013; accepted August 13, 2013. Date of current version February 18, 2014. This work was supported by the National Natural Science Foundation of China under Award 50837003 and Award 51007027, the National Basic Research Program of China under Award 2009CB219706, and Jiangsu Province 333 Program for Excellent Talents. Recommended for publication by Associate Editor S. Choi. D. Pan, C. Bao, W. Li, and X. Wang are with the State Key Laboratory of Advanced Electromagnetic Engineering and Technology, Huazhong University of Science and Technology, Wuhan 430074, China (e-mail: [email protected]; [email protected]; [email protected]; [email protected]). X. Ruan is with the State Key Laboratory of Advanced Electromagnetic Engineering and Technology, Huazhong University of Science and Technology, Wuhan 430074, China, and also with the Aero-Power Sci-Tech Center, College of Automation Engineering, Nanjing University of Aeronautics and Astronautics, Nanjing 210016, China (e-mail: [email protected]). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TPEL.2013.2279206

adopted to attenuate the switching harmonics. Comparatively, the LCL filter is competitive for its higher attenuating ability, which allows the use of smaller inductors to meet the harmonic limits. However, due to the resonance hazard of the LCL filter, damping solutions are needed to stabilize the system [2]. A direct way to damp the LCL-filter resonance is to insert a passive resistor into the filter network. This passive damping solution is very simple and highly reliable, but it results in power loss [3], [4]. To overcome this drawback, the concept of virtual resistor is proposed in place of the physical one [5], [6]. Generally, the virtual resistor is realized by proper control algorithms, which are the so-called active damping solutions. Compared with passive damping, active damping is more flexible and more efficient. Among the various active damping solutions, the capacitor-current-feedback active damping has been widely used for its simple implementation [7]–[9], and it is chosen in this paper. In [7], it has been proved that proportional feedback of the capacitor current is equivalent to a virtual resistor connected in parallel with the filter capacitor. This conclusion is drawn without considering the delay effect, and thus it is not accurate when digital control is employed. In the digitally controlled system, there will be computation and pulse width modulation (PWM) delays. The computation delay is the time duration from the sampling instant to the PWM reference update instant, and it is one sampling period in the synchronous sampling case (where the sampling takes place at the beginning and in the middle of a switching period) [10]. The PWM delay is caused by the zero-order hold (ZOH) effect which keeps the PWM reference constant after it has been updated, and it is definitely half sampling period [11]. The delay effect on the LCL-type grid-connected inverter with capacitor-current-feedback active damping has been discussed in recent literatures. Orellana and Griño´ [12] present a comparative study of the capacitor-current-feedback active damping in the continuous-time and discrete-time domain, and show that the discrete-time active damping loop might be unstable due to the one-sample computation delay. Bao et al. [13] regard onesixth of the sampling frequency (fs /6) as a critical LCL-filter resonance frequency, and show that if the resonance frequency is higher than fs /6, the resonance peak should not be damped below 0 dB to ensure system stability. More importantly, Parker et al. [14] show that if the resonance frequency is equal to fs /6, the digitally controlled LCL-type grid-connected inverter will always be unstable no matter how much the capacitor current feedback coefficient is. However, what essentially causes the

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PAN et al.: CAPACITOR-CURRENT-FEEDBACK ACTIVE DAMPING WITH REDUCED COMPUTATION DELAY

loss of damping effectiveness for the resonance frequency of fs /6 is still not identified. The LCL-filter resonance frequency can be intentionally arranged away from fs /6 to avoid instability. Since a lower resonance frequency usually calls for larger filter inductors or filter capacitor [15], a resonance frequency higher than fs /6 would be cost-effective. However, the real grid contains the inductive grid impedance, which makes the resonance frequency lower. Furthermore, the grid impedance might vary in a wide range depending on the grid configuration, which leads to a wide range variation of the resonance frequency. As reported in [16], a 40% drop of the resonance frequency can be yielded as the grid impedance varies up to a typical 10% per-unit (PU). In view of this, the grid impedance might reduce the resonance frequency to fs /6, and thus trigger instability. Therefore, the stability challenge for the resonance frequency of fs /6 must be addressed to achieve high robustness against the grid-impedance variation. In recent literatures, the control and stability issues of the LCL-type grid-connected inverter have been extensively discussed. In [17], a linear quadratic Gaussian servo controller which combines the linear quadratic regulator and the Kalman filter is proposed. With this control scheme, null steady-state tracking error, channel decoupling, and noise immunity are achieved. In [18], an adaptive robust predictive current control is presented to achieve zero steady-state current error for threephase grid-connected inverters. In a word, Huerta et al. [17] and Esp´ı et al. [18] mainly focus on the steady-state control performance, but do not pay much attention to system stability concerning the grid-impedance variation. In [19], the variation of grid impedance is taken into account, and a model reference adaptive state feedback control is employed to guarantee system stability. With this method, the current controller presents good transient performance and stability features even with a large variation of grid impedance. Nevertheless, the design procedure for an adaptive controller is complicated. This paper investigates the effect of computation and PWM delays on the capacitor-current-feedback active damping for the LCL-type grid-connected inverter, and proposes useful guidelines for improving system robustness against the gridimpedance variation. In Section II, the averaged switch model (ASM) of the digitally controlled LCL-type grid-connected inverter with capacitor-current-feedback active damping is derived. Through equivalent transformations of the ASM, a virtual impedance model of the capacitor-current-feedback active damping is obtained. Based on the virtual impedance model and the open-loop Bode diagrams, great insights into the delay effect on the damping performance are provided in Section III. In this section, the stability analysis with the Nyquist stability criterion clearly identifies that the unconditional instability feature for the resonance frequency of fs /6 arises from the generation of a pair of open-loop unstable poles. Accordingly, the demand for reducing the computation delay in the capacitor-currentfeedback active damping is drawn out to remove the open-loop unstable poles. In Section IV, an intuitive method for reducing the computation delay is introduced, which is realized by shifting the sampling instant towards the PWM reference update instant. Such sampling scheme has been successfully utilized

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Fig. 1. LCL-type grid-connected inverter with capacitor-current-feedback active damping.

in [20] and [21], and it is extended to the capacitor current in this paper. However, unlike the cases in [20] and [21], where the currents needed to be sampled are ripple-free, the capacitor current of the LCL filter contains abundant switching ripple, aliasing might occur if the sampling instant is not properly located. A detailed investigation of the sampling-induced aliasing is presented in this section to help choose the sampling instant of the capacitor current. In Section V, a comparison between the capacitor-current-feedback active damping with one-sample and reduced computation delay is presented. It will be shown that with the proposed method, the open-loop unstable poles are removed, and a stable operation is retained even for the resonance frequency of fs /6; thus, high robustness against the grid-impedance variation is acquired. In Section VI, the experimental results are presented to validate the theoretical analysis. Finally, Section VII concludes this paper. II. MODELING THE LCL-TYPE GRID-CONNECTED INVERTER A. ASM of the Digitally Cotrolled System Fig. 1 shows the configuration of a voltage source inverter feeding into the grid through an LCL filter. L1 is the inverter-side inductor, C is the filter capacitor, and L2 is the grid-side inductor. Generally, the grid impedance at the point of common coupling (PCC) mainly consists of inductance and resistance [16]. Since the grid resistance offers a certain degree of damping and helps stabilizing the system, a pure inductance Lg is considered here to draw the worse case. Lg contributes to the grid-side inductor, and can be regarded as a part of the LCL filter. The primary objective of the grid-connected inverter is to control the grid current iL 2 , so that it can be synchronized with the voltage at PCC, which is denoted by vg , and its amplitude can be regulated as required. Generally, the phase angle of vg is obtained through a phase-locked loop (PLL), and the current amplitude reference is generated by the outer voltage loop [1]. Since the dynamics of the voltage loop is much slower than that of the grid current loop, the grid current loop can be evaluated independently, and the current amplitude reference is directly given as I ∗ here. iL 2 is sensed with the sensor gain of Hi2 , and the sensed current is compared to the current reference iref .

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capacitor current has no contribution to the resonance damping [5], [6], and thus it is unnecessary to be sampled accurately. In view of this, we might sample the capacitor current at the time instant which has a time duration of Td (0 < Td ≤ Ts ) before the PWM reference update instant, and the sampled capacitor current is shown with the dash-dotted line in Fig. 2. As seen, quite different sampling results might be obtained depending on the sampling instant. The detailed analysis about this sampling scheme will be presented latter in the following section. Adopting the method, the computation delay in the capacitorcurrent-feedback active damping can be expressed in a general value of Td . For convenience of illustration, it is defined that Td = λTs (0 < λ ≤ 1). Obviously, λ = 1 for the synchronous sampling case. After being updated, the PWM reference is held on and compared to the triangular carrier to generate the duty cycle. This behavior can be modeled by ZOH, which is expressed as Gh (s) =

1 − e−sT s . s

(2)

To obtain a more intuitive sense, Gh (s) is rewritten in the frequency domain, i.e., Gh (jω) = Fig. 2.

Computation and PWM delays inherent in the digital PWM.

The current error signal is sent to the current regulator Gi . The capacitor current ic is fed back to damp the LCL-filter resonance actively, and Hi1 is the feedback coefficient. Subtracting the capacitor current feedback signal from the output of the current regulator yields the modulation reference vm , which is fed to a digital PWM modulator. As previously mentioned, the digitally controlled system contains computation and PWM delays. The delay mechanism is shown in Fig. 2, where the sine-triangle, asymmetrical regular sampled PWM is employed, the sampling frequency fs is twice the switching frequency fsw , and Ts is the sampling period. In general, iL 2 and ic are sampled at the beginning and in the middle of the switching period, and the sampled currents are shown with the dashed lines in the figure. Such sampling scheme is called the synchronous sampling, and it has the advantage of obtaining the average current per switching period (the fundamental component) without requiring low-pass filtering [10]. At time step k, the sampled currents are used to calculate the PWM reference. In order to avoid the unwanted intermediate PWM transitions, the PWM reference is not updated until time step k+1 [22]. Thus, a computation delay of Ts is introduced into the grid current loop and the capacitor-current-feedback active damping. In the s-domain, the one-sample computation delay is expressed as Gd (s) = e−sT s .

(1)

To evaluate the delay effect on the damping performance from a general point of view, the capacitor-current-feedback active damping with an unspecific computation delay is intentionally investigated. Indeed, the fundamental component of the

sin (0.5ωTs ) −j 0.5ω T s 1 − e−j ω T s = e jω 0.5ω

≈ Ts e−j 0.5ω T s .

(3) −0.5sT s

, which Applying s = jω to (3) yields Gh (s) ≈ Ts e means that a PWM delay of half sampling period is introduced. Considering the computation and PWM delays, the ASM of the digitally controlled LCL-type grid-connected inverter is given in Fig. 3, where KPW M is the transfer function of the PWM inverter, expressed as KPW M =Vin /Vtri , and Vin is the input voltage, Vtri is the amplitude of the triangular carrier. Meanwhile, the sampler is represented by 1/Ts [23]. B. Virtual Impedance Model of the Capacitor-Current-Feedback Active Damping Referring to Fig. 3, by replacing the feedback of the capacitor current ic (s) with the capacitor voltage vc (s), and moving its feedback node from the output of Gd (s) to the output of 1/sL1 , an equivalent block diagram is obtained, as shown in Fig. 4(a). So the capacitor-current-feedback active damping is equivalent to virtual impedance Zeq connected in parallel with the filter capacitor. And Zeq is expressed as Zeq (s) = =

L1 Ts esλT s Hi1 KPW M CGh (s) L1 Δ es(λ+0.5)T s = Rd es(λ+0.5)T s Hi1 KPW M C

(4)

where Rd = L1 /(Hi1 KPW M C) is the equivalent virtual resistor of the capacitor-current-feedback active damping without delays [7]. Substituting s = jω into (4) yields Zeq (jω) = Rd cos(λ + 0.5)ωTs + jRd sin(λ + 0.5)ωTs Δ

=Req (ω)//jXeq (ω)

(5)


Fig. 3.

ASM of the digitally controlled LCL-type grid-connected inverter with capacitor-current-feedback active damping.

Fig. 4.

Equivalent virtual impedance of the capacitor-current-feedback active damping. (a) Block diagram. (b) Equivalent circuit.

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where Req (ω) =

Rd , cos(λ + 0.5)ωTs

Xeq (ω) =

Rd . sin(λ + 0.5)ωTs

(6)

It means Zeq can be represented in form of parallel connection of a resistor Req and a reactor Xeq , as shown in Fig. 4(b). In Zeq , the component Req damps the resonance peak of the LCL filter, and the component Xeq changes the resonance frequency. As seen in (6), both Req and Xeq are frequency dependent. The frequency boundary of Req to be positive and negative is denoted by fR b , and the frequency boundary of Xeq to be inductive and capacitive is denoted by fX b . According to (6), the expressions of fR b and fX b can be derived as fR b =

fs , 4 (λ + 0.5)

fX b =

fs . 2 (λ + 0.5)

(7)

Obviously, fX b = 2fR b . For the synchronous sampling case (λ = 1), fR b =fs /6, fX b =fs /3, and the curves of Req and Xeq as the function of frequency are shown with the solid lines in Fig. 5. Besides, the proposed virtual impedance model can be extended to the situation where other state variable is used for the resonance damping. Usually, the inverter-side inductor current is the one which is used except for the capacitor current [5], [7]. In [7], without considering the delay effect, it has been proved that proportional feedback of the inverter-side inductor current is equivalent to a virtual resistor Rv connected in series with the inverter-side inductor. Similar to the analysis depicted previously, when one-sample computation plus half-sample PWM delays are taken into account, proportional feedback of the inverter-side inductor current will be equivalent to virtual impedance, which is expressed as Rv e−1.5sT s , connected in series with the inverter-side inductor.

Fig. 5.

Curves of R e q and X e q as the function of frequency.

III. EFFECT OF THE COMPUTATION AND PWM DELAYS ON THE DAMPING PERFORMANCE Based on the virtual impedance model depicted previously, the effect of the computation and PWM delays on the damping performance is comprehensively explored in this section. The loop gain is used for performance evaluation. For convenience of derivation, the loop gain in the z-domain is preferred and derived in Appendix A. Here, its expression is given as (8), shown at the bottom of the next page. In (8), Gi (z) is the discrete representation of Gi (s), and ωr is the resonance angular frequency of the LCL filter, expressed as L1 + L2 + Lg (9) ωr = L1 (L2 + Lg ) C and the resonance frequency is fr = ωr /(2π). In the following analysis, the capacitor-current-feedback active damping with

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Fig. 6.


Bode diagrams of the loop gain T (z,1) with G i (z) = 1. (a) fr ∈ (0, fs /6). (b) fr ∈ (fs /6, fs /3). (c) fr ∈ (fs /3, fs /2).

one-sample computation delay (λ = 1) is first evaluated to point out the basic problems in conventional application. A. Performance Evaluation in the Open-Loop Bode Diagrams For λ = 1, the Bode diagrams of loop gain T (z,1) with Gi (z) = 1 for different fr are shown in Fig. 6. As seen, for a specific fr , both the magnitude and phase plots vary significantly with the increase of Hi1 . 1) Magnitude Plots: In the range (0, fs /3), Xeq is inductive and yields a higher actual resonance frequency fr , as shown in Fig. 6(a) and (b); and in the range (fs /3, fs /2), Xeq is capacitive and yields a lowerfr , as shown in Fig. 6(c). From (4) and (6), it is clear to see that a larger Hi1 leads to a smaller |Xeq |, and thus fr deviates farther from fr . Since fX b =fs /3, no matter how Hi1 increases, fr will only approach but never step over fs /3. However, if fr < fs /6, fr might step over fs /6 if Hi1 is sufficiently large. The value of Hi1 yielding fr = fs /6, Hi1c , is derived in Appendix B, and here its expression is given as Hi1c =

ωr L1 (2 cos ωr Ts − 1) . KPW M sin ωr Ts

(10)

For Hi1 > Hi1c , fr > fs /6, as shown in Fig. 6(a); and if fr > fs /6, fr > fs /6 certainly exists for Hi1 > 0. 2) Phase Plots: As seen from Fig. 6, the −180◦ crossings might take place at fr or fs /6 or both of them. For Hi1 = 0, the phase plots cross over −180◦ at fr if fr < fs /6 or at fs /6 if fr > fs /6 [14]. While for Hi1 > 0, the situations become much more complicated. From (8), the loop gains at fr and fs /6 can be obtained as Hi2 L1 (11a) T (ej ω r T s , 1)|G i (z )=1 = − Hi1 (L1 + L2 + Lg )

T (ej π /3 , 1)|G i (z )=1 =

Hi2 L1 Hi1c − Hi1 ·

sin ωr Ts + ωr Ts (1 − 2 cos ωr Ts ) . (L1 + L2 + Lg ) sin ωr Ts (11b)

From (11a), it can be seen that the phase plots always cross over −180◦ at fr for Hi1 > 0. Strictly, fr < fs /2 is required to ensure system controllability [24], thus ωr Ts < π and sinωr Ts > 0. In (11b), letting f (ωr Ts ) = sinωr Ts + ωr Ts (1−2cosωr Ts ), it is easy to get that f (ωr Ts ) > 0. That means f (ωr Ts ) is an increasing function, thus f (ωr Ts ) > f (0) = 0. And as seen in (10), Hi1c > 0 for fr < fs /6 and Hi1c ≤ 0 for fr ≥ fs /6. Thus, if fr < fs /6, the phase plots cross over −180◦ one more time at fs /6 for Hi1 > Hi1c ; if fr ≥ fs /6, the phase plots certainly cross over −180◦ at fs /6 for Hi1 > 0. 3) Open-Loop Unstable Poles: Since the resonance actually arises at fr rather than fr , the characteristics that Req exhibits at fr will be essential for the resonance damping. Specially, for fr = fs /6, i.e., Hi1 =Hi1c when fr < fs /6, since Req is infinite at fr (fs /6), it has no contribution to the resonance damping. Thus, the magnitude plot exhibits an infinite resonance gain, and the phase plot steps by −180◦ at fr , as shown in Fig. 6(a). Apparently, these features are exactly the same as those in the undamped case. More importantly, for fr > fs /6, Req is negative at fr . As demonstrated in Appendix B, a pair of openloop unstable poles will be generated in this case. Based on the previous analysis, the key features of the digitally controlled LCL-type grid-connected inverter with capacitor-current-feedback active damping can be summarized as follows.

ωr Ts z 2 − 2z cos ωr Ts + 1 − (z − 1)2 sin ωr Ts Hi2 KPW M Gi (z) · T (z, λ) = ωr (L1 + L2 + Lg ) (z − 1) z (z 2 − 2z cos ω T + 1) + H i 1 K P W M (z − 1) [z sin (1 − λ) ω T + sin λω T ] r s r s r s ωr L1 (8)


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1) If fr < fs /6, i.e., 0 < Hi1 < Hi1c when fr < fs /6, Req is positive atfr , no open-loop unstable pole exists, and the phase plots cross over −180◦ at fr . 2) Iffr = fs /6, i.e., Hi1 =Hi1c when fr < fs /6, Req is infinite atfr (fs /6), it has no contribution to the resonance damping, no open-loop unstable pole exists, and the phase plots cross over −180◦ at fr . 3) If fr > fs /6, i.e., Hi1 > Hi1c when fr < fs /6 or Hi1 > 0 when fr ≥ fs /6, Req is negative at fr , a pair of open-loop unstable poles is generated, and the phase plots cross over −180◦ both at fr and fs /6. B. Stability Analysis With the Nyquist Stability Criterion After a detailed investigation of the frequency responses of the loop gain, stability analysis is carried out by means of the Nyquist stability criterion. In the open-loop Bode diagram, the frequency ranges with magnitudes above 0 dB are concerned. In these ranges, a −180◦ crossing in the direction of phase rising is defined as positive crossing, and a −180◦ crossing in the direction of phase falling is defined as negative crossing. The numbers of positive and negative crossings are denoted by N+ and N− , respectively. The Nyquist stability criterion tells that the value of 2(N+ −N− ) must be equal to the number of the open-loop unstable poles to ensure system stability. Otherwise, the system goes unstable [25]. Case I ( fr < fs /6, and fr ≤ fs /6): For fr < fs /6, if 0 < Hi1 ≤Hi1c , then fr ≤ fs /6, and no open-loop unstable pole exists. Hence, the value of 2(N+ −N− ) must be equal to zero to ensure system stability. Note that the phase plot crosses over −180◦ only at fr in the direction of phase falling, which means N+ is zero unconditionally. Therefore, as long as the gain margin at fr is greater than 0 dB, i.e., N− = 0, the system will be stable. From (8), the gain margin (in decibels) at fr can be obtained as GM1 = −20 lg T ej ω r T s , 1 G i (z )=K p = 20 lg

Hi1 (L1 + L2 + Lg ) Hi2 Kp L1

(12)

where Gi (z) is represented by a proportional gain Kp . In fact, Gi (z) might be either a proportional-integral (PI) regulator or a proportional-resonant (PR) regulator, but both a PI regulator and a PR regulator can be reduced to a proportional gain at the −180◦ crossover frequencies [13], [14]. Case II (fr < fs /6, and fr > fs /6): For fr < fs /6, if Hi1 > Hi1c , then fr > fs /6, a pair of open-loop unstable poles arises, and the phase plot crosses over −180◦ at fr in the direction of phase falling, and at fs /6 in the direction of phase rising, respectively. Hence, to ensure system stability, the value of 2(N+ −N− ) must be equal to 2, which means that the gain margin at fr must be greater than 0 dB, i.e., N− = 0, and the gain margin at fs /6 must be smaller than 0 dB, i.e., N+ = 1.

Fig. 7.

Curves of GM 1 and GM 2 with the increase of L g .

From (8), the gain margin (in decibels) at fs /6 can be obtained as (13), shown at the bottom of this page. According to (12) and (13), GM2 will be equal to GM1 if fr =fs /6. Case III (fr ≥ fs /6, and fr > fs /6): If fr ≥fs /6, then fr > fs /6 for Hi1 > 0, and the phase plot crosses over −180◦ at fs /6 in the direction of phase falling, and at fr in the direction of phase rising, respectively. Similarly, due to the existence of a pair of open-loop unstable poles, GM1 < 0 dB and GM2 > 0 dB are both required for system stability. C. Robustness Against the Grid-Impedance Variation As seen, if a pair of open-loop unstable poles is generated, stringent gain margin requirements have to be satisfied to ensure system stability, and these requirements vary with fr . Therefore, it is necessary to evaluate the system robustness against the variation of fr , which is commonly caused by the variation of Lg [16]. According to (12) and (13), the curves of GM1 and GM2 with the increase of Lg are depicted in Fig. 7, where fr > fs /6 is chosen for Lg = 0 in order to cover all the three cases discussed previously. With the increase of Lg , both fr and fr decreases. Since fr > fr for fr < fs /6, the system first steps from Case III into Case II, and then into Case I. And for fr = fs /6, since T (z,1) exhibits an infinite resonance gain at fs /6, a notch is produced in the curve of GM2 consequently. Based on Fig. 7 and the gain margin requirements discussed previously, it can be concluded that: 1) If fr > fs /6, GM1 < 0 dB and GM2 > 0 dB are required for Hi1 > 0 (Case III). With the increase of Lg , GM1 increases, and GM2 decreases in Case III; thus, the stability margin gets smaller, which indicates poor robustness against the grid-impedance variation. 2) If fr < fs /6, GM1 > 0 dB is required for 0 < Hi1 ≤Hi1c (Case I), and GM1 > 0 dB and GM2 < 0 dB are required for Hi1 > Hi1c (Case II). With the increase of Lg , GM1 increases in Cases I and II, and GM2 decreases in Case II;

L1 + L2 + Lg Hi1 KPW M sin ωr Ts + ωr L1 (1 − 2 cos ωr Ts ) j π /3 = 20 lg GM2 = −20 lg T e ,1 · G i (z )=K p Hi2 KPW M Kp L1 sin ωr Ts + ωr Ts (1 − 2 cos ωr Ts )

(13)

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thus the stability margin gets larger, which indicates high robustness against the grid-impedance variation; 3) If fr = fs /6, GM1 =GM2 , the requirements of GM1 < 0 dB and GM2 > 0 dB are contradictory, which indicates the system can hardly be stable irrespective of Hi1 . Therefore, for the digitally controlled LCL-type gridconnected inverter with capacitor-current-feedback active damping, it is desirable to choose fr < fs /6. However, a lower fr usually calls for larger filter inductors or filter capacitor [15], and thus is not cost-effective. To improve system robustness for fr > fs /6 and address the stability challenge for fr =fs /6, the open-loop unstable poles need to be removed. In doing so, the system with fr ≥fs /6 will behave in the same way as the case offr ≤ fs /6, where the gain margin requirement is much easier to be satisfied. According to the previous analysis, a positive Req in a wider frequency range (i.e., a higher fR b ) is desirable to get rid of the open-loop unstable poles. As seen in (7), this can be achieved by reducing λ, i.e., reducing the computation delay in the capacitor-current-feedback active damping. IV. CAPACITOR-CURRENT-FEEDBACK ACTIVE DAMPING WITH REDUCED COMPUTATION DELAY As shown in Fig. 2, the computation delay in the capacitorcurrent-feedback active damping can be reduced by shifting the capacitor current sampling instant towards the PWM reference update instant. However, since the capacitor current contains abundant switching ripple, aliasing might occur if the sampling instant is not properly located. Therefore, before putting into practice, the feasibility and effectiveness of this method needs to be evaluated at first. A. Sampling-Induced Aliasing of the Capacitor Current Fig. 8(a) shows the simulation results of the capacitor current sampling under normal operation, where the fundamental frequency fo = 50 Hz, fsw = 10 kHz, and fs = 20 kHz. Different values of λ in the range [0, 1] are investigated individually with a step of 0.1. As seen, the sampled capacitor current ics varies significantly with the sampling instant. For the synchronous sampling case (λ = 1), since the sampling instant locates at the beginning and in the middle of the switching period, the average value per switching period, i.e., the fundamental component, is acquired. Thus, aliasing is automatically avoided. Because of this advantage, the synchronous sampling is commonly used in the digitally controlled systems. And for 0 < λ < 1, the fundamental sampling error is introduced, and the low-order aliased harmonics (mainly 3rd, 5th, and 7th) might appear in ics . Since the LCL-filter resonance arises in the high-frequency range, these low-frequency disturbances will not affect the performance of the resonance damping [5], [6], but they might affect the performance of the grid current reference tracking. Fortunately, due to the fact that the capacitor current feedback signal is relatively small compared with the PWM reference, the effects of these small bounded disturbances will not be notable [26]. In addition, the current regulator Gi (z) is generally tuned with high low-frequency gains, and thus it can further suppress these undesirable effects on the grid current.

Fig. 8. Simulation results of the capacitor current sampling under normal operation. (a) Sampled capacitor current. (b) Harmonic analysis.

Moreover, this shortcoming can be avoided by selecting a proper λ. The harmonic amplitudes in ics for different λ are lined out in Fig. 8(b). Note that for two different λ which are symmetrical about 0.5, the harmonic amplitudes in ics are nearly the same. Especially for λ = 0.5, the minimum harmonics exist, and ics is nearly equal to the fundamental component. Thus, it is desirable to choose a λ which is either relatively small (for instance λ ≤ 0.1) or much closer to 0.5. In practical application, the minimum value of λ is limited by the time required for the capacitor current sampling and the processing of active damping. This time is related to the A/D converter and the digital signal processor (DSP) that used. Taking a 32-bit fix-point 150MHz TI TMS320F2812 DSP for instance, the single-channel conversion time of the on-chip A/D converter is 0.2 μs [27]. The conversion result is subtracted from the output of the current regulator, and then the PWM reference is obtained and updated to the compare units of DSP. The time for these processing is measured as 0.6 μs. Thus, the overall time is 0.8 μs, which means that the minimum value of λ is about 0.02 for fs = 20 kHz. Besides the sampling-induced aliasing, the switching noise is another important issue in the capacitor current sampling. The switching noise is created during switching transitions and coupled to the current sensors. In the synchronous sampling case, since the sampling takes place at the beginning and in the middle of a switching period where no switching devices are turned ON


or OFF, the switching noise is almost avoided in the sampled capacitor current. And in the sampling scheme discussed previously, the capacitor current sampling instant might be shifted to the switching points; thus, the sampled capacitor current might be distorted by the switching noise. To overcome this drawback, some techniques are adopted in practical implementation. First, skip any sampling during switching transitions. The switching transition instant can be estimated using the PWM reference value, and then the capacitor current sampling can be adjusted properly away from this instant. Second, install a low-pass filter between the current sensor and the A/D converter. Considering that the frequency of switching noise is usually higher than 1 MHz [28], a low-pass filter with a cutoff frequency around 100 kHz will be suitable. Note that the grid current is ripple free, there is no constraint on its sampling instant. Therefore, the sampling scheme discussed previously can also be applied to the grid current. In this way, the computation delay in the grid current loop can be reduced, which leads to the improvement of system phase. Thus, a higher crossover frequency with satisfactory phase margin can be acquired [20], [21]. Due to the space limit, the detailed analysis about this issue is not presented here. Except for the delay reduction, the computation delay might be compensated either with a lead compensator [15] or a state observer [26]. A lead compensator can partially compensate the computation delay, but it leads to the amplification of high frequency noise. A state observer is a hopeful solution to this problem. But, the nature of state observer as model-based dependence increases its sensitivity against LCL-filter parameters variation. Compared with these two typical delay-compensation approaches, the delay reduction method presented in this paper is simpler since it only needs a proper shifting of the capacitor current sampling instant. Moreover, the fact that the computation delay is directly reduced through sampling indicates a model-independent nature. B. Damping Performance With Reduced Computation Delay After the computation delay in the capacitor-current-feedback active damping has been reduced, the damping performance needs to be reevaluated. As seen in (4), with a smaller λ, Zeq exhibits more like the virtual resistor Rd . According to (7), both fR b and fX b increases with the decrease of λ. The previous analysis shows that, fR b should be higher than fr to get rid of the open-loop unstable poles. Therefore, a smaller λ would be desirable for a higher LCL-filter resonance frequency. Particularly, if λ = 0, then fR b =fs /2, a positive Req will be obtained below the Nyquist frequency (see Fig. 5). This is the ideal case, in which the open-loop unstable poles can be removed for fr < fs /2. Obviously, this ideal case can be approached by minimizing the value of λ. While in practice, λ can be chosen according to the specific fr which is usually constrained by the requirement of harmonic attenuation, and it is not necessary to be the minimum. Specifically, fr is typically required to be lower than one half of the switching frequency fsw to ensure the effective attenuation of the switching harmonics [3], [29], and fs is generally set to be 2fsw [10], [11]. Thus, fr < fs /4, and then a positive Req

3421

TABLE I PARAMETERS OF THE PROTOTYPE

in the range (0, fs /4) is expected. As seen in (7), this can be achieved by choosing λ ≤ 0.5. Taken as an instance, the case of λ = 0.5 is illustrated to show how the damping performance is improved by reducing the computation delay. Recalling (4) and (7), for λ = 0.5, Zeq can be rewritten as Rd esT s , and fR b =fs /4, fX b = fs /2. The curves of Req and Xeq as the function of frequency are shown with the dashed lines in Fig. 5. Similar to the case of fr < fs /6 for λ = 1, in the case of fr < fs /4 for λ = 0.5, a higher fr will be yielded due to the inductive Xeq . And fr might step over fs /4 if Hi1 is sufficiently large. Recalling the derivation of Hi1c , in this case, the value of Hi1 yieldingfr = fs /4, Hi1m , can be derived as Hi1m =

ωr L1 cos ωr Ts . KPW M sin 0.5ωr Ts

(14)

Since Req is infinite at fs /4, a resonance peak with infinite gain arises at fr forfr = fs /4. If 0 < Hi1 < Hi1m , thenfr < fs /4, Req is positive at fr , no open-loop unstable pole exists (the derivation of the open-loop unstable poles is the same as the case of λ = 1, and thus it is not repeated here), and the phase plot crosses over −180◦ only once. According to the Nyquist stability criterion, as long as the gain margin at the −180◦ crossover frequency is greater than 0 dB, the system will be stable. Apparently, these features are exactly the same as the case of fr < fs /6 for λ = 1. Therefore, it can be foreseen that a robust damping performance will be acquired in the case of fr < fs /4 for λ = 0.5. To obtain a more explicit understanding, a design example will be given in the following section. V. DESIGN AND COMPARISON OF THE CAPACITOR-CURRENT-FEEDBACK ACTIVE DAMPING WITH ONE-SAMPLE AND REDUCED COMPUTATION DELAY The design and comparison of the capacitor-current-feedback active damping with one-sample and reduced computation delay are presented in this section. Table I gives the parameters of a 6-kW single-phase LCL-type grid-connected inverter, where the unipolar sine-triangle, asymmetrical regular sampled PWM is implemented. The LCL filter is regularly designed with the well-known constraints, i.e., the current ripple is less than 40% (peak-to-peak) of the rated fundamental current on the inverter

3422

Fig. 9.


Bode diagrams of the compensated loop gain T (z, λ).

side, the capacitive reactive power is less than 5% of rated load, and the switching harmonics is less than 0.3% of the rated fundamental current [3], [29]. The consequent resonance frequency is 4.6 kHz, which is much closer to fs /4 (5 kHz). All the controller parameters are properly designed with assumption of Lg = 0, and the system stability is examined with Lg varies up to 10% PU, which corresponds to a short-circuit ratio of 10 [16]. A PR regulator is employed and tuned considering the overall system dynamics which are mainly evaluated by the unity-gain crossover frequency fc and the phase margin PM. For the system studied in this paper, a stable operation might yield multiple unity-gain crossings (for instance the case of fr > fs /6 for λ = 1). Anyway, the dynamic of the dominant closed-loop poles is related to the unity-gain crossing at the lowest frequency. To yield a satisfactory transient performance, a phase margin of PM = 45◦ at fc ≈ 0.3fr is desired [8]. In the s-domain, PR regulator is expressed as 2Kr ωi s Gi (s) = Kp + 2 s + 2ωi s + ωo2

(15)

where ωo = 2πfo is the fundamental angular frequency, and ωi is the resonant cutoff frequency. To deal with a typical ±1% variation of the grid fundamental frequency [16], ωi = 1%·2πfo = π rad/s is set. Kp = 0.48 is chosen for a target fc = 1.3 kHz, and then Kr = 65 is designed to achieve PM = 45◦ . For digital implementation, PR regulator is typically decomposed into two simple integrators, and the direct integrator is discretized with forward difference while the feedback one is discretized with backward difference [30]. In this way, the corresponding discrete transfer function of Gi (s) is obtained as 2Kr ωi Ts (z − 1) . +z + 2ωi Ts − 2) − 2ωi Ts + 1 (16) Hi1 is designed to achieve proper resonance damping with reasonable gain margins, typically 3 dB [13]. For the capacitorGi (z) = Kp +

z2

(ωo2 Ts2

Fig. 10. Closed-loop pole maps for different λ with grid-impedance variations. (a) λ = 1. (b) λ = 0.5.

current-feedback active damping with one-sample computation delay (λ = 1), there might be multiple −180◦ crossings (i.e., fr and fs /6), and the gain margin at each −180◦ crossover frequency must be concerned. Note that fr > fs /6 in the design example, according to Section III-B, GM1 < −3 dB and GM2 > 3 dB are both required in this case. From (12) and (13), the satisfactory range of Hi1 can be calculated as (0.004, 0.041). Thus, the value of Hi1 = 0.02 is chosen. For the capacitor-current-feedback active damping with reduced computation delay, 0.1 ≤ λ ≤ 0.5 is evaluated here. Taking λ = 0.5 for instance, Hi1m = 0.042 can be calculated out from (14). To get rid of the open-loop unstable poles, Hi1 < 0.042 is required. In this case, the phase plot crosses over −180◦ only once near fs /6, thus a 3-dB gain margin at fs /6 is enough to ensure system stability. According to (8), solving −20lg|T (ej π /3 ,0.5)| > 3 yields Hi1 > 0.004. Therefore, Hi1 = 0.02 is also appropriate for λ = 0.5. Using this design procedure, it will be found the same Hi1 can also be used for the other λ in the range [0.1, 0.5].


Fig. 11.

Sampled capacitor currents for different λ. (a) λ = 1. (b) λ = 0.5. (c) λ = 0.1.

Fig. 12.

Steady-state experimental results under full load condition with L g = 0. (a) λ = 1. (b) λ = 0.5.

The Bode diagrams of compensated loop gain for λ = 1 and λ = 0.5 are shown in Fig. 9, where fc = 1.3 kHz and PM = 45◦ can be readily identified. For λ = 1, the magnitude above 0 dB is required to yield a positive crossing at fr ; and for λ = 0.5, there is no constraint on the magnitude at fr , since the open-loop unstable poles have been removed and the phase at fr is already well below −180◦ . The phase plots for λ = 1 and λ = 0.5 show quite different features. Specifically, for λ = 1, the phase plot crosses over −180◦ both at fr and fs /6, and the corresponding gain margins are GM1 = −9.13 dB and GM2 = 4.12 dB; and for λ = 0.5, the phase plot crosses over −180◦ near fs /6, and the corresponding gain margin is 4.28 dB. As seen, the 3-dB gain margin requirements are well satisfied in different cases. Fig. 10 shows the closed-loop pole maps with Lg varies up to 10% PU (the pair of closed-loop poles introduced by the PR regulator is not displayed since they vary little). For λ = 1, as shown in Fig. 10(a), the resonant poles move outside the unit circle for 180 μH < Lg < 750 μH, which corresponds to 2.7 kHz < fr < 3.5 kHz. As discussed in Section III-C, instability comes about when fr moves close to fs /6 (3.3 kHz), and further increasing Lg (even larger than 10% PU) makes the resonant poles track back inside the unit circle. And for λ = 0.5, as shown in Fig. 10(b), the resonant poles are well damped into the unit circle. The other λ in the range [0.1, 0.5] shows the same features as λ = 0.5, and thus it is not repeated here. VI. EXPERIMENTAL VERIFICATION A 6-kW prototype is built and tested in the lab. The PCC voltage vg , which is used in the PLL, is sensed by a voltage hall.

3423

TABLE II MEASURED RESULTS IN DIFFERENT CASES

The grid current iL 2 and capacitror current ic are separately sensed by two current halls. The controller is implemented in a TI TMS320F2812 DSP. Since the real grid contains uncertain grid impedance, a programmable ac source (Chroma 6590) is used to simulate the grid voltage in the experiments, and the grid impedance Lg is emulated by an external inductor. First of all, the sampled capacitor currents for different λ are presented to validate the theoretical analysis in Section IV-A. Using the view graph of Code Composer Studio, the sampled capacitor currents for λ = 1, λ = 0.5, and λ = 0.1 are given in Fig. 11. As seen, the measured results are in agreement with the simulation results given in Fig. 8, Moreover, the switching noise is rarely observed in the sampled capacitor currents. For Lg = 0, both the steady-state and transient responses are investigated for λ = 1 and 0.1 ≤ λ ≤ 0.5. Fig. 12 shows the steady-state experimental results under full-load condition, and Fig. 13 shows the transient experimental results when the grid current reference steps between half- and full-load, both for λ = 1 and λ = 0.5. Since rare differences can be observed in the grid current, the measured results in terms of fundamental amplitude error EA , total harmonic distortions (THDs), and percentage

3424


Fig. 13.

Transient experimental results when the grid current reference steps between half and full load with L g = 0. (a) λ = 1. (b) λ = 0.5.

Fig. 14.

Experimental results with L g = 220 μH. (a) λ = 1. (b) λ = 0.5.

overshoots (POs) are further presented in Table II to provide a more explicit comparison. As seen, EA is less than 0.4% in different cases. This is thanks to the PR regulator which has sufficiently high fundamental gain and thus ensures the tracking accuracy and suppresses the effect of the fundamental sampling error of the capacitor current (see Fig. 8). As for the THDs, for λ = 1, due to the dead-time effect, a certain amount of harmonics, which are mainly of low order, exists in the grid current. And for 0.1 ≤ λ ≤ 0.5, the THDs get higher due to that the samplinginduced low-order aliased harmonics of the capacitor current are injected into the control loop (see Fig. 8). Besides increasing the loop gains, this drawback can be overcome by selecting a proper λ. Note that, for λ = 0.5 and λ = 0.1, the increments of THDs are very little compared with λ = 1, thus they are preferred in practice. Moreover, since satisfactory stability margins are preserved in different cases, the measured POs are nearly the same. As discussed in Section V, in the case of λ = 1, instability arises for 180 μH < Lg < 750 μH. To draw the worst case, Lg = 220 μH, which corresponds to fr = 3.3 kHz, is chosen and tested, and the experimental results for λ = 1 and λ = 0.5 are given in Fig. 14. For λ = 1, as shown in Fig. 14(a), significant steady-state oscillation arises in the grid current, and the oscillation frequency is exactly fr = 3.3 kHz. This indicates instability and is in good agreement with the theoretical analysis. And for λ = 0.5, as shown in Fig. 14(b), the steady- state oscillation is absent, and a stable operation is retained. The same results can be obtained for the other λ in the range [0.1, 0.5], and thus are not repeated here. The experimental results show that, using the capacitor-current-feedback active damping with reduced com-

putation delay, the LCL-type grid-connected inverter remains satisfactory steady-state and transient performances, and exhibits high robustness against the grid-impedance variation at the same time. VII. CONCLUSION This paper identifies the role that the computation and PWM delays play in the effectiveness of capacitor-currentfeedback active damping for the LCL-type grid-connected inverter. A virtual impedance model is proposed to describe the damping performance. This virtual impedance consists of a resistor paralleled with a reactor. The virtual resistor damps the resonance peak of the LCL filter, and the virtual reactor changes the resonance frequency. If the actual resonance frequency is higher than one-sixth of the sampling frequency (fs /6), where the virtual resistor is negative, a pair of open-loop unstable poles will be generated. The open-loop unstable poles make the LCL-type grid-connected inverter much easier to be unstable if the resonance frequency is moved closer to fs /6 due to the variation of grid impedance. This paper addresses this issue by shifting the capacitor current sampling instant towards the PWM reference update instant. And it is recommended to locate the capacitor current sampling instant either in the middle of the sampling period or much closer to the PWM reference update instant to reduce the sampling-induced low-order aliased harmonics. With this method, the LCL-type grid-connected inverter remains satisfactory steady-state and transient performances, and exhibits high robustness against the grid-impedance variation at the same time.


APPENDIX A

as

Referring to Fig. 3, the transfer functions from the inverter output voltage vinv (s) to the grid current iL 2 (s) and the capacitor current ic (s) can be derived as GiL 2 (s) = Gic (s) =

1 1 iL 2 (s) = · , vinv (s) sL1 (L2 + Lg ) C s2 + ωr2 1 ic (s) s2 = · 2 . vinv (s) sL1 s + ωr2

3425

(A1.1)

Hi1c =

ωr L1 (2 cos ωr Ts − 1) . KPW M sin ωr Ts

Second, the existence conditions of the open-loop unstable poles are derived. Apparently, the open-loop unstable poles of T (z,1) can only exist in the roots of Den(z) = 0. To check the root location, we take the w transform z = (1+w)/(1−w) to map the area outside the unit circle in the z-plane into the right-half plane in the w-plane. In this way, Den(w) can be expressed as

Applying ZOH transform to GiL 2 (s) and Gic (s)e−sλT s yields ZZOH [GiL 2 (s)] =

Den (w) = Den (z)|z = 1 + w =

Ts (L1 + L2 + Lg ) (z − 1) −

·

sin ωr Ts ωr (L1 + L2 + Lg )

z2

z sin (1 − λ) ωr Ts + sin λωr Ts . z (z 2 − 2z cos ωr Ts + 1)

In the z-domain, Gi (s) and Gd (s) are replaced by their discrete representations Gi (z) and Gd (z) = z −1 . Thus, the loop gain can be obtained as (A1.3), shown at the bottom of this page. APPENDIX B First, the value of Hi1 yielding fr = fs /6, Hi1c , is derived. Extracting the partial factor from the denominator of T (z,1): Den (z) = z z 2 − 2z cos ωr Ts + 1 Hi1 KPW M (z − 1) sin ωr Ts . ωr L1

(A2.1)

At the actual resonance frequency fr , a pair of resonant poles, which is z1,2 = e±j 2π f r T s , exists in T (z, 1). Forfr = fs /6, z1,2 are √ 3 1 . (A2.2) z1,2 = ± j 2 2 Obviously, z1,2 are the roots of Den(z) = 0. Substituting (A2.2) into (A2.1), and solving Den(z1,2 ) = 0, Hi1c is obtained T (z, λ) =

(1 − w)3

(A2.4)

where

(A1.2)

+

2 a3 w3 + a2 w2 + a1 w + a0

1 −w

z−1 , − 2z cos ωr Ts + 1

z−1 ZZOH Gic (s) e−sλT s = ωr L1 ·

(A2.3)

⎧ Hi1 KPW M sin ωr Ts ⎪ ⎪ a3 = 1 + cos ωr Ts + ⎪ ⎪ ωr L1 ⎪ ⎪ ⎪ ⎪ ⎪ ⎪ ⎪ ⎨ a2 = 1 + cos ωr Ts − 2Hi1 KPW M sin ωr Ts ωr L1 . ⎪ ⎪ ⎪ Hi1 KPW M sin ωr Ts ⎪ ⎪ a1 = 1 − cos ωr Ts + ⎪ ⎪ ⎪ ωr L1 ⎪ ⎪ ⎪ ⎩ a0 = 1 − cos ωr Ts

(A2.5)

For fr < fs /2 and Hi1 > 0, a3 > 0 and a1 > a0 > 0 are obtained. According to Routh’s Method, the Routh array of the characteristic equation a3 w3 + a2 w2 + a1 w + a0 = 0 is w3 : a3

a1

w2 : a2

a0

1

w : b1

0

(A2.6)

w0 : a0 where b1 = (a1 a2 −a0 a3 )/a2 . To avoid the right-half-plane roots for Den(w) = 0, which are also the open-loop unstable poles of T (z,1), the conditions of a2 ≥ 0 and b1 ≥ 0 must be satisfied. From (A2.5), we can obtain 0 < Hi1 ≤ Hi1c .

(A2.7)

Note that Hi1c > 0 for fr < fs /6 and Hi1c ≤ 0 for fr ≥fs /6. Therefore, if fr < fs /6, no open-loop unstable poles exist for 0 < Hi1 ≤Hi1c , and for Hi1 > Hi1c , there is at least one negative value between a2 and b1 ; thus, a pair of open-loop unstable

Hi2 Gi (z) z −1 KPW M ZZOH [GiL 2 (s)] 1 + Hi1 KPW M ZZOH [Gic (s) e−sλT s ]

ωr Ts z 2 − 2z cos ωr Ts + 1 − (z − 1)2 sin ωr Ts Hi2 KPW M Gi (z) · = ωr (L1 + L2 + Lg ) (z − 1) z (z 2 − 2z cos ω T + 1) + H i 1 K P W M (z − 1) [z sin (1 − λ) ω T + sin λω T ] r s r s r s ωr L1 (A1.3)

3426


poles is produced. And if fr ≥fs /6, there is certainly a pair of open-loop unstable poles for Hi1 > 0.

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struction and line current sampling delay reduction methods,” IEEE Trans. Power Electron., vol. 26, no. 8, pp. 2210–2220, Aug. 2011. B. P. McGrath, S. G. Parker, and D. G. Holmes, “High performance current regulation for low-pulse-ratio inverters,” IEEE Trans. Ind. Appl., vol. 49, no. 1, pp. 149–158, Jan./Feb. 2013. J. L. Agorreta, M. Borrega, J. López, and L. Marroyo, “Modeling and control of N-paralleled grid-connected inverters with LCL filter coupled due to grid impedance in PV plants,” IEEE Trans. Power Electron., vol. 26, no. 3, pp. 770–785, Mar. 2011. I. J. Gabe, V. F. Montagner, and H. Pinheiro, “Design and implementation of a robust current controller for VSI connected to the grid through an LCL filter,” IEEE Trans. Power Electron., vol. 24, no. 6, pp. 1444–1452, Jun. 2009. G. C. Goodwin, S. F. Graebe, and M. E. Salgado, Control System Design. Upper Saddle River, NJ, USA: Prentice-Hall, 2000, pp. 136–140. Y. A.-R. I. Mohamed, M. A. Rahman, and R. Seethapathy, “Robust linevoltage sensorless control and synchronization of LCL-filtered distributed generation inverters for high power quality grid,” IEEE Trans. Power Electron., vol. 27, no. 1, pp. 87–98, Jan. 2012. Texas Instruments, TMS320F2812 Digital Signal Processor. (2012). [Online]. Available: http://www.ti.com/lit/ds/symlink/tms320f2812.pdf H. Fujita, “A single-phase active filter using an H-bridge PWM converter with a sampling frequency quadruple of the switching frequency,” IEEE Trans. Power Electron., vol. 24, no. 4, pp. 934–941, Apr. 2009. W. Wu, Y. He, and F. Blaabjerg, “An LLCL power filter for single-phase grid-tied inverter,” IEEE Trans. Power Electron., vol. 27, no. 2, pp. 782– 789, Feb. 2012. ´ López, J. Malvar, and A. G. Yepes, F. D. Freijedo, J. D. Gandoy, O. P. F. Comesaña, “Effects of discretization methods on the performance of resonant controllers,” IEEE Trans. Power Electron., vol. 25, no. 7, pp. 1692–1712, Jul. 2010. Donghua Pan (S’12) was born in Hubei Province, China, in 1987. He received the B.S. degree in electrical and electronic engineering from the Huazhong University of Science and Technology, Wuhan, China, in 2010, where he is currently working toward the Ph.D. degree. His current research interests include magnetic integration technique and renewable energy generation system.

Xinbo Ruan (M’97–SM’02) was born in Hubei Province, China, in 1970. He received the B.S. and Ph.D. degrees in electrical engineering from the Nanjing University of Aeronautics and Astronautics (NUAA), Nanjing, China, in 1991 and 1996, respectively. In 1996, he joined the Faculty of Electrical Engineering Teaching and Research Division, NUAA, where he became a Professor in the College of Automation Engineering in 2002 and has been engaged in teaching and research in the field of power electronics. From August to October 2007, he was a Research Fellow in the Department of Electronic and Information Engineering, Hong Kong Polytechnic University, Hong Kong. Since March 2008, he has been also with the School of Electrical and Electronic Engineering, Huazhong University of Science and Technology, China. He is a Guest Professor with Beijing Jiaotong University, Beijing, China, Hefei University of Technology, Hefei, China, and Wuhan University, Wuhan, China. He is the author or coauthor of four books and more than 100 technical papers published in journals and conferences. His main research interests include soft-switching dc–dc converters, soft-switching inverters, power factor correction converters, modeling the converters, power electronics system integration, and renewable energy generation system. Dr. Ruan received the Delta Scholarship by the Delta Environment and Education Fund in 2003 and the Special Appointed Professor of the Chang Jiang Scholars Program by the Ministry of Education, China, in 2007. Since 2005, he has been serving as Vice President of the China Power Supply Society, and since 2008, he has been a member of the Technical Committee on Renewable Energy Systems within the IEEE Industrial Electronics Society. He has been an Associate Editor for the IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS and the IEEE JOURNAL OF EMERGING AND SELECTED TOPICS ON POWER ELECTRONICS since 2011 and 2013, respectively. He is a Senior Member of the IEEE Power Electronics Society and the IEEE Industrial Electronics Society.


Chenlei Bao was born in Zhejiang Province, China, in 1987. He received the B.S. degree from the School of Electrical Engineering and Automation, Harbin Institute of Technology, Harbin, China, in 2010, and the M.S. degree in electrical and electronic engineering from the Huazhong University of Science and Technology, Wuhan, China, in 2013. He is currently an electrical engineer in Shanghai Marine Equipment Research Institute, Shanghai, China. His current research interests include digital control technique and renewable energy generation system.

Xuehua Wang (M’12) was born in Hubei Province, China, in 1978. He received the B.S. degree in electrical engineering from Nanjing University of Technology, Nanjing, China, in 2001, and the M.S. and Ph.D. degrees in electrical engineering from Nanjing University of Aeronautics and Astronautics, Nanjing, China, in 2004 and 2008, respectively. He is currently a Lecturer in the School of Electrical and Electronic Engineering, Huazhong University of Science and Technology, China. His main research interests include multilevel inverter and renewable energy generation system.

Weiwei Li (S’12) was born in Henan Province, China, in 1987. He received the B.S. degree in electrical and electronic engineering from the Huazhong University of Science and Technology, Wuhan, China, in 2009, where he is currently working toward the Ph.D. degree. His current research interests include digital control technique and renewable energy generation system.

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