Carbon Nanofibers (CNF) for Enhanced Solder-based Nano-Scale Integration and on-chip Interconnect Solutions. V. Desmaris, A. M. Saleem, S. Shafiee, J. Berg, M. S. Kabir, A. Johansson Smoltek AB, Regnbagsgatan 3, 41755 Gothenburg, Sweden
[email protected] Phil Marcoux PPM Associates Mountain View, CA, USA.
Abstract While the density of chip-to-chip and chip-to-package component interconnections increases and their size decreases the ease of manufacture and the interconnection reliability are being dangerously reduced. This paper introduces the use of Carbon Nanofibers (CNF) grown on chip as an embedded reinforcing material for nanosolder interconnections and as bonding material (adhesive) for chip-to-package solutions. Interconnections are realized by means of microbumps which can be less than 10 m in diameter and up to 20 m high. Such micro-bumps are shown to be solderable using conventional thermal-compression and micro-bumps. Using CNF embedded in polymer is shown to provide a robust solution for chip-to-package interconnections. Introduction During the last two decades, the eventual ban of toxic SnPb solder for chip soldering lead to surge of alternative solder, which are nowadays well standardized and established [1-3]. However the continuous increase of the density of the chip-tochip and chip-to-package, as consequence of Moore’s law [4] make lead-free solders more challenging to implement, since the interconnect pitch get smaller and the current and power densities, that they should handle, larger. In addition, the interconnect reliability is dangerously being reduced as well because of warpage and heat. Beside the potential toxicity, solders such as SnAgCu or Sn-Pb are still limited in by their relatively high temperature processing, excess growth of IMC and/or cost [5-6]. To mitigate these problems, composite solders have been suggested as prospective future solder material [7]. Nano materials such as nanoparticles [8], Carbon nanotubes (CNT) [9] or Carbon Nanofibers (CNF) [10] have been considered for forming alloyed interconnects. CNT-or CNF- reinforced solders have shown promising results, yet their implementation required complex processing including solder material transfer from one substrate to another or high temperature processing Because of the more controllable electrical DC andf RF behavior [11] of CNF as compare to CNT and their high resistance to corrosion, we present, in this paper, the use of CNF in the forms of solderable micro-bumps grown directly on chips, providing prospectively high aspect ratio bumps with diameter in the order of 10-20 micrometers. In addition we
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show that CNF can be used as adhesive in combination with polymers and provide good mechanical connection to packages such as lead-frame or PCB. CNF on chip Using Smoltek’s patented technology, CNFs are produced using DC Plasma Enhanced Chemical Vapor Deposition (Fig.1.) at a temperature of 390 C, which is considered at present to be a CMOS compatible process temperature. The growth process itself is of catalytic nature, which allows full control of the placement of the CNF over chips. Therefore The CNF formation process includes the deposition and patterning of a catalyst before growth an environment containing ammonia and acetylene as a Carbon precursor. The use of a DC-plasma yield vertically aligned CNF of typically 50-100 nm in diameter and 2-150 micrometers in lengths (Fig.2Fig3.).
Figure 1. A high resolution of image of the carbon nanofibers reveals the diameter ranging from 20-100nm
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2014 Electronic Components & Technology Conference
Figure 2. A high resolution of image of the carbon nanofibers reveals the diameter ranging from 20-100nm
Figure 4. TEM Cross sectional view of CNFs rooted in a metal pad and wetted with Ind290 solder.
Figure 3. A forest of CNFs grown onto a metal IC bond pad. The pad size is approximately 20µm x 20 µm. Wetability of CNF The CNF were first grown as a film on Al-coated Si-chip to verify their wetability with low temperature solders such as Ind290 [12]. Regardless of an eventual coating the CNF were shown to wet very well the solder. As shown on Fig. 4.,the TEM analysis of a cross section of the Solder-CNF composite did not reveal the presence of voids, which would be compromising the reliability of the interconnects made out of it. In addition, the wetability of the CNF to the solder could prevent the solder from wicking out and away from the pads, thus reducing the number of solder shorts that occur as the solder pad-pad pitch gets smaller.
CNF as solderable micro-bumps The considerable Young Modulus of the CNFs along their growth axis confer them remarkable piercing properties, e.g. for nano-imprinting [13]. In addition, the CNF remarkable compressive strength would imply that they could provide considerable reinforcement of a solder bump, preventing it to deform and dimple during testing [14]. The demonstration of solderable micro-bumps was conducted using standard thermal compression flip-chip technique and test vehicle made of a readout wafer with 40 micrometer In-Sn solder bumps. Two set of samples were used for these experiments: uniformly Al-coated Si chips and Al-patterned Si chips. The CNF were grown at 390 C for both type of samples yielding either CNF films or CNF micro-bumps. The CNF, were later coated with Au, using sputtering. The Au-coated CNF films were flip-chipped to the read out using a NILT Nanoimprint CNI system under vacuum, whereas the Si Chips with micro CNF-bumps were flipchipped at 180 C using a conventional SET FC 150 flip-chip bonder and later reflowed at 170 C for 7 min as illustrated on Fig.5.
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The transfer of CNFs from their original substrate to micro-solder bump confirmed by inspecting the original substrate in SEM after disassembling (Fig. 7.). Clearly, the original substrate show large areas, from which fibers are missing, which support the idea that the fibers are embedded into the solder.
Figure7. SEM picture of the original substrate after disassembly, covered with a film of CNF, except where it was in contact with the solder
Figure 5. Schematic view of the micro-bump soldering. Upon disassembly, the wetting of the fibers to the In-Sn solder was investigated using SEM. As shown on Fig 6, fibers inclusions in the solder are visible indicating the solder did wet the Au-coated fibers and formed an interconnection.
Figure 6. SEM picture of the top of the In-Sn bumps after disassembly.
The electrical behavior of the interconnection was tested using the chips with CNF films and compared to the electrical behavior of chips without any CNF (Au coated Si). The results of 2 point resistance measurements performed with a Keithley 4200-SCS parameter analyser and a DC-probe station are summarized on Fig 8 and Fig 9. The measured resistances for chips with Au-coated CNF or solely Au are similar. This indicate that it is possible to make solderable CNF microbumps, without compromising the electrical quality of the interconnects.
Figure 8. Electrical characteristics of the solder bumps on bare metal (i.e. without CNF)
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Figure 11. SiC power transistor with nanofibers bonded to a DCB substrate Figure 9. Electrical characteristics of the solder bumps on with embedded CNF CNF-based adhesives interconnects CNF films can also be used as performance enhancer of flip-chip bonding, when soldering processes could not be used. For this purpose, CNF were first grown at the backside of SiC power transistors. Then, a low-temperature polymer was used to bond the fiber-covered transistor (back sides) to substrates. A double-layer of polymer was spun onto the fibercovered transistor chip, and the chip was bonded to different substrates, namely a Si-chip with measurement lines made of electroplated Gold (Fig. 10.) and direct-copper-bonding (DCB) substrates (Fig. 11.). The SiC chips were bonded to the substrates for 5 min at 160 C under a bonding pressure of 50 bar.
Electrical measurements were carried out using Keithley instrument both for two and four probe measurements. Representative results from four probe measurements are presented in Figure 12.
Figure 12. IV characteristics of the interconnect between SiC power transistor with nanofibers bonded and the silicon substrate
Figure 10. SiC power transistor with nanofibers bonded to a silicon substrate
The interconnection between the SiC chip and the Sisubstrate exhibit good ohmic behavior, whereas the bonding to the DCB substrate shows some non-linearity. This behavior can be ascribed to the large RMS surface roughness of the substrates (~12 micrometers) as compared to the fiber length (2 um). Taking advantage of the Transmission Line Measurements [15] configuration of the Si-chip, and using a simple resistance to model the interconnect behavior (Fig. 13.), the resistance value showed 21 mΩ per contact points with linear IV proving the fact that it is possible to utilize CNF on SiC substrate for Flip Chip bonding with good ohmic contacts. Specifically, the resistance per contact point was found to be of the order of
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9·10-5 Ω·cm2 which is within the frame of electrical requirements for FC bumping purposes.
very suitable for the formation of short pitch chip-to-chip interconnects. In addition, the use of embedded CNF into polymer to enhance the performance of the Chip-to-package interconnect has been demonstrate in terms of electrical performance. Furthermore, prototype assemblies made of Si power devices attached to Ag coated leadframe was confirmed to perform beyond the MILx1 standards in terms of mechanical strength. Acknowledgments The authors would like to acknowledge the Swedish Governmental Agency for Innovation Systems (VINNOVA) for its financial support regarding the CNF-based Adhesives for SiC devices.
Figure 13. Schematic of the model used for specific resistance extraction The mechanical strength of the CNF-based adhesive was investigated using small Si transistor chips bonded to Ag plated leadframe (Fig. 14.). The Si mechanical dies were 1.45x1.45 mm. CNF were grown at the backside of the chips before being attached to the leadframe using double layer of. A double-layer of polymer was spun onto the fiber-covered transistor chip. The Si chips were bonded to the substrates for 5 min at 160 C under a bonding pressure of 50 bar.
Figure 14. Si chips on Ag plated leadframe Statistics of the minimum shear force required to detach the chips from the leadframe were taken on 10 samples and lead to an average of 2300g and sample standard deviation of 0,497g. The obtained results qualify the assembly as MIL x1 according to the MIL-STD-883 standard for microelectronic devices. Conclusions Prospective CNF-based solutions for next generation of interconnects have been presented. Solderable CNF Micro-bumps with high aspect ratio have been demonstrated and resulted in interconnects made of CNF reinforced In-Sn solder composite. We believe this approach is
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