Carbon nanotube field effect transistors: toward future

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International Journal of Computers and Applications

ISSN: 1206-212X (Print) 1925-7074 (Online) Journal homepage: http://www.tandfonline.com/loi/tjca20

Carbon nanotube field effect transistors: toward future nanoscale electronics Felix Obite, Geoffrey Ijeomah & Joseph Stephen Bassi To cite this article: Felix Obite, Geoffrey Ijeomah & Joseph Stephen Bassi (2018): Carbon nanotube field effect transistors: toward future nanoscale electronics, International Journal of Computers and Applications, DOI: 10.1080/1206212X.2017.1415111 To link to this article: https://doi.org/10.1080/1206212X.2017.1415111

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Date: 04 January 2018, At: 01:37

International Journal of Computers and Applications, 2018 https://doi.org/10.1080/1206212X.2017.1415111

Carbon nanotube field effect transistors: toward future nanoscale electronics Felix Obitea,b  , Geoffrey Ijeomahc 

and Joseph Stephen Bassia 

a

Faculty of Electrical Engineering, Universiti Teknologi Malaysia, Johor, Malaysia; bFaculty of Physical Science, Department of Physics, Ahmadu Bello University, Zaria, Nigeria; cFaculty of Electrical & Electronics Engineering, Universiti Malaysia Pahang, Pahang, Malaysia

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ABSTRACT

As the scaling down of silicon MOSFET is approaching its utmost limit, different materials are effectively being examined in order to keep the scaling trend. Among these, carbon nanotubes (CNTs) have emerged as one of the most extensively studied materials due to their excellent performance properties such as minimal short channel effects, high mobility, and high normalized drive currents. CNTs are the backbone of carbon nanotube field effect transistor, which is considered as the most preferred candidate for the replacement of silicon transistors. Despite their practical significance, a well-organized framework, and consistent review are still lacking. To this end, this paper presents an intensive review in order to define the state of the art in this field from a fresh and unifying viewpoint while elucidating fruitful insights into recent advances and future trends. In particular, we review material properties and structures. Specifically, we emphasize on the most relevant device fabrication and current modeling concepts. Furthermore, we distill key insights into recent advances and challenges that may sustain or expand future applications. The future research directions are also carefully analyzed.

1. Introduction Over the past decades, the electronics field has witnessed a rapid miniaturization of transistors [1] with the number of transistors embedded in an IC chip multiplying every two years [2–5]. As the device channel lengths reach the sub –10 nm era, severe short channel effects, and direct tunneling between source and drain constitute a major challenge in the increased scaling of silicon devices. Therefore, remarkable research efforts have been carried out recently by several research bodies for integrating novel semiconductors as the channel material that can enable higher mobility and enhanced electrostatics at the nanoscale [6–9]. The integration of new materials, like high-k gate dielectrics and several metals, has been the driving factor leading the evolutionary path of CMOS scaling [2–5]. The drive behind the development of CNT technology is the awareness that the silicon-based CMOS technology will soon reach its absolute limits by the year 2020 [10,11]. Rather than continuous scaling of silicon, improvements in transistor performance and speed will have to come from new materials [11,12]. Bearing in mind the 2020 target, researchers from the academia and industry started to work actively on emerging prospects [11].

CONTACT  Felix Obite 

[email protected]

© 2018 Informa UK Limited, trading as Taylor & Francis Group

ARTICLE HISTORY

Received 30 August 2016 Accepted 6 December 2017 KEYWORDS

Carbon nanotube; field effect transistors; nanoscale electronics; silicon MOSFET

The international technology roadmap for semiconductor (ITRS) supervises the progress in the semiconductor industry. The ITRS working group in 2008, realized the need and presented to its working committee to investigate any current techniques and technology beyond CMOS [10]. After a thorough evaluation of all possible emerging devices, the working committee recommended carbon-based nanoelectronics, specifically CNTs and graphene as the promising future technology. The main reasons for the recommendation are informed by CNTs and graphene excellent performance properties such as minimal short channel effects, high mobility, and high normalized drive currents [13–16]. CNT technology is projected to overtake the technology of silicon-based CMOS and is the most preferred option that can withstand scaling up to 5 nm. IBM and Stanford research scientists have reported the best sub 10  nm silicon-based FET and tunnel FET [17,18]. The CNT technology showed appreciable results when scaled from 8 nm to 5 nm node compared to other alternatives. CNTs form the pillar of carbon nanotube field effect transistors (CNTFETs). Further experiments with CNTFETs [19–21] have shown that CNT-based transistors have high

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conductance which shows a big potential for sub-nanometer integrated circuits [22]. It has been proposed that high-k dielectrics are important for next-generation transistors due to reduced power dissipation and low leakage currents [23,24]. Nevertheless, for conventional semiconductors, a major setback is the degradation of electrical characteristics due to the introduction of carrier scattering mechanism at the high-k semiconductor interface [25]. It was recorded recently [26–29] that CNTFETs with high-k dielectrics can be operated in a ballistic range, thereby leading the path to ultrafast devices since the high-k dielectrics and ballistic transport of electrons both facilitate high on-current which is directly proportional to the transistor speed. CNTFETs were fabricated initially on oxidized silicon substrates [19,30]. Their applications were limited as a result of poor gate coupling due to a thick SiO2 layer and back gate geometry. However, the application of top-gate geometry in 2002 [20,31] made CNTFET a more promising option for next-generation FETs. Both p-type and n-type CNTFETs were developed [29] and verified for performance similar to MOSFETs. Currently, with better processing methods, CNTFETs with high carrier mobility and very high ON/OFF switching ratio have been fabricated [32–36]. Also, fabrication of inverters made of p-type and n-type CNTFETs was presented in [37,38]. Recently, a fabrication of doping-free CNT-based ballistic CMOS devices and circuits was proposed by [39], which are well-suited to CMOS current fabrication processes. CNTFET-based biosensors [40,41] have recently been studied extensively for biomolecular detection. A number of review articles have been published in the literature on CNTFET [42–48], and several of them

have generated a significant impact on research and commercial use. However, a well-organized framework and consistent review are still lacking. Considering the relevance of CNTFETs, and to further advance its fascinating properties, this paper presents an intensive review in order to define the state of the art from a renewed and unifying perspective while given fruitful insights into recent advances and future prospects. The remaining parts of this paper are organized as follows. In Section 2 we elaborate on material properties and structures. The most relevant device fabrication techniques are discussed in Section 3. Section 4 covers the most current modeling concepts for CNTFETs. Section 5 is devoted to recent advances and challenges that may sustain or expand future applications. Finally, we conclude the overview in Section 6, with fruitful insights into future research directions.

2.  The background 2.1.  Material properties and structure of CNTs CNTs can be considered as continuous hollow tubes made up of the flexible graphite sheet, based on the graphite sheet layer number, they are separated into single-walled carbon nanotubes (SWCNTs) and multi-walled carbon nanotubes (MWCNTs) [49–51], as appeared in Figure 1(a) and (b). Basically, SWCNT is a molecular single nanomaterial, which is composed of only a layer that spools a single graphite sheet into a continuous molecular cylinder. Its length and diameter distribution are within the range of 1–50 μm and 0.75–3 nm, respectively. Although MWCNT is made up of several curly graphite sheet layers and has its diameter ranging from 2 to 30 nm and in some cases greater than 100 in Figure 1(b) [52], the individual layer

Figure 1. (a) SWCNTs schematics which is made up of a curly graphite single layer. (b) MWCNTs schematics. Source: Reprinted from [51], Copyright 2014, Elsevier.

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distance is about 0.42 nm. We can picture the structure of SWCNTs as shown in Figure 2, the graphene plane is mapped into the cylinder without deforming the hexagonal graphene structure. An illustration of the vector from A to A′ is given in Equation (1).

will exhibit metallic characteristic from the semiconductor. The armchair CNTs possesses the most stable structure with metallic attributes [56].

(1)

The CNTFETs were developed initially at Delft University by Dekker’s group and by IBM for a suitable back gate geometry [19,30]. Though the device (Figure 4) is like the silicon-based FET as shown in Figure 5 [30], the full device physics vary differently [58,59]. In silicon-based FETs, carriers are produced from dopants levels through thermal excitation, and the FET polarity is dictated by the kind of dopants, either an n-type (donor) or p-type (acceptor) [60]. While in a CNTFET, the condition is practically different. This is due to the fact that CNTs are inherently intrinsic whereby stable or substitutional doping is not feasible [61–63]. Thus, it is very difficult for controlled doping in CNT, which hindered the development of CNT into a high-performance CMOS technology for quite a while [64]. Since in CNT, the high carrier mobility is as a result of steady and perfect sp2 CNT structure, and the dopants introduction in the CNT would interfere the otherwise stable structure and compromise its electrical characteristics, leading to lower carrier mobility, stronger scattering, and hence reduce performance [64]. Figure 6(a) shows a self-aligned previously developed top-gate structure [67] used for both n-type and p-type FETs fabrication. The CNTFETs contact metal determines the polarity, i.e. Sc for n-type [39] and Pd for p-type [28]. For a semiconducting CNT, the conduction and valence bands are symmetric close to the Fermi level, while for both n-and p-contacts the carrier injection efficiency is at the same level [68]. From Figure 6(b)–(d), the n-type and p-type CNTFETs display nearly symmetric electronic properties and high simultaneous performance, with peak transconductances exceeding 15 μS and up to 15 μA saturation currents at 1.0 V bias [69]. Figure 6(d) illustrates the output characteristics of these devices, which, shows the nearly symmetric Ids – Vds curve for a given p-and n-FETs, varying from 0 to 1.0 V in steps of 0.2 V under various gate voltages. The performance metric of the gate delay generally describes the intrinsic speed of the FETs, defined as 𝜏 = CV ∕I , where C denotes total gate capacitance, the applied voltage is V = Vds, and the ON-state current is I = Ion [70]. The diameter (d) of the semiconducting CNT channel is 1.8 nm, and the thickness (t) of the thin film gate dielectric (HfO2 ) is 12 nm with an εr of 18. Thus C was obtained to be 1.71 pF cm−1 [69]. From Figure 6(b) and (c), the threshold voltage Vth is extracted using the peak transconductance approach [70]

Ĉ h = n̄a1 + m̄a2

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where Ĉ h denotes a linear combination of the lattice basis vectors, the lattice basis vectors are ā 1, ā 2, n and m represent the positive integers which are called the chiral indices. While rolling the graphene sheet, there is an overlap of carbon atom A on the carbon atom A′, thereby forming CNTs. Once (n, m) integers are defined, the CNT structure is determined completely. All SWCNTs structural parameters can be evaluated using (n, m) index [53,54]. Based on the specific winding direction, SWCNTs are segmented into three specific structure types: armchair, zigzag, and chiral types, respectively [51]. The CNT structure types are related to their (n, m) chiral vector and the θ spiral angle. As depicted in Figure 3, if n = m, the spiral angle is 300 between Ĉ h chiral vector and ā 1 lattice vector, this type of CNT is known as armchair; and if m = 0 and 𝜃 = 0, the CNT type is called zigzag; and if 0 < 𝜃 < 300 , the CNT type is known as chiral. The electrical characteristics of SWCNTs largely depend on chirality and diameter [55], thus the diameter d is expressed as √ |C| a d= = (n2 + nm + m2 (2) 𝜋

where a denotes the adjacent distance of separation between two carbon atoms. The CNTs possess both metallic and semiconducting attributes. The energy band gap of semiconducting SWCNTs is inversely proportional to the diameter. When the diameter d is very large, the energy gap is approximately zero, and the SWCNTs conductivity

Figure 2.  The schematic structural diagram of CNTs, where the basis vectors are indicated by ā 1 and ā 2. The SWCNTs structure is determined by (n, m) index. Source: Reprinted from [51,57], Copyright 2014, Elsevier.

2.2.  Basics and structure of CNTFETs

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Figure 3.  Examples of three different types of CNTs. Source: Adapted and Reprinted from [51,57], Copyright 2014, Elsevier.

Figure 4.  CNTFET schematic showing the first back-gate developed by IBM group. Source: Reprinted from [65], Copyright 2009, John Wiley & Sons, Inc.

Figure 5. Silicon-based FET device geometry. Source: Reprinted from [66], Copyright 2011, Nature Nanotechnology.

and recorded 0.05 V for p-FET and n-FET is 0.03 V [69]. To achieve an ideal threshold voltage, a Pd metal is used as the top gate, which adjusts the threshold voltage efficiently.

Thus, the excellent performance and symmetric CNTFETs with ideal threshold voltages provide the perfect building blocks for fabricating CNT-based Integrated Circuits [69]. There are four basic kinds of CNTFETs, in particular, S-B CNTFET, Partially gated CNTFET, C-CNTFET, and T-CNTFET [44]. Figure 7(a) demonstrates the Schottky barrier-CNTFET in which the channel comprises intrinsic CNT having a metal contact at the source and drain sides directly. Ambipolar properties are observed since the channel is intrinsic throughout. A number of techniques are implemented to withstand ambipolar effects [71]. There is an observation of ION for both positive and negative bias gate since hole injection occurs at positive bias gate and electron injection at negative bias gate. The hole injection current is smaller compared to electron injection which depends little on drain voltage. The width and height of the Schottky barrier are essential as electrons and holes can tunnel from metal into the CNT channel directly. The main drawback of SB-CNTFET is that the inverse sub-threshold slope value is usually higher than the theoretical threshold (60 mV/dec) [72]. Partially gated CNTFET in (Figure 7(b)) is the second type where the channel is uniformly doped or intrinsic (p or n). As uniform doping exists throughout the channel, the device works in depletion mode. They display n-type or p-type behavior depending on the doping type. There is an improvement in the device characteristics with ohmic contacts. In such devices, the ION is limited by a source exhaustion phenomenon [31]. Schottky barriers are created at the source and drain region when the channel is intrinsic throughout, though the effects of the Schottky barriers are not significant due to the partial gate. It operates also in enhancement mode. The third type is C-CNTFET (Figure 8(a)). The structure is similar to conventional MOSFET so it is called conventional CNTFET. The ungated channel comprises intrinsic CNTFET while the source and the drain are doped heavily. There is an improvement in the device characteristics as a result of doping with unipolar properties being observed at low OFF current (IOFF ). The ION is also limited by the quantity of charge that may be induced by the gate in the channel and not by the source doping [5]. Due to deficiency of Schottky barrier, the OFF current is limited by thermal emission rather than direct tunneling which gives appreciable inverse subthreshold slope values (60 Mv/dec). T-CNTFET is the fourth type (Figure 8(b)). A T-CNTFET structure is achieved by introducing a p-i-n or n-i-p doping profile through the CNT channel. The device works based on tunneling principle hence the name T-CNTFET. Even though tunneling behavior is unsafe in CNTFET it can be of benefit in T-CNTFET using the gate voltage to control the tunneling [73]. Band to band tunneling current is modulated by gate voltage in this device

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Figure 6. Geometry and characteristics of CNTFETs. (a) Scanning electron microscope (SEM) image of both p-and-n-FETs with a scale bar of 10 μm. (b) and (c) are p-FET and n-FET transfer characteristics with approximately 1.8 nm diameter and approximately 1 μm channel length. (d) The CNTFETs output characteristics for p-type (green lines) and n-type (blue lines) with varying Vgs from 0 to 1 V in 0.2 V steps, from bottom to the top [67]. Source: Images are reprinted from the American Chemical Society, 2008.

Figure 7. (a) SB-CNTFET (b) Partial gated CNTFET. Source: Adapted from [44].

[74]. The major benefit of T-CNTFET is to attain inverse sub-threshold slope at room temperature lesser than 60 mV/dec. Nevertheless, there are several challenges to achieving the production of tunnel devices [75].

The devices are simulated using a device simulator known as Nano TCAD ViDES which is based on the principle of Non-Equilibrium Green Function (NEGF). As depicted in Figures 7 and 8, the length of the gate is LG, LS is the source-side CNT length and LD is the drain-side CNT length region, tox is the oxide thickness. The drain current IDS vs. the gate voltage VGS is illustrated in Figure 9(a) for SB-CNTFET having two dissimilar drain voltage (VDS) of 0.1 V and 0.5 V [44]. There is a great influence of VDS on the transfer characteristics since it works on tunneling from SB. Since CNT is intrinsic throughout, it has the characteristics of n-type and p-type for both positive and negative gate bias. For device working in the subthreshold region VDS = 0.1 V, as the gate bias is increased it works in n-type. But there is a great influence of VDS when it works in the saturation region. There is adequate low IOFF in this situation and the voltage at threshold is quite higher than the subthreshold region which keeps fluctuating with increasing VDS [44]. For a uniformly doped p-type CNT as channel, Figure 9(b) illustrates the IDS vs. VGS characteristics of partial gated CNTFET. This device works in depletion mode since the CNT is doped uniformly throughout the channel. Due to ohmic contacts, the device characteristics are improved over the intrinsic channel. The P-type device will turn off for negative gate bias, as holes repel from the channel.

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Figure 8. (a) C-CNTFET (b) T-CNTFET. Source: Adapted from [44].

enhancement mode and ION is higher due to the doping concentration at the source and drain terminal. There is also little VDS effect on transfer characteristics. The drawback of this device is charge accumulation occurring in the channel which makes it a leaky device [44]. Lastly, Figure 10(b) illustrates the transfer characteristics of T-CNTFET. The conduction in T-CNTFET occurs as a result of bandto-band tunneling and the nonexistence of charge accumulation makes it a novel device. Essential advantages are low IOFF and a sharper inverse subthreshold slope [76]. The major drawback is that there is high IOFF at higher VDS (0.5 V), but it is an ideal device at low VDS. From the simulation results, it is evident that CNTFET is a low power device which shows significant results at VDS = 0.1 V. The performance parameters were evaluated respectively at VDS = 0.5 V and VDS = 0.1 V. The highest ION/IOFF ratio was recorded by C-CNTFET, then Partial, Tunnel, and lastly Schottky. Similarly, Partial gated CNTFET responds to the highest transconductance followed by C-CNTFET, SB-CNTFET, and T-CNTFET [44].

3.  Fabrication of CNTFETs

Figure 9.  IDS − VDS characteristics for (a) SB-CNTFET (b) Partial gated CNTFET. Source: Adapted from [44].

Currently, there are several groups chasing the fabrication of CNTFET in different variations, making increasing progress in advancing performance limits, and also experiencing myriad issues, as anticipated for any innovation in its infancy. While the simplicity of manufacturing has significantly improved since their first implementation in 1998, there is still a long distance to cover before large scale integration and commercial application become feasible. CNTFETs were fabricated earlier using nanotubes integrated by a process of laser ablation utilizing nickel– cobalt catalysts [77]. The CNTs were further suspended in a solvent and distributed with predefined metal contact pads on an oxidized silicon wafer. The outcome was randomly distributed CNTs with some connecting the contacts. Afterward, catalytic chemical vapor deposition (CVD) techniques were adopted to grow CNTs [78, 79]. The CVD methods give more control over device fabrication and have prompted increasing advances in device performance [80–83]. Typically, CNTFET geometries are classified into two basic types, planar and coaxial [84]. 3.1.  Planar devices

Figure 10(a) shows the ideal characteristics of C-CNTFET. From simulation results, it is apparent that the characteristics are drastically improved with doping included in CNT source and drain region. For the current conduction, the gate control increases as the gate bias affect directly the charge developed inside the channel. The IOFF, in this case, is much lower than the others since the device works in

To date, the greater amount of CNTFETs fabricated are planar devices because of their relative simplicity and suitable compatibility with current technologies. The metallic source-drain and nanotube contacts are organized on a substrate insulation, with the contacts either being patterned over the nanotube, or the nanotube being draped over the pre-patterned contacts. In the former case, the

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Figure 10. IDS − VDS characteristics for (a) C-CNTFET (b) T-CNTFET. Source: Adapted from [44].

nanotubes are dispersed usually in a solution and moved to a substrate having pre-arranged electrodes. The first CNTFET devices reported in 1998 involved the simplest fabrication possible. They comprised of highly doped silicon back gates, glazed with thick SiO2 , and using either, Au or Pt patterned source-drain metal contacts as depicted in Figure 11. Analysis of several metals such as Ni, Ti, Pd, and Al, has been reported by different groups, to manipulate primarily the difference in work function between the nanotubes and the end contacts. Further work produced also a device that substituted the back gate by placing an electrode over the substrate, perpendicularly to the source and drain contacts as shown in Figure 12. Thus, the separation of the nanotube from the gate electrode is done using a thin layer of Al2 O2 insulation, with the strips of the source-drain electrodes placed over the ends of the tube for contact resistance reduction.

Figure 11.  Schematic side view of TubeFet device. Source: Reprinted from [19], Copyright 1998, Nature.

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Figure 13(a) illustrates a further CNTFET improvement by placing the gate electrode over nanotube, hence enhancing the channel electrostatics through the thin gate oxide. Furthermore, in this device, the Ti source-drain metallization form abrupt junctions of titanium carbide with the CNT, resulting in increased conductance. Another effort to achieve improved gate electrostatics use materials such as zirconia ZnO2 and hafnia HfO2 having high dielectric constants, being utilized as gate insulators [29]. Figure 13(b) shows a device developed with Pd source-drain contacts so as to exploit the material’s work function sensitivity to hydrogen. Recently, a multi-gate device has been reported as shown in Figure 13(c), where parallel top gates are utilized to control independently the electrostatics of several channel sections, thereby simplifying the transport characteristics study of the CNT channel. A device with outstanding DC features was fabricated more recently with Pd end contacts, hafnia, and Al gate insulation [26]. A local gated CNTFET has been reported most recently, as illustrated in Figure 14. The method is based on the individually directed assembly of SWCNT from dichloroethane through AC through AC dielectrophoresis to pre-patterned source and drain electrodes having a local Al gate in the middle. Local gated devices exhibit superior performance when compared to the global back gate having on-off ratios higher than and 170 mV/decade of maximum subthreshold swings. 3.2.  Coaxial devices Though not yet fabricated in ideal form, coaxial devices are of unique interest since their geometry permits improved electrostatics than the planar devices. Taking advantage of the cylindrical inherent structure of nanotubes. These devices can display wrap-around gates that exploit capacitive coupling between the nanotube channel and gate electrode. The first of such device was reported by [88] as illustrated in Figure 15(a) using a MWCNT for the channel. Two gates are initiated: an electrolyte gate; and a highly doped silicon back gate Figure 15(b), identical to planar devices; formed by LiClO4 electrolyte droplet in contact with a thin platinum wire Figure 15(c). Currently, the development of electrolyte-gated devices has been the nearest approximation to this geometry. An enhanced version of this device is shown in Figure 16, using SWCNTs and AgClNaCl as the electrolyte, resulting in a current–voltage characteristic that is similar to modern silicon MOSFETs. CNT alternative device structures that place the tube vertically towards the substrate have been used already for field emission technologies. Coaxial CNTFETs can be fashioned perhaps by inserting CNTs within the cavities of

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Figure 12.  Height image of the single-nanotube transistor and device schematic side view. Source: Images are reprinted from [13], Copyright 2001, Science.

a porous material like alumina, surrounded by electrolyte solution for individual device gating.

4.  Modeling of CNTFET An extensive variety of simulation techniques have been used for investigating the performance and properties of CNTFETs extending from atomistic first–principles techniques [90, 91], effective-mass Schrodinger-Poisson (SP) solver [92–94] and Boltzmann transport equation (BTE) [95–97] to compact models [98–100]. Their focus is just on single tube devices similar to the existing device numerical simulation techniques. Also, most methodologies adopt ohmic contacts and a perfect cylindrical structure with pin-like contacts. Atomistic techniques can be used for comprehensive analyses on functionalization effects and contact resistance, but are not suitable for the simulation of practical device useful structure. SP-based alternative techniques are restricted to device structures having short channels of about 200 nm maximum as a result of the computational exertion. Particularly time-dependent simulations are more challenging. An overview of this technique is presented in [94]. Usually, the numerical tools extremely long simulation run time restrict their suitability for device design. For more feasible practical devices with greater scattering probability and longer channels, BTE solver approach seems to be more suitable. The BTE can either

be solved using a Monte-Carlo technique [96] or directly [95]. The difficulty in finding appropriate contact models is common to all simulation techniques. The techniques range from a simple model of Schottky barrier [101] to more complex heterojunction models [101]. An extensive survey is discussed in [102]. For circuit design and analysis, compact models (SPICE models) [46, 99, 103–105] are used. These models depend on the ballistic transport principles. For devices working in the ballistic system, carriers move through the channel with little or no scattering activities as contrasting to the conventional drift and diffusion mode [46]. An energy barrier is created by the channel for the carriers. The carriers having adequate energy to overcome the obstacle can move through the channel and add to the current. Iterations are needed for calculating consistently the surface potential which is a major variable in evaluating the energy barrier and thus the S/D current in ballistic transport. Efforts on fast analytical solutions neglecting iterative calculation are presented in [100, 106–109] While the majority of the transport models presented above concentrate on intrinsic transport characteristics and how carriers occupy and move through the channel, the impact of parasitic components (parasitic capacitances and series resistances) cannot be neglected. Progress has been recorded to model parasitic capacitances analytically [99, 110] and resistances in series [91, 111, 112]. A combination of these models with intrinsic transport model can be implemented to achieve more desirable CNTFETs. A general method for evaluating the electron transport of single-tube CNTFET can be derived using the Landauer equation [113, 114].

ID =

) ] [ ( 4q ∞ ∫ Tn (W) fn W, WFS − fn (W, WFD ) dW (3) h −∞

where fn is the Fermi function of the electron and Tn(≤1) is the transmission factor of the electron between the S/D contact, which normally includes tunneling through the Schottky barriers and scattering within the tube. For an average energy independent transmission factor (Tn,av ), the rest of the integral can be analytically evaluated, given rise to the closed-form expression, [ ( ∗ )]) ( [ ( ∗ )] 𝜓t − VDS 𝜓t − ln 1 + exp ID = Tn,av Gq VT ln 1 + exp VT VT

(4)

VT is the thermal voltage, the quantum conductance per tube:

Gq = 4q2 ∕h = 1.55 μS

(5)

where ψt represent the potential of the tube surface and Wg1 is the conduction band edge of the first subband while

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higher current carrying capacity, high structural ruggedness, and low self-heating that qualifies CCNTFETs for next-generation electronic devices.

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5.  Recent advances and challenges Fast advances in CNTFET technology, enabled by high-k dielectric material and pass-transistor logic (PTL), can revolutionize the future wave highly integrated electronic devices that can convey remarkable computing capacity. While CMOS is the preferred choice of logic for silicon technology, CMOS inherently is not the most effective logic among those studied by researchers from academia and industry. A signal in CMOS logic is permitted to be added only to the gate, and not to the source and drain. This restriction largely limits CMOS efficiency, while in PTL, a signal might be added to any of the FET three terminals, thereby making it very effective [115, 116]. 5.1.  High-k dielectric material for CNTFETs

Figure 13.  (a) A schematic top gate CNTFET cross section illustrating the gate, and source and drain electrodes. Source: adapted from [85]. (b) Image of scanning electron microscope (SEM) left, and image of atomic force microscope (AFM) right. Source: Adapted from [28]. (c) A schematic segmented gate CNTFET cross section. Source: adapted from [86].

assuming the ideal case and similar to MOSFETs i.e. (i) neglecting the effect of S/D contact by way of functionalization and oxide charge on electrostatic potential (ii) similar work function for gate material and CNT, the gate voltage is related to the surface potential under the gate through the charge balance, � Qt� = Cox (VG� S� − 𝜓t )

(6)

′ where Qt′ tube is charge and Cox is the capacitance of the ′ gate oxide per tube length. Qt is very small at adequately low carrier injection into the tube, and hence ψt follows the internal GS voltage (VG′ S′) closely. For large sufficient, the drain current above the threshold voltage Vth (i.e. the ideal case of Wg1/2g defined earlier) is expressed as

ID = Tn,av Gq (𝜓t − Vth )

(7)

Thus, 𝜓t follows VG′ S′ and Tn,av is not dependent on the bias, ID linearly follows VG′ S′. It is the linearity together with

A high-quality gate dielectric with high (k) dielectric material is greatly desirable for all high-performance FETs [117, 118]. The channel current control in a FET is achieved through capacitance coupling between the channel and the gate, and the gate oxide contributes essentially in this phase. While the preferred oxide of choice is SiO2 Si O2 or the past four decades, since the discovery of the first MOS integrated circuit, the high-k material HfO2 was introduced in 2007 as a replacement for SiO2 at the 45 nm scaling. The reason behind the shift is that the speed of the device is proportional to the current of the device, which also is directly proportional to the capacitance of the gate given by;

Cox =

𝜀0 k tox

(8)

where ε0 denotes free space dielectric constant. An obvious option is to increase Cox using a high-k material in order to improve the performance of the device and escape gate leakage current during scaling, while the oxide thickness tox is kept constant. Even though HfO2 works better for silicon, such earlier high-k oxides are not suitable for growing very thin dielectric layers on sp2 nano-structured carbon structure. This is because the normal technique for the growth of gate oxide, such as ALD is not suitable for growing a high standard oxide layer on a perfect sp2 lattice layer, due to the absence of nucleation centers on the perfect lattice structure. Luckily, the initial study on the CNT contact shows that some metals, for instance, Sc [39] and Y [119] can wet with CNT, and easily oxidized to obtain an ultrathin oxide layer directly on sp2

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Figure 14.  Local gated CNTFET fabrication. (a) source-drain electrodes of 1μ separation are patterned on heavily doped substrates of Si∕SiO2 (250 nm thick oxide layer). (b) Local Al gate electrodes are patterned with EBL and 2–3  nm thick Al2 O3 is obtained by oxygen plasma treatment. (c) DEP assembly of CNT. An 8VP-P AC voltage is applied to the source electrode for 1–2 s with a function generation. (d) A resulting AFM image of a device displaying assembled nanotubes at the tips [87]. Source: Images are reprinted from IOP Publishing Ltd, 2008.

carbon [120]. A uniform yttria Y2 O3 layer can be created on SiO2 as shown in Figure 17(a) and its scanning electron microscope (SEM) is shown in Figure 17(b), which has been revealed to represent an ideal dielectric material for CNTFET, resulting to an ideal 60 meV/decade of sub-threshold swing at room temperature.

The CNT device diameter is 1.2 nm, the source to drain channel is 2 μm, and a gate electrode of 1 μm width is fabricated in the middle of the channel [120]. The electrical measurements were carried out at room temperature under a base pressure of 1 × 10–6 Torr in a vacuum chamber [120]. For Vgs up to2 V, the gate leakage current is less than 20 pA indicating a very high quality thin dielectric oxide (Y2 O3 ). Figure 17(c) and (d) illustrates a typical output and transfer characteristics of CNTFET. The Sc electrode creates an ohmic contact to the CNT conduction band presenting a free barrier electron injection into the FET. Thus, in Figure 17(c), perfect n-type transfer characteristics are required for a Sc-contacted FET [120]. A reasonably large back-gate bias VBG = 40 V is applied to the two ungated CNT segments between the top-gate finger and the source and drain electrode, in order to n-dope this region electrostatically. This high value of VBG retains the ungated channels of the CNT in their on-state, but the top-gate is used to turn off the CNT channel below the gate from its steady on-state. For Vds = 0.5 V, the device Ion ∕Ioff ratio can exceed five orders of magnitude, and the CNTFET normalized saturation current for Vds = 2 V and VTG = 1.4 V is as high as 6 mA∕μm (Figure 17(d)). The subthreshold swing SS and transconductance gm determine the switching property of a FET [121]. The 60 mV∕dec SS in Figure 17(c) represents an ideal transition between the ON and OFF states (i.e. for a perfect FET at room temperature up to a theoretical limit) [121]. 5.2.  Pass-transistor logic (PTL) A single FET in PTL, either an n-type or p-type is adequate to execute a logic operation, which reduces significantly the number of FETs utilized compared with using a configuration of conventional CMOS to accomplish the same

Figure 15. (a) Electrochemical gating with lithographically defined Au contacts evaporated over the nanotubes. (b) Silicon substrate used as a gate. (c) Nanotubes placed into an electrolyte for increased trans-conduction. (c). Source: Adapted from [88].

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Figure 16.  Schematic of the electrolyte gate measurement. A water gate voltage Vg is applied to droplet through a silver wire [89]. Source: Reprinted from The American Chemical Society, 2002.

function. The drawback with PTL is that a zero threshold voltage is required by the logic which is difficult to achieve in silicon technology where a considerable amount of the control is achieved by doping. For CNT technology, a perfect zero threshold voltage technology is achievable where the FET threshold voltage might be controlled by the gate with the injection of carriers from the contacts, thus possible to achieve the most complex logic functions realized on individual CNTs [11, 122]. Specifically, a three adder is designed employing three pairs of n-and p-type

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CNTFETs only; where 28 FETs could have been required using a CMOS configuration, allowing more simplified large circuits with fast speed and less power consumption. Figure 18(a) illustrates a semi-adder circuit using PTL. Figure 18(c) and (d) is the two outputs of the sum and carry, respectively, which follow the projected truth table given in Figure 18(b) exactly. An extensive study on CMOS-based carbon nanotube PTL integrated circuits is presented in [69]. While CNTFETs acquire some inherent reliability and variability shortcomings of silicon-based FETs, for instance, the ones coming from metal oxide deformities among others, solutions for reducing the cause of this nonuniformity have been investigated and proposed [123, 124]. A further challenge originates from non-perfect CNT growth control. As-grown CNTs normally contain both metallic and semiconducting CNTs, which are unsuitable for electronics devices. Nevertheless, rapid advances have been made recently in controlled removal of metallic CNTs [125], selective development of semiconducting-improved CNTs [126, 127], and CNT separation[35]. Specifically (99%) high purity semiconducting nanotubes have been attained [128–130], giving a perfect opportunity for utilizing CNT to advance the MOSFET in the direction of the roadmap.

Figure 17. Device geometry of a top-gate CNTFET with a thin layer of Y2 O3 as the top-gate dielectric. (a) Device structure schematic diagram. (b) Scanning electron microscope (SEM) image of CNTFET device. (c) Device transfer characteristics for Vds = 0.1, 0.3 and 0.5 V , respectively. (d) Device output characteristics for varying values of VTG (-1 bottom black to 1.4 V top purple) with a step of 0.2 V [120]. Source: Images are adapted and reprinted from The American Chemical Society, 2010.

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Figure 18. CNT PTL semi-adder circuit (a) schematic diagram and circuit equivalent diagram, and (b) the semi-adder circuit truth table. Normalized output voltage levels by a supply voltage of (c) SUM and (d) carry for all four inputs. Source: Reprinted from [11], Copyright 2014, Elsevier.

6.  Conclusion and future direction

Acknowledgements

CNTFETs are promising candidates for next-generation nanoscale electronic devices. The unique structural geometry and excellent electronic properties make them a high potential in high-performance digital circuits. In this paper, we have provided a solid, consistent, and state-of-the-art overview of CNTFET. To give insight into the distinct characteristics of CNTFETs, we have reviewed material properties and structures. We elaborate on the most relevant device fabrication and current modeling concepts. We also distilled key insights into recent advances and challenges that may sustain or expand future applications While considerable progress has been achieved, further advances are needed for CNTFET technology to facilitate circuits for high-performance applications such as (1) high-density CNT ≥200 CNTs per μm obtained on a wafer scale; (2) stable and effective CNT doping with control over doping levels on the same wafer; A low-resistance metal-CNT contacts at short contact lengths