Carbon Nanotube Interconnects for Low-Power High-Speed Applications Naushad Alam, A. K. Kureshi, Mohd. Hasan
T. Arslan
Aligarh Muslim University Aligarh, India {itsnaushad, akkureshi, m_hasan786}@rediffmail.com
University of Edinburgh United Kingdom
[email protected]
Abstract—This paper investigates the prospects of mixed bundle of Carbon Nanotubes (CNT) as low-power high-speed interconnects for future VLSI applications. The power dissipation and delay of CNT bundle interconnects are examined and compared with that of the Cu interconnects at the 32-nm technology node. We evaluated and compared various performance metrics of interconnects with both CMOS and Carbon Nanotube Field Effect Transistor (CNFET) driver and FO4 load using transmission line model. The results show that CNT bundle consumes 1.5 to 4 folds smaller power than Cu for intermediate and global interconnects. The CNT bundle interconnects are also faster than Cu except for local interconnects. It is concluded that the mixed bundle of CNTs is a promising candidate for intermediate and global interconnects in future technologies.
I.
INTRODUCTION
The sustaining of the Moore’s Law requires continued transistor scaling and performance improvement. As the fabrication technology move to finer very deep sub-micron (VDSM) design rules, the intrinsic gate delay tends to decrease significantly. In contrast, the overall chip size and worst case line length on a chip tend to increase, mainly due to increasing chip complexity; thus, the importance of interconnect delay increases in VDSM technologies. For example, the longest wire on a VLSI chip may be about 2 cm long [1]. The parasitic effects introduced by the wires display a scaling behavior that differ from the active devices such as transistors, and they tend to gain in importance as device dimensions are reduced and circuit speed is increased. Interconnects dominate some of the relevant metrics of digital integrated circuits such as speed, energy consumption, and reliability in VDSM [2]. In [3], it is shown that global interconnects consume over 50 % of the overall dynamic power of a high-performance microprocessor (77 million transistors), fabricated in 0.13-µm CMOS. The situation worsens further in deep submicron where interconnects constitute up to 70% of the total on-chip capacitance [4], and are the major source of power dissipation.
As interconnect feature size shrinks, copper resistivity increases due to surface and grain boundary scattering and also surface roughness [5]. The steep rise in parasitic resistance of copper interconnects poses serious challenge for interconnect delay. According to ITRS, the Cu wires are becoming more and more vulnerable to electromigration because of rapid increase in current density [6]. All these factors result in degraded interconnect performance with each technology generation which conflicts with the high performance requirement, such as low power, low interconnect delay and reliability of VLSI circuits in VDSM. To control the exacerbating problem of power dissipation, that has become the main limitation for virtually all digital chips, and delay of interconnects changes in material used for on-chip interconnects have been sought even in earlier technology generations, for example the transition from Aluminium to Copper some years back. Bundle of CNTs have recently been proposed as possible replacement for copper interconnects in future technologies due to its superior conductivity and current carrying capabilities [6]. Carbon nanotube is a graphene sheet rolled up into cylinder with diameter of the order of nanometer. Depending on the direction in which the sheet is rolled up (Chirality),resulting CNT demonstrates either metallic or semiconducting properties [7]. Because of its extremely desirable properties of high mechanical and thermal stability, high thermal conductivity and large current carrying capacity, CNT promises to be suitable candidate for interconnects in future VLSI circuits. However, the high resistance (of the order of 6.45 KΩ) associated with an isolated CNT [8] necessitates the use of a bundle of CNTs. A bundle of CNTs is generally a mixture of single-walled and multi-walled CNTs (SWCNTs and MWCNTs). A SWCNT consists of one graphene shell and has electron mean free paths of the order of a micron [8] and achieves ballistic transport over long lengths. If several SWCNTs with varying diameter are nested concentrically inside one another, the resulting structure is called a MWCNT and they are predominantly metallic in nature.
This work is funded by Royal Academy of Engineering, UK.
978-1-4244-3828-0/09/$25.00 ©2009 IEEE
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CNT BUNDLE CIRCUIT MODEL
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Fig. 1. Power Dissipation ratio for Cu and CNT bundle in local interconnect with CMOS and CNFET driver. Power Dissipation of Intermediate Interconnect 2.5 P (Cu) / P (CNT)
Mixed bundle of CNTs and Cu interconnects are modeled as an equivalent transmission line and the equivalent circuit parameters (R, L, C) were extracted, using Carbon Nanotube Interconnect Analyzer (CNIA) [9] and BPTM tools, based on the interconnect geometries suggested in [10] for 32-nm technology node. We evaluated and compared various performance metrics of interconnects with both CMOS and CNFET driver and FO4 load. To extract the circuit parameters of mixed CNT bundle interconnect a realistic nanotube density of 5 x 1012 tubes/cm2 has been considered. The resistance of mixed CNT bundle local interconnect is constant for its length (l) smaller than the mean-free path (λ) of CNT. This is because for l < λ, CNT operates in ballistic region and its quantum resistance is independent of the interconnect length, whereas, the resistance of copper wire is directly proportional to its length. While copper resistance increases linearly with its length, in case of CNT bundle interconnect, only the scattering resistance increases linearly but the quantum resistance is independent of the interconnect length. The quantum resistance is regarded as lumped and equally divided at the two ends of transmission line model while the scattering resistance is distributed over the length. The total capacitance of a CNT bundle is a bit complex, since each individual CNT in a bundle consists of two types of capacitance, the quantum capacitance (CQ), and electrostatic capacitance (CE) and the total capacitance of the CNT bundle depends on these two components. However, with CNIA tool [9] we were able to extract the total capacitance (CQ + CE) of the CNT bundle easily and we observed that for a given length of interconnect the CNT bundle has a smaller capacitance than its Cu counterpart. III.
Power Dissipation of Local Interconnect
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Fig. 2. Power Dissipation ratio for Cu and CNT bundle in intermediate interconnect with CMOS and CNFET driver. Power Dissipation of Global Interconnect P (Cu) / P (CNT)
II.
of interconnects using simulation runs with HSPICE at a frequency of 500MHz with Vdd = 0.9V. Fig. 1, 2, and Fig. 3 plot the ratio of dissipated power in Cu and CNT bundle for local, intermediate and global interconnects respectively with CMOS and CNFET drivers. Results show that the power dissipation of local copper interconnect is smaller than the corresponding CNT bundle. This is because for small length interconnect CNT bundle’s resistance & capacitance, domina-
P (Cu) / P (CNT)
This paper investigates the prospects of mixed bundle of CNTs as low-power high-speed interconnects for the future VLSI applications. To the best of our knowledge, this is the first effort to analyze the power dissipation of CNT interconnects and its comparison with copper interconnects. We also compare the delays of the bundle of CNTs and Cu interconnects at local, intermediate and global interconnect levels. The investigations have been based on simulation running with HSPICE for 32-nm technology node using Berkeley Predictive Technology Model (BPTM) for CMOS and Stanford model for Carbon Nanotube Field Effect Transistor (CNFET) driver and FO4 load. The rest of the paper is organized as follows. In section II, the circuit parameters are extracted for simulation, section III compares the power dissipation of interconnects and comparative delay analysis is presented in section IV. Section V concludes the paper.
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INTERCONNECT POWER DISSIPATION
The power dissipation analysis of interconnect is performed by using the extracted parameters in the equivalent transmission line model. We measure the power dissipation
CMOS Driver
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Fig. 3. Power Dissipation ratio for Cu and CNT bundle in global interconnect with CMOS and CNFET driver.
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ted by the quantum resistance & capacitance, are larger than Cu wire. However, at intermediate and global level, the CNT bundle consumes 1.5 to 4 folds smaller power than Cu as the resistances & capacitances associated with the bundle were found to be smaller than that of copper wire of same geometries. Fig. 4, 5, and Fig. 6 plot the power dissipation of local, intermediate, and global interconnects with voltage swing variations. As depicted in Fig. 4, the power dissipation of both the Cu and CNT bundle is almost same because of their identical parasitic components for local interconnect.
Power Dissipation (Watt.)
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Fig. 4. Power Dissipation of local interconnects with voltage swing variation. Power Dissipation Vs Voltage Swing Power Dissipation (uW)
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Fig. 5. Power Dissipation of intermediate interconnects with voltage swing variation. Power Dissipation Vs Voltage Swing Power Dissipation (uW)
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Fig. 5 and 6 depict that the power of CNT bundle does not increase as much as Cu with the increase in voltage swing for intermediate and global interconnects. This is attributed to the lower resistance & capacitances associated with the CNT bundle of the same lengths. This characteristic feature can be used to increase the speed of CNT bundle interconnect while keeping the power lower than Cu interconnect. Moreover, for a power constraint design, CNT bundle can be used to get greater speed for the same power dissipation. IV.
For delay analysis and comparison, each interconnect wire is being driven by an input buffer so as to have realistic input to interconnects and an FO4 load is connected at the other end. We used the test bench and methodology for delay measurement as suggested in [11]. The interconnect delay is measured from the output node of input buffer to the input node of FO4 load. For fair comparison between the CMOS and CNFET drivers, the geometric widths of both the drivers are the kept same. The analysis is done at a frequency of 500MHz and voltage swing of 0.9V. It has been demonstrated in [12] that due to better gate coupling and ballistic transport of electrons through an array of CNTs between drain and source of a CNFET results in a higher drive current and robustness to voltage scaling. The high performance of CNFET originates from a high carrier density due to the enhanced gate capacitance, and a large carrier velocity caused by the large group velocity of the original graphene band [13]. It was observed that at local level, Cu is faster than CNT bundle because of smaller resistance as compared to large quantum resistance associated with the CNT bundle. The resistance plays dominating role in determining the delay of interconnects. The inductance, of the order of nano henry, plays a much smaller role despite its large nominal values because R >> ωL for the interconnect geometries under analysis. Fig. 8 and Fig. 9 compare the delays of CNT bundle and Cu interconnects at intermediate and global levels. The results show that at intermediate and global level, CNT bundle is faster than Cu interconnects because of the smaller resistances and capacitances. Fig. 10 and Fig. 11 clearly show that the lowest delay values are obtained by using a combination of CNFET driver and CNT bundle for intermediate and global interconnects.
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DELAY ANALYSIS AND COMPARISON
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Fig. 6. Power Dissipation of global interconnects with voltage swing variation.
CONCLUSION
The power dissipation and delay analysis is performed for local, intermediate and global interconnects with mixed bundle of CNTs and Cu wire at 32-nm technology node. The power dissipation analysis of the interconnects has been performed for the first time and it is observed that for intermediate and global interconnects, mixed bundle of CNTs consumes smaller power than its Cu counterpart. Results show that increase in power dissipation with voltage swing is smaller for mixed bundle of CNTs and hence voltage swing can be increased to reduce the delay while having the power
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Delay Vs Voltage Swing
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Fig. 7. Ratio of CNT bundle local interconnect delay to that of Cu interconnect with CMOS and CNFET driver.
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Fig. 11. Delay of CNT bundle and Cu global interconnect with voltage swing variation.
comparable to Cu interconnects. CNT bundle intermediate and global interconnects are faster despite having larger inductances because of the smaller delay dominating components, namely ‘R’ and ‘C’, as compared to Cu wire. This paper also analyzed the effect of CMOS and CNFET driver and it is clear from the results that CNFET driver drives the interconnects more efficiently. It is concluded that mixed bundle of CNTs can replace Cu interconnects in future low-power high-speed VLSI systems.
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Fig. 8. Ratio of CNT bundle intermediate interconnect delay to that of Cu interconnect with CMOS and CNFET driver.
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[4] [5]
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[6]
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Fig. 9. Ratio of CNT bundle global interconnect delay to that of Cu interconnect with CMOS and CNFET driver. Delay Vs Voltage Swing 180
Delay (ps)
[8] [9] [10]
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[7]
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[11]
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[12]
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[13]
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