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Jun 6, 2013 - Cascaded Multilevel Converters: Optimal. Asymmetries and Floating Capacitor Control. Javier Pereda, Student Member, IEEE, and Juan Dixon, ...
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IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 60, NO. 11, NOVEMBER 2013

Cascaded Multilevel Converters: Optimal Asymmetries and Floating Capacitor Control Javier Pereda, Student Member, IEEE, and Juan Dixon, Senior Member, IEEE

Abstract—Cascaded multilevel (CM) converter is a series connection of several inverters that together generate multiple voltage levels with controllable frequency, phase, and amplitude. Its main advantages are high power, reliability, and power quality. However, it has considerable drawbacks such as high number of components, many isolated power sources, decreasing voltage quality with the modulation index, and regeneration in some series inverters at specific modulation indexes, even when the machine is motoring. The authors propose to improve any CM topology through two solutions: use optimal voltage asymmetries (ratios), higher than conventional ones; replace the voltage sources by floating capacitors balanced with a new control (PI controller) and/or a high-frequency link. This paper presents theoretical analysis and experimental results of CM converters with increased voltage-quality (levels), some of them keeping this high quality and avoiding regeneration in motor mode at any motor operation point, using the proposed voltage asymmetries and simplifying or eliminating some voltage sources. Experimental results show a reduction of components, an improved voltage quality, and a satisfactory behavior in stationary and dynamic operation. Index Terms—Asymmetric inverters, cascaded multilevel (CM) converters, hybrid inverters, multicell inverters, power conversion.

I. I NTRODUCTION

M

ULTILEVEL converters are the state of the art in ac drive systems and a great solution for many applications (minerals, chemical, oil, gas, metals, paper, water, power generation, energy conversion, manufacturing, transportation, etc.) [1], [2]. Their main advantages are high-quality power, a wide range of power operation, operation under fault, and the use of traditional semiconductors [3], [4]. Their high-quality power is achieved by generating several voltage levels, which reduces total harmonic distortion (THD), common-mode and derivative voltages (dv/dt), isolation motor damage, and output filters. However, multilevel converters are more complex in topology, control, and modulation than traditional ones (twolevel inverters); they use many semiconductors; and their power quality decreases with modulation index m (voltage amplitude). Multilevel converters can be classified in three main topologies, namely, neutral point camped (NPC), flying capacitor, and cascaded multilevel (CM) [5], [6]. CM converters are based on a series connection of several inverters, which are called main and auxiliary (aux) inverters. Manuscript received November 7, 2011; revised April 23, 2012 and July 25, 2012; accepted September 10, 2012. Date of publication October 24, 2012; date of current version June 6, 2013. This work was supported in part by the Comisión Nacional de Investigación Científica y Tecnológica through Project Fondecyt 1100175, by ABB Chile, and by Iniciativa Científica Milenio through NEIM Project P-07-087-F. The authors are with the Pontificia Universidad Católica de Chile, 7820436 Santiago, Chile (e-mail: [email protected]; [email protected]). Digital Object Identifier 10.1109/TIE.2012.2219834

These inverters can have the same (modular) or different topologies (hybrid), and they can generate the same (symmetrical) or different voltages per level (asymmetrical). Usually, the cascaded converter is composed by h-bridges connected in series, which is called a cascaded h-bridge (CHB) converter. Anyway, the cascaded converter can be composed by a series connection of any inverter topology. The main advantages of cascaded converters are the use of conventional inverters and semiconductors, great flexibility and fault tolerance, but they use many isolated power supplies. Asymmetrical cascaded converters increase the voltage quality per number of semiconductors used [7] and reduce the switching losses, but they lose modularity, and their aux inverters regenerate at some modulation indexes, even if the machine is motoring. This paper proposes two general solutions to reduce or eliminate the main drawbacks of cascaded converters and to keep or increase their advantages. Both solutions can be applied simultaneously or independently, and they are shown below. 1) Use new optimal voltage asymmetries among the supplies of the series inverters to increase the voltage-quality (levels). These asymmetries were calculated using a proposed formula that is general to any multilevel converter. 2) Replace or eliminate the aux voltage sources by two possible methods: floating capacitors (FCs) balanced with a new PI control, and/or a high-frequency link (HFL) [8]. Both methods can be applied together or independently. If a main power supply with variable voltage is used, the proposed aux voltage sources work as variable voltage supplies and keep the asymmetry without extra hardware or software. Then, the voltage amplitude of the motor can be controlled by the main dc voltage; hence, the modulation index m of the cascaded converter is fixed. Therefore, voltage-quality is maintained all the time, and regeneration in motor mode is avoided at any operation point of the motor. Even more, if variable supplies are used, the voltage asymmetry of the main inverter can be further optimized (maximized), which was called as extreme asymmetry. This paper is organized as follows. Section II shows the cascaded converter topologies. Section III presents the power supply solutions. Section IV presents the optimal asymmetries. Finally, Section V shows the experimental results. II. C ASCADED M ULTILEVEL (CM) C ONVERTER T OPOLOGIES CM converter uses several inverters connected in series that may have any topology (see Fig. 1). Cascaded converter can be classified according to the topologies used, the voltages supplied to each series inverter, or the motor connection implemented, as follows.

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PEREDA AND DIXON: CM CONVERTERS: OPTIMAL ASYMMETRIES AND FLOATING CAPACITOR CONTROL

Fig. 1.

Some possible VSI topologies (single- and three-phase topologies) used in CM converters.

Fig. 2.

CM converter topologies (possible connections of inverters and the motor).

Fig. 3.

Classification of CM converters according with the voltage sources of each VSI connected in series.

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A. Topology Classification (Modular or Hybrid)

B. Voltage Supply Classification (Symmetric or Asymmetric)

If all the inverters used in the cascaded converter have the same topology, then the converter is modular. Otherwise, the converter is hybrid. Fig. 2 shows all cascaded converter topologies, which are composed by single- and/or three-phase inverters. Hybrid converters combine the advantages of the different topologies used, but they are less modular and fault tolerant than modular and symmetrical converters; hence, this tradeoff must be evaluated in the design.

If each voltage source inverter (VSI) used in the cascaded converter generates voltage levels with the same amplitude, then the converter is symmetrical (1 : 1). Otherwise, the converter is asymmetrical. Symmetrical converters have more redundant voltage vectors than the asymmetrical ones; thus, they generate less number of vectors (levels), but they are more fault tolerant due to their high redundancy and modularity. Fig. 3 shows the voltage supply classification.

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A. Method I: Floating Capacitors (FCs)

Fig. 4. Power supply solutions for cascaded converters: (a) FCs, (b) HFL, and (c) FCs combined with HFL.

C. Motor Connection (Star, Delta, or Open-End Winding) The motor can be connected in Y, Δ, or open-end winding, depending on the cascaded converter topology (see Fig. 2). If the cascaded converter uses 2 three-phase inverters, the motor can only have an open-end winding connection. However, this open-end winding configuration can get exactly the same result of Y connection because the floating neutral is created through the inverters [see Fig. 2(c), (e), and (f)]. If the motor has isolated windings [see Fig. 2(b)], which is only possible using single-phase inverters and an open-end winding connection, some inverters of the cascaded converter can share the same power supply, which not only reduces hardware but also reduces the number of levels generated in the motor. On the other cases, the cascaded converter must be powered by an isolated power supply per series inverter used. The nonisolated open-end winding connection generates the same voltage on each motor winding than Y. In addition, both generate more levels than the Δ connection due to the floating neutral generated in the motor or through the inverters. III. P ROPOSED P OWER S UPPLIES FOR C ASCADED M ULTILEVEL (CM) C ONVERTERS The proposed methods are two: FCs and/or an HFL. Both methods replace all the aux voltage supplies and can work together or alone (see Fig. 4). If the main voltage source is variable, both methods work as variable voltage supplies to keep the voltage asymmetry and the modulation index is maintained at any operation point. Operating the cascaded converter with a fixed modulation index m∗ has three main advantages: The regeneration on aux inverters in motor mode is avoided; the high voltage quality is maintained at any operation point; and the converter is operated in the point of zero aux average power. Both methods are general solutions and applicable to any cascaded converter (see Fig. 2), but some topologies are widely more improved than others; therefore, the solutions must be evaluated for each topology (see Fig. 3). However, the proposed methods are focused in asymmetric converters.

This solution replaces the aux voltage sources by FCs [see Fig. 4(a)]. Some publications also propose FCs, which are controlled by PWM, PS-PWM, time-domain modulation, and switching state redundancy in a multilevel converter [9]–[14], but this paper proposes a different control (PI controller) that adjusts a fixed modulation index m∗ in the cascaded converter to operate the capacitors as active filters. Therefore, the FCs have zero average power without using special PWM, PS-PWM, or vector redundancies of the cascaded converter. As the cascaded converter operates with a fixed modulation index all the time, the motor voltage amplitude must be controlled by the main dc voltage source Vdc that must be variable; hence, the FC voltages must also vary. Fig. 5 shows the space voltage vectors of a nine-level cascaded converter as an example and the average power sign zones of the aux supplies Paux in the modulation index domain [8], [15]. The PI control operates the converter between the discharging and charging areas (m∗ = 0.8 approximately) to have zero average power in the aux supplies (Paux = 0). If the capacitor voltages are lower than the reference, the error is positive; thus, the PI controller slightly decreases the modulation index to operate in the charging zone; otherwise, the PI controller increases the modulation index to operate in the discharging zone. The modulation index variation is very low; thus, the level number is maintained under normal operation (only the pulsewidth changes). However, under very fast dynamic performance, the number of levels can be reduced according to the capacitor time response, but this situation is quite short (e.g., 1 s) if the capacitance is selected according to the motor current. Moreover, under very fast operation, the performance will be very similar to a conventional multilevel converter that generates a level number according with the output voltage amplitude (modulation index). Therefore, the converter operates in the external border (trajectory) shown in Fig. 5, which has the highest modulation index (levels) of all possible trajectories with zero Pau = 0. The redundancy areas have smaller modulation indexes because they use the redundant main vectors that are in the central area. Then, the PI controller can achieve zero aux average power in a higher modulation index than using redundant main vectors. Therefore, the PI controller can be applied in converters with very high asymmetries, where redundancy control does not work because the vector redundancy is minimized. It is important to clarify that vector redundancy comes from each series inverter and from the combination of all these inverters (multilevel converter redundancy). The multilevel converter redundancy is reduced with voltage asymmetry, but the redundancy of each series inverter is maintained because its topology is not manipulated. Therefore, a second control (capacitor balance control) uses the vector redundancy of the aux inverters to balance the capacitors and to assist the PI control, increasing stability and dynamic performance. PI Control: The proposed PI control is briefly illustrated in Fig. 6 where a reference voltage vector is introduced from a motor control (open loop, v/f, direct torque control, etc.), then its amplitude is compensated because the cascaded converter

PEREDA AND DIXON: CM CONVERTERS: OPTIMAL ASYMMETRIES AND FLOATING CAPACITOR CONTROL

Fig. 5.

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Nine-level CHB converter (Paux sign and control strategies).

redundant aux vectors by a model predictive control that minimizes the cost function J (1). The manipulated variables are the redundant vectors k of the space vector that was previously selected by the space-vector control. The cost function quantifies the future quadratic error of each capacitor using capacitor voltages vj and reference Vref (r · Vdc ), phase currents (ia , ib , and ic ), capacitance values Cj , the sampling period Ts , the charging effect on each capacitor Sj (k), and weighting coefficients λj (usually not used). However, other balance controls can be used as special carrier-based PWM or space-vector modulation by the nearest three vectors [16]–[20] J(k) =

M 

λj ·(Vref −vj (t+Ts |k))2

(1)

j=1

Ts   · ι · S j (k)+vj (t) (2) Cj  i ∈ {ia , ib , ic } for one-phase inverters  ι= j (3) for three-phase inverters [ia ib ic ] ⎧ Sj (k) for one-phase inverters ⎪ ⎪ ⎨ ⎡ S a (k) ⎤  (4) S j (k) = ⎣ jb Sj (k) ⎦ for three-phase inverters ⎪ ⎪ ⎩ Sjc (k) S (k) 1 if jth capacitor is directly connected

vj (t+Ts |k) =

j

or = 0 if jth capacitor is disconnected −1 if jth capacitor is inversely connected. S j (k)[i] (5)



Fig. 6.

FCs and/or HFL to supply each inverter of the CM converter.

is submodulated (m∗ < 1). The compensated amplitude is introduced in the variable source as reference to obtain Vdc . The capacitor voltages are compared with the reference, which is obtained by applying the voltage ratio r to the main voltage Vdc (e.g., r = 1/4 if the asymmetry is 1 : 4). Finally, the error is introduced in the PI controller to adjust the fixed modulation index m∗ of the cascaded converter, which is the manipulated variable to control the capacitor voltages. If two or more FCs are used, the PI control is the same showed in Fig. 6, but the controlled variable is the sum of all FC voltages; thus, r must be multiplied by the number of FCs (M ) and a second control must be added to balance the FCs. Capacitor Voltage Balance Control: This control balances the capacitor voltages and assists the PI controller using the

B. Method II: High Frequency Link (HFL) HFL is presented in [8] and proposed in this paper because it is ideal as a multiple variable voltage supply. HFL is also ideal to work with optimal asymmetries and fixed modulation indexes because it generates autobalanced variable voltages and its power is highly reduced (small HFL). HFL is a high-frequency toroidal transformer to supply the aux inverters with a fixed voltage (r · Vdc ); hence, the aux voltages change with the main voltage Vdc and keep the voltage ratio r (N1 /Nmain ), even if Vdc is variable. HFL uses an h-bridge to generate a square voltage and h-bridge rectifiers to obtain the aux dc voltages.

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TABLE I PARAMETERS OF THE C ASCADED C ONVERTERS AND I NVERTERS

A. Conventional Optimal Asymmetries (Maximizing L) This conventional optimization maximizes L, which is the same as maximizing each voltage ratio (9) and (10). However, these voltage ratios are limited by the level number of the previous (smaller) series inverters to ensure a generation of equidistant levels in the phase voltage of the converter rj ≤ L(j−1)

L(j) = 1 +

j 

ri · (Li − 1)

(9)

i=1

L = L(N ) .

TABLE II E XAMPLES OF C ONVENTIONAL AND P ROPOSED O PTIMAL A SYMMETRIES

HFL works at any modulation index, and it can supply all the aux inverters without closed-loop control or works with the FCs, as shown Fig. 6, where the HFL supplies six aux singlephase inverters as an example. IV. O PTIMAL AND E XTREME VOLTAGE A SYMMETRIES This section presents the classic and proposed optimization methods of voltage asymmetries. The classic one is focused in maximizing the levels generated by the converter L, and the proposed one t is focused in maximizing the levels generated on each motor winding Lm . However, both methods of optimization do the same; they maximize the voltage ratios (6), which are limited to different values according on the method of optimization applied. The parameters are defined in Table I. The number of space voltage vectors of an inverter is determined by the number of phases and voltage levels per phase (7). For a cascaded converter, the voltage vectors are the products of the vectors of all inverters; thus, a high number of vectors are generated, but many of them are redundant. The conventional optimization increases the nonredundant vectors indirectly, as a consequence of maximizing L (8). In contrast, the proposed optimization maximizes the redundant vectors to increase Lm directly. Table II and Fig. 7 show some proposed and conventional optimal voltage asymmetries as examples rj = Vj /V1  F L , nv = N

j=1 (Lj )

(6) F

,

nnonredundant = 1+F ·L·(L−1). v

for a single inverter for a cascaded converter

(7) (8)

(10)

B. New Optimal and Extreme Asymmetries (Maximizing Lm ) These proposed optimizations maximize Lm , which is the same as maximizing each voltage ratio or the nonredundant vectors. However, maximizing the nonredundant vectors is easier and more general than maximizing Lm because the space voltage vectors of the converter and the motor are always equivalent, and the converter and motor voltages are different according with the modulation and motor connection; Y or open-end winding (Lm > Lf f > L); Δ (Lm = Lf f > L); and isolated open-end winding (Lm = L). Therefore, the proposed optimizations are applicable to any motor connection except for the isolated one [see Fig. 2(b)] because its space voltage vector is virtual (no phase–phase voltages) and maximizing Lm does not make sense (Lm = L). The new asymmetries generate distorted converter phase voltages (nonequidistant levels) and the same L than classic optimal asymmetries. However, they generate equidistant levels in each motor winding (phase) and maximize Lm due to the right combination of the distorted converter phase voltages that optimizes the phase–phase voltages. Therefore, the converter has a virtual level number (L∗ ) higher than conventional (L∗ ≥ L). Another advantage is the power reduction in aux inverters, ideal to use FCs or HFL as aux sources. Proposed Optimal Asymmetries: This optimization maximizes the voltage ratios, but they are limited by (11) to ensure equidistant voltage vectors and levels in the motor winding voltages at any modulation index    3 L(j−1) − dj−1 − 1 rj ≤ 1 + floor (11) 2 ⎧ if Lj is odd and ⎪ ⎨ 0, d j−1 = 0 and j < N dj =   ⎪ ⎩ floor L(j−1) −1 − 3 dj−1 , other case 2 2   (12) L∗ = L(N ) − dN /h  π cos 6·(LN −1) , if LN is odd and dN = dN −1 h= 1, other case. Proposed Extreme Asymmetries: If LN ≤ 3 and the converter works with a fixed modulation index m∗ , the last voltage ratio rN can be higher to maximize Lm to the extreme (nonredundant vectors in the cascaded converter). Therefore, the voltage ratio of the N th inverter (biggest) is limited by (13) to ensure that the fixed trajectory has equidistant vectors.

PEREDA AND DIXON: CM CONVERTERS: OPTIMAL ASYMMETRIES AND FLOATING CAPACITOR CONTROL

Fig. 7.

Space voltage vectors of the converter and the motor (both are identical) from the examples in Table II.

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Fig. 10. Motor voltages using the proposed extreme asymmetries (1 : 5) in Fig. 8.

Fig. 8. Cascaded converter using a three-level (aux) and a two-level inverter.

Fig. 9. Motor voltages using the proposed optimal asymmetries (1 : 4) in Fig. 8.

Therefore, the motor works as if the converter will generate L∗ number of levels (14). This fixed trajectory matches with the fixed modulation index m∗ presented in Section III (zero average aux power); hence, this extreme asymmetry is compatible with FCs or HFL rN ≤ 2 · L(N −1) − 1

(13)



L = (1 + rN · (LN − 1)) /h  1, if LN = 2 h= cos(π/12), if LN = 3.

(14)

V. E XPERIMENTAL R ESULTS Three topologies were implemented with FCs (22 mF) and proposed asymmetries. A 3-kW motor and an ABB industrial controller (AC800PEC) were used with a sampling period Ts of 50 μs. The switching frequency is the fundamental for the main inverter, and it is LN · rN times the fundamental for the smallest aux inverter; hence, frequency is rising on each inverter according with its asymmetry. The experimental results illustrate the motor phase voltages and currents in steady-state and dynamic operation.

Fig. 11.

Cascaded converters using two three-level inverters.

Fig. 12. Motor voltages using the proposed optimal asymmetries (1 : 4) in Fig. 11.

A. Three-Level + Two-Level Inverters

B. Two 3-Level Inverters

Three possible topologies were tested generating the same motor voltages (see Fig. 8). Fig. 9 shows experimental voltages with the proposed optimal asymmetries (1 : 4), where the motor voltages have 15 levels and a THDv of 5.5%. Fig. 10 shows the voltages using the proposed extreme asymmetries (1 : 5), where the motor voltages have 18 levels and a THDv of 4.8%.

Four possible topologies are illustrated in Fig. 11, and the experimental voltages with the proposed optimal asymmetries (1 : 4) are shown in Fig. 12, where the motor voltages have 28 levels and a THDv of 3%. Fig. 13 shows the voltages using the proposed extreme asymmetries (1 : 5), where the motor voltages have 34 levels and a THDv lower than 3%.

PEREDA AND DIXON: CM CONVERTERS: OPTIMAL ASYMMETRIES AND FLOATING CAPACITOR CONTROL

Fig. 13. Motor voltages using the proposed extreme asymmetries (1 : 5) in Fig. 11.

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Fig. 15. Motor voltages using the new optimal asymmetries (1 : 4 : 16) in Fig. 14.

Fig. 16. Motor voltages using the new extreme asymmetries (1 : 4 : 21) in Fig. 14.

Fig. 15 shows the voltages using the optimal asymmetries 1 : 4 : 16 (n1 = 4 and n2 = 16), where the motor voltages have 104 levels. Fig. 16 shows the voltages using extreme asymmetries 1 : 4 : 21 (n1 = 4 and n2 = 21), obtaining 123 levels in the motor voltage. The trajectory to get equidistant voltages is shown in Fig. 14 and matches with the zero power trajectory m∗ ; thus, FCs could be used by PI control (see Fig. 6). The THDv ’s of both voltage asymmetries are very low (less than 2%), and the voltage is sinusoidal at a simple view. All the topologies illustrated in Fig. 14 generate the same voltages in the motor windings for a determined asymmetry. The topologies with open-end winding connection do not have a motor neutral n, and the converter has two neutrals (n1 and n2). However, the motor is connected in star through the converter; hence, these topologies generate the same motor voltage with that in the star motor connection. The voltages are defined in (15)–(17), where vaN is the phase voltage of the converter, vab is the phase–phase voltage of the motor or the converter (are the same), and van is the phase voltage of the motor winding  vaN Y or Δ motor connection (15) vaN = va1n1 − va2n2 open-end wiring ⎧ Y or Δ motor connection ⎨ (vaN − vbN ) vab = (va1 − vb1 ) (16) ⎩ −(va2 − vb2 ) open-end wiring  v −v ca ab Y motor connection 3 van = (17) (va1 − va2 ) open-end wiring. Fig. 14. Cascaded converters using three 3-level inverters.

C. Three 3-Level Inverters The topologies illustrated in Fig. 14 were implemented using FCs in the middle inverter and an HFL in the smallest one (the same system illustrated in Fig. 6.)

Fig. 17 shows these voltages (i.e., van , vaN , and vab ) using any topology in Fig. 14 with extreme asymmetry (1 : 4 : 21). The phase voltage of the converter vaN has the same levels (27) as the conventional optimal asymmetry (1 : 3 : 9), but these voltage levels are nonequidistant, which generate jumped levels and distorted waveform. However, the phase and phase–phase voltages of the motor have equidistant levels with a sinusoidal

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VII. C ONCLUSION

Fig. 17. Voltages using the proposed extreme asymmetries (1 : 4 : 21) in Fig. 14.

Fig. 18. FC voltage and current (vcap and icap ) in phase A and three-phase capacitor voltages (see Fig. 8 topology with extreme asymmetries 1 : 5).

waveform and more voltage levels than regular asymmetries; thus, the motor receives a higher power quality and the aux inverters manage less power. This is possible because the control is focused on three-phase systems; hence, it combines the distorted (nonequidistant) phase voltage of the converter to generate a uniform (equidistant) phase–phase voltage, which is possible using the fixed modulation index m∗ . D. Floating Capacitors (FCs) Voltages Fig. 18 shows the voltage and current of FC (22 mF) used in Fig. 8 in steady and dynamic operation. In steady operation, the capacitor voltage ripples only can be seen in the oscilloscope using ac coupling because the voltage has no appreciable variations. In the dynamic test, the three voltage capacitors are balanced and controlled. VI. D ISCUSSION The dynamic performance and voltage ripples in the FC depend on the capacitance, the current load, and the switching frequency. When a very fast dynamic operation is required, the performance will be limited by the capacitance, which must be over a limit to insurance stability. In the worst cases, the voltage quality will decrease for milliseconds until the FCs get the reference. However, if we compare this limit case with a conventional multilevel converter, which decreases the level number under nominal operation, the proposed solution is similar or better. The other solution for high dynamic performance is to replace the FCs by an HFL because it has a very high dynamic performance [8], [15]. The proposed control is more complex than conventional ones because it requires a PI controller, a capacitor balance control, and voltage sensors for each FC, but the hardware is reduced. The complexity is in the software and does not represent a limitation or increased cost because the actual technology allows high computation at a low cost.

Overoptimal and extreme voltage asymmetries for general CM converters have been presented in this paper through general formulas. These voltage asymmetries increase the voltagequality (levels) compared with conventional ones, even when they work with lower modulation indexes m∗ . However, the extreme asymmetry requires variable voltage sources to operate in all the amplitude voltage range without voltage distortion in the motor (working in a fixed m∗ ). Two methods to eliminate or replace the isolated voltage sources have been also presented, i.e., a PI controller to use FCs and an HFL as an isolated voltage source. Both methods can work together or alone. The dynamic response of converters with FCs is limited by the voltage variation rate, which depends on the capacitance value and motor current, but the capacitance also increases the control stability; thus, the design has a tradeoff that should be evaluated according to the requirements. The proposed asymmetries are ideal to apply FCs and/or HFL because they reduce the power requirement of aux inverters, increasing control stability and reducing the capacitor and HFL size. Even more, the single space voltage trajectory m∗ of extreme asymmetries matches with the zero average power in aux inverters, which makes possible the application of FCs. Experimental results of several topologies were shown with satisfactory results in stationary and dynamic tests.

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PEREDA AND DIXON: CM CONVERTERS: OPTIMAL ASYMMETRIES AND FLOATING CAPACITOR CONTROL

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Javier Pereda (S’09) was born in Santiago, Chile. He received the electrical engineering degree (with highest honors) from the Pontificia Universidad Católica de Chile, Santiago, in 2009, and is currently working toward the Ph.D. degree at the same university. He is a Research Assistant in power electronics, electrical machines, power generation, and electric traction with the Department of Electrical Engineering, Pontificia Universidad Católica de Chile, where he is also part of the Electric Vehicle Laboratory. He is currently working on ac motor drives, direct torque control, and new multilevel inverter topologies. Mr. Pereda is a member of Millennium Nucleus of Power Electronics, Mechatronics and Control Process (NEIM) and a Comisión Nacional de Investigación Científica y Tecnológica (Conicyt) scholarship holder.

Juan Dixon (M’90–SM’95) was born in Santiago, Chile. He received the M.S. Eng. and Ph.D. degrees from McGill University, Montreal, QC, Canada, in 1986 and 1988, respectively. Since 1979, he has been with the Department of Electrical Engineering, Pontificia Universidad Católica de Chile, Santiago, where he is currently a Professor. He has presented more than 70 works in international conferences and has published more than 40 papers related to power electronics in IEEE Transactions and IEE Proceedings. His main areas of interest are in electric traction, PWM rectifiers, active filters, power factor compensators, and multilevel converters. He has created an electric vehicle laboratory, where state-of-the-art vehicles are investigated.