Chapter 7

Memory Built Built--In SelfSelf-Repair

Jin-Fu Li Advancedd Reliable Ad R li bl S Systems (ARES) Lab. L b Department of Electrical Engineering National Central University Jhongli, Taiwan

Outline ¾ Introduction ¾ Redundancy Organizations ¾ Built-In Redundancy Analysis Techniques ¾ Built-In Self-Repair Techniques ¾ Conclusions

Advanced Reliable Systems (ARES) Lab., EE. NCU

Jin-Fu Li

2

Embedded Memory–Quality ¾ During manufacture ¾ Yield ¾ Exponential yield model ¾ Y = e− AD , where A and D denote the area and defect density, respectively

¾ After manufacture ¾ Reliability

¾ During use ¾ Soft error rate


Jin-Fu Li

3

An Explosion in Embedded Memories ¾ Hundreds of memory cores in a complex chip is common ¾ Memory cores usually represent a significant portion ti off the th chip hi area RAM RAM RAM

RAM

RAM

RAM RAM RAM

RAM

RAM

AMD dual-core Opteron™ processor Advanced Reliable Systems (ARES) Lab., EE. NCU

Intel dual-core Intanium processor (JSSC, 2006) Jin-Fu Li

4

Memory Repair ¾ Repair is one popular technique for memory yield improvement ¾ Memory repair consists of three basic steps ¾Test ¾Redundancy analysis ¾Repair delivery


Jin-Fu Li

5

Conventional Memory Repair Flow Test Error Logging Bitmap Redundancy Analysis

Requirements: 1 Memory tester 1. 2. Laser repair equipment Disadvantages: 1. Time consuming 2 Expensive 2. E i

Laser Repair Test


Jin-Fu Li

6

Memory BISR Flow Required Circuit BIST BISD BIRA

Test

Built-In Self-Test Built-In Self-Diagnosis Built-In Redundancy-Analyzer Reconfiguration


Function

Jin-Fu Li

Fault Location Redundancy allocation Swap Defective Cells

7

Typical Memory BISR Architecture Normal I/Os

Testt Collar &

BIST

Reco onfigura ation mechanis sm

BIRA

RAM

Redundancy


Jin-Fu Li

8

Typical Memory BIST Architecture Normal I/Os

Test Controller

Generator

Tes st Collarr

Test Pattern

RAM

Comparator


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9

Redundancy Organizations ¾ A memory array with local redundancies

Bank 1 Locall Spare L S Columns B k2 Bank Local Spare p Rows

10

Jin-Fu Li

EE, National Central University

Redundancy Organizations ¾ A memory array with hybrid redundancies

Bank 1

B k2 Bank Local Spare p Rows

11

Global (Linked) p Columns Spare Jin-Fu Li


Redundancy Organizations ¾ A memory array with hybrid redundancies

Bank 1

Bank 2

Bank 2

B k2 Bank

Global ((Linked)) Spare Rows

12

Local p Columns Spare Jin-Fu Li


Redundancy Scheme ¾ Three typical local redundancy schemes

Spare rows

Spare columns


Jin-Fu Li

Spare rows and Spare columns 13

Spare Column & Spare IO c0c1c2c3

c0c1c2c3

c0c1c2c3

c0c1c2c3

c0c1c2c3

r0 r1 r2 r3

Spare IO Q0 c0c1c2c3

Q1 c0c1c2c3

Q6 c0c1c2c3

Q7 c0c1c2c3

r0 r1 r2 r3 Spare Col. Q0

Q1


Q6 Jin-Fu Li

Q7

[ LogicVision] 14

Reconfiguration Scheme 32 columns

32 columns Spare column

S Spare co olumn Sense Amplifier p

Sense Amplifier p Decoder 10 bit data 10-bit Programming Module (Flash) [M. Yarmaoka, et al., JSSC, 2002]


Jin-Fu Li

15

Types of Reconfiguration Schemes ¾Three kinds of reconfiguration techniques ¾ f reconfiguration ¾Soft fi i ¾Byy programming p g g FFs to store repair p information

¾Firm reconfiguration ¾By programming ¾B i non-volatile l til memories i to t store t repair information

¾Hard (permanent) reconfiguration ¾Laser-blown or electrically-blown y ppolysilicon y or diffusion fuses Advanced Reliable Systems (ARES) Lab., EE. NCU

Jin-Fu Li

16

Comparison Advantages

Disadvantages

Soft

1. Multi-time repair 2. Low design overhead

1. Some latent defects cannot be repaired 2 Long 2. L repair i setup t time ti

Firm

1. Multi-time repair 2 Short repair setup time 2.

1. High-voltage programming circuit is required q

Hard 1. Short repair setup time


1. One-time repair 2. Specific technology is required

Jin-Fu Li

17

Memory BISR Techniques ¾ Dedicated BISR scheme ¾A RAM has a self-contained self contained BISR circuit

¾ Shared BISR scheme ¾Multiple RAMs share a BISR circuit ¾E g processor ¾E.g., processor-based based BISR scheme and IP IP-based based BISR scheme

¾ BISR classification l ifi ti according di to t the th capability bilit of redundancy analysis ¾BISR with redundancy analysis capability ¾BISR without redundancy analysis capability Advanced Reliable Systems (ARES) Lab., EE. NCU

Jin-Fu Li

18

BISR Strategies ¾ Types of BISR ¾ Off-line BISR ¾ On-line BISR

¾ Off Off-line line BISR without BIRA ability ¾ BIST + reconfiguration mechanism

¾ Off-line Off line BISR with BIRA ability ¾ BIST + BIRA + reconfiguration mechanism

¾ On-line O li BISR

19

Jin-Fu Li


Examples of BISR Design ¾ NEC BISR design without BIRA (JSSC92) 5 32 26

21

I/O Buffer

32

I/O

64 Mb Memory Array

21

Spare p M Memory

16 32b 16wx32b

CAM

16wx21b

21

32

ROM 20

TPG

32

C Comparator Jin-Fu Li

Fail BIST Block

BISR Block


Examples of BISR Design ¾ A BISR design (ITC98) Data Input Bus

Spare Memory

Main Memory

Column Decoder Redundancy Analysis Algorithm Information 21

Reconfiguration Control Unit Jin-Fu Li


RAM BISR Using Redundant Words Address, Data Input, Control BIST

Mux

Fuse Box Redundancy

RAM

Logic

Mux

[ V. Schober, et. al, ITC01] Advanced Reliable Systems (ARES) Lab., EE. NCU

Jin-Fu Li

22

Redundancy Wrapper Logic ¾ The redundancy logic consists of two basic components ¾Spare memory words ¾Logic to program the address decoding

¾ The address comparison is done in the redundancy logic ¾The address is compared to the addresses that are stored in the redundancy word lines

¾ An overflow bit identifies that there are more failing addresses than possible repair cells ¾ The programming of the faulty addresses is done during the h memory BIST or from f the h ffuse bbox dduring i memory setup Advanced Reliable Systems (ARES) Lab., EE. NCU

Jin-Fu Li

23

An Array of Redundant Word Lines Address, Data Input, Control

MBIST

F

Address

Write Data

Address

Expected Data

RAM Fail TDI

fail

Fail Address

RAM Data

FA

Address

Data

FA

Address

Data

FA

Address

Data

Word Redundancy

FO Control

Overflow

TDO

Data out [V. Schober, et. al, ITC01]


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24

Applications of Redundancy Logic ¾ Faulty addresses can be streamed out after test completion Then the fuse completion. f se box bo is blo blownn accordingly in the last step of the test ¾This is called here hard repair o y do donee at w wafer e level eve test es ¾Thiss iss normally

¾ Furthermore, the application can be started i immediately di t l after ft the th memory BIST passes ¾This is called here soft repair


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25

Redundancy Word Line

TDI

Fail

Fail_address _

FA

Address

A

R W

DI

Expected_data p _

Data

&

Comparator

&

Fail

Fail_address

TDO

Read

Expected_data, DO

[V. Schober, et. al, ITC01] Advanced Reliable Systems (ARES) Lab., EE. NCU

Jin-Fu Li

26

One-Bit Fuse Box ¾ One-bit O bi fuse f box b contains i a fuse f bit bi andd a scan flip fli flop fl for controlling and observing the fuse data ¾Test_Update=0: the chain of inverters is closed (The value is latched) ¾T ¾Test_Update=1: U d 1 iit is i possible ibl to set the h internal i l node d from f TDO ¾The ports TDI and TDO are activated at scan mode Test_Update

1

FRest

0 FRead

Scan FF

TDO

FRest FRead FGND

t

Fout Reset cycle to read out the fuse information

Fuse

FGND

TDI

Fuse Bit (FB) Advanced Reliable Systems (ARES) Lab., EE. NCU

[V. Schober, et. al, ITC01] Jin-Fu Li

27

Fuse Boxes ¾ The fuse box can be connected to a scan register to stream in and out data duringg test and redundancy y configuration Update

Fuse Box

Reset

FB

FB

Scan FF

TDI

Fail

FB

Scan FF

Scan FF

A[0]

TDO

A[N-1] [V. Schober, et. al, ITC01]


Jin-Fu Li

28

Parallel Access of the Fuse Information Fuse Box

BIST Fuse activation Address to be fuse

FA

Fuse Address

FA

Fuse Address

FA

Address Register g

FA

Fuse Address

FA

Address Register g

FA

Address Register g Redundancy Logic [V. Schober, et. al, ITC01]


Jin-Fu Li

29

Serial Access of the Fuse Information Fuse Box

BIST Fuse activation

TDI

Address to be fuse

FA

Fuse Address

FA

Fuse Address

FA

Address Register

FA

Fuse Address

FA

Address Register

FA

Address Register

TDO

Redundancy Logic

[ V. Schober, et. al, ITC01] Advanced Reliable Systems (ARES) Lab., EE. NCU

Jin-Fu Li

30

Test Flow to Activate the Redundancy Initialization of the BIST Load faulty addresses

Increment address Access memory No

Yes

Test finished?

No

Fail? Yes

No

Fuse to be blown?

No

Yes

Yes

Stream out faulty addresses Soft repair

Hard repair

Free eg ste register?

Write expected p data Write address Write Fail flag Unrepairable [ V. Schober, et. al, ITC01]


Jin-Fu Li

31

Redundancy Analysis ¾ A repairable memory with 1D redundancy ¾Redundancy allocation is straightforward

¾ A repairable i bl memory with i h 2D redundancy d d ¾Redundancy analysis (redundancy allocation) is needed

¾ Redundancy analysis problem ¾Choose the minimum number of spare rows and columns that cover all the faulty cells 2

1 2 3

1

4 5 6 Advanced Reliable Systems (ARES) Lab., EE. NCU

Jin-Fu Li

32

Redundancy Analysis Using ATE ¾ Create a fault map which size is the same as the memoryy under test 0 2 4 1 2 2 0 1 Column Counters

1 0 1 1 0 1 1 2 2 1 0 0 1 1 0

Row Counters

¾ Execute software-based redundancy analysis using computer t in i ATE 33

Jin-Fu Li


Redundancy Analysis Using ATE ¾ Hardware d necessary to execute the h redundancy d d analysis ¾ A device image memory (or fault memory) ¾ The size is the same as the memory under test

¾ Counters that indicate the number of faults that occur in a row, or a column

¾ A Apparently, l the h conventional i l software-based f b d redundancy analysis algorithms are not adapted to be realized li d with i h hardware h d andd be b embedded b dd d into i the h SOCs ¾ Hardware overhead is too large

¾ Efficient built-in redundancy-analysis (BIRA) algorithms are required to be developed 34

Jin-Fu Li


BIRA Algorithm – CRESTA ¾ Comprehensive Real-time Exhaustive Search Test and Analysis ¾ Assume that a memory has 2 spare rows (Rs) & 2 spare columns (Cs), (Cs) then all possible repair solutions ¾R-R-C-C (Solution 1) ¾R C R C (Solution 2) ¾R-C-R-C ¾R-C-C-R (Solution 3) ¾C R R C (Solution ¾C-R-R-C (S l ti 4) ¾C-R-C-R (Solution 5) ¾C C R R (Solution ¾C-C-R-R (S l ti 6) Solution 1 (R-R-C-C) [ T. Kawagoe , et. al, ITC00] Advanced Reliable Systems (ARES) Lab., EE. NCU

Jin-Fu Li

35

CRESTA Flow Chart Start Test No

Fail ? Yes

S1

S3

S2

S6

Finish ?

No

Yes

Result Output End Advanced Reliable Systems (ARES) Lab., EE. NCU

[T. Kawagoe , et. al, ITC00] Jin-Fu Li

36

Basic Idea and Limitation of CRESTA ¾ Assume that there are m spare rows and n spare columns in a memory. y Then a CRESTA repair p analyzer y contains C(m+n, m) sub-analyzers ¾ E.g., g , if 2 spare p rows and 2 spare p columns are available,, CRESTA will need C(4, 2)=6 sub-analyzers

¾ Each sub-analyzer y analyzes y in-comingg row/column addresses of faulty memory cells in parallel in a different repair p strategy gy ¾ Because CRESTA tries all the possible repair strategies of spare resources resources, it guarantees finding a solution for a repairable memory 37

Jin-Fu Li


Basic Idea and Limitation of CRESTA ¾ Since CRESTA needs row address and column address of a faultyy memory y cell in order to check if the current faulty memory cell can be repaired by previously allocated spare p resources ¾ It is unable to handle at-speed multiple-bit failure occurring in a word-oriented memory ¾ Determine the number of spare columns needed for all failure bits in a word cannot be achieved in one cycle

¾ In an at-speed BISR design, a column repair vector (CRV) is used to store column failure information for solving this problem ¾ CRV is a column repair vector of the same size as the word width 38

Jin-Fu Li


At-Speed BIRA ¾ Example of redundancy allocation ¾ CCRR (Unrepairable)

0

RSV

BIST Read Cycle

Fail_ Map

Current Spare

Allocated Rows

CRV

C C R R

0

00000

C1

--

00000

1

10001

C1

--

10001

2

01110

C2

--

11111

3

01110

R1

--

11111

4

00000

R1

--

11111

0 1 2 3 4

1

2

3

1

4 1

2

2

2

3

3

3

¾ CRRC

39

RSV

BIST Read Cycle

Fail_ Map

Current Spare

Allocated Rows

CRV

C R R C

0

00000

C1

--

00000

1

10001

C1

--

10001

2

01110

R1

R1

10001

3

01110

R2

R1R2

10001

4

00000

C2

R1R2

10001 Jin-Fu Li


At-Speed BIRA Implementation Restart BIST Controller

Fail/Success

Memory Under Test BISRA Controller

Repair Data Repairable

¾ In the BISRA, all C(m+n, m) analysis engines or just one engine can be implemented ¾ In one engine scheme, update the repair strategy if the current repair strategy fails and then re-run BIST and try th nextt repair the i strategy t t 40

Jin-Fu Li


At-Speed BIRA Implementation Fail Map Address

SRA

BISRA Engine

SRA

Fail Map

CAR

CAR

A B I T E R

CAR

Address

BISRA Engine g

Restart

RSR

BISRA Engine

BISRA cont controller olle with ith C(m+n, C(m+n m) engines

41

SRA

BISRA cont controller olle with ith one engine

Jin-Fu Li


At-Speed BIRA Implementation ¾ Spare Resource Allocation (SRA): allocates either a spare row or a spare column according to its repair strategy ¾ Control and Report (CAR): checks if this repair strategy fails ¾ If not, it will report the repair data, such as faulty row addresses and CRV to BISRA controller CRV,

¾ Repair Strategy Reconfiguration (RSR) block: updates the repair strategy and sends a “restart” restart signal to BIST controller

42

Jin-Fu Li


Heuristic BIRA Algorithms ¾ Most of heuristic BIRA algorithms need a local bitmap for storing the information of faulty cells detected by the BIST circuit ¾ An A example l off 4 × 5 local l l bitmap bi Address R1 R2 R3 R4 RAR

C1 1 0 0 0


C1 0 1 0 0

C1 0 0 1 0

C1 0 1 0 0

Jin-Fu Li

C1 CAR 0 0 1 0

43

A BIRA Flow for Performing Heuristic RAs START BIST No

Fail? Yes Local Bitmap

Update p Bitmap

Full? Y Yes Redundancy Allocation


Jin-Fu Li

No

44

Redundancy Allocation Rules ¾ Typical redundancy analysis algorithms ¾Two-phase ¾Two phase redundancy allocation procedure: mustmust repair phase and final-repair phase

¾ Must-repair M t i phase h ¾Row-must repair (column-must repair): a repair solution forced by a failure pattern with >SC (>SR) defective cells in a single row (column), where SC and SR denote the number b off available il bl spare columns l andd spare rows

¾ Final-repair phase ¾Heuristic algorithms are usually used, e.g., repair-most rule Advanced Reliable Systems (ARES) Lab., EE. NCU

Jin-Fu Li

45

NTHU/ADMtek BISR Scheme ¾ Redundancy R d d organization i i SEG0

SEG1

SCG1

SCG0

SR0 SR1 SR: Spare Row; SCG: Spare Column Group; SEG: Segment 46

Jin-Fu Li


Dedicated BISR: NTHU/ADMtek BISR Scheme ¾ BISR block diagram Q D Wrappper

A

MAO

BIRA

POR

BIST

Main Memoryy

Spare Memory

MAO: mask address output; POR: power-on reset 47

Jin-Fu Li


BISR Flow ¾ Power-on BISR procedure Power On

BIST Test Spare Row & Column

Error information

BIRA

C i Continue

BIST Test Main Memory

BIRA Error information Masked address

BIRA

48

Reduced address space

Jin-Fu Li

Address Remapping Address EE, National Central

University

Degraded Performance ¾ Down-graded operation mode ¾ If the spare rows are exhausted exhausted, the memory is operated at down-graded mode ¾ The Th size i off the th memory is i reduced d d

¾ For example, assume that a memory with multiple bl k is blocks i usedd for f buffering b ff i andd the h blocks bl k are chained by pointers ¾ If some block is faulty and should be masked, then the pointers are updated to invalidate the block ¾ The system still works if a smaller buffer is allowed

49

Jin-Fu Li


Definitions ¾ Definition ¾ Subword ¾ A subword is consecutive bits of a word ¾ Its length is the same as the group size

¾ Example: a 32x16 RAM with 3-bit row address and 2-bit column address

A word with 4 subwords 50

A subword with 4 bits Jin-Fu Li


BIRA Algorithm ¾ Row-repair rules ¾ To reduce the complexity, complexity we use two row row-repair repair rules ¾ A row has multiple faulty subwords ¾ Multiple faulty subwords with the same column address and different row addresses

¾ Examples:

subword

51

subword Jin-Fu Li


BIRA Procedure ¾ BIRA procedure Run BIST

Done

Stop

Detects a fault

Check Row-Repair Rules

M t Met

Not met

Repair-Most Rules

Check Available Spare Rows No available spare row

Export Faulty Row Address 52

Jin-Fu Li


Analysis of Repair Rate ¾ Repair rate analysis

¾ Repair rate ¾ The ratio of the number of repaired memories to the number of defective memories

¾ A simulator has been implemented to estimate the repair rate of the proposed BISR scheme [Huang, et al., MTDT, 2002]

¾ Industrial case: ¾ ¾ ¾ ¾ 53

SRAM size: 8Kx64 # of injected random faults: 11~10 10 # of memory samples: 534 RA algorithms: proposed and exhaustive search algorithms Jin-Fu Li


Results of Repair Rate ¾ Simulation results NSR NSC NSCG 1 1 1 1 2 2 2 2 3 3 3 3 4 4 4 4 5 5 5 5 54

0 4 8 12 0 4 8 12 0 4 8 12 0 4 8 12 0 4 8 12

0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3

RR 18.37% 8.37% 73.10% 94.43% 99.26% 36 55% 36.55% 86.09% 99.26% 100% 72.17% 96.10% 99.81% 100% 72.36% 98.52% 100% 100% 85.90% 99.81% 100% 100%

1MA 2MA 3MA 4MA 5MA >5MA 99 38 5 1 192 36 3 0 0 7 1 0 73 4 0 0 44 1 0 0

191 40 7 1 2 16 1 0 75 5 0 0 44 3 0 0 18 0 0 0

4 35 12 1 71 12 0 0 43 4 0 0 18 0 0 0 7 0 0 0 Jin-Fu Li

69 16 1 1 46 3 0 0 18 3 0 0 8 0 0 0 6 0 0 0

45 9 3 0 18 8 0 0 7 2 0 0 5 0 0 0 1 0 0 0

32 7 2 0 13 0 0 0 7 0 0 0 1 0 0 0 0 0 0 0

RR (Best) 18.54% 8.5 % 86.14% 99.81% 100% 37 08% 37.08% 94.01% 100% 100% 55.06% 97.38% 100% 100% 71.91% 98.69% 100% 100% 85.77% 99.81% 100% 100% EE, National Central University

Test Chip ¾ Layout view of the repairable SRAM Technology: 0.25um 0 25um SRAM area: 6.5 mm2 BISR area : 0.3 mm2 S Spare area : 00.3 3 mm2 HOspare: 4.6% HObisr: 4.6% Repair rate: 100% (if # random faults is no more than 10)

Redundancy: 4 spare rows and 2 spare column groups G Group size: i 4 55

Jin-Fu Li


Shared BISR Techniques ¾ A complex SOC usually has many RAMs with different sizes ¾ Each repairable RAM has a dedicated BISR circuit ¾Area cost is high g

¾ If a BISR circuit can be shared by multiple RAMs, then the area cost of the BISR circuit can drastically be reduced ¾ Shared h d BISR techniques h i ¾Reconfigurable BISR or IP-based BISR technique Advanced Reliable Systems (ARES) Lab., EE. NCU

Jin-Fu Li

56

NCU/FTC BISR Scheme ¾ Reconfigurable BISR scheme for multiple RAMs RAM 1

RAM 2

RAM N-1

Wrapper

Wrapper

Wrapper

BIST RSO

TDI LD

ReBIRA

ReBISR

Shift_en Register Fuse

TDO p Fuse Group [T. W. Tseng, et. al, ITC06]


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57

Repair Process Test & Repair

Normal Operation

BIST

Power-On

BIRA

Repair Signature Setup

Load Repair Signatures into the Fuse Group

Normal Access

Pre-Fuse Testing Program Fuse


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58

Test and Repair Mode RAM 1

RAM 2

RAM N-1 N 1

Wrapper

Wrapper

Wrapper

BIST RSO

TDI LD


ReBIRA

ReBISR


Jin-Fu Li

TDO Fuse Group

59

Normal Mode RAM 1

RAM 2

RAM N-1 N 1

Wrapper

Wrapper

Wrapper

BIST RSO

TDI LD


ReBIRA

ReBISR


Jin-Fu Li

TDO Fuse Group

60

NCU/FTC BISR Scheme ¾ Reconfigurable BIRA architecture BIRA_en

Syndrome n

Fail_h _

Multi-faults Multi faults Detector

k

Test_done

FSM Syndrome Encoder

Hold_l Unrepairable

Bitmap

Shift_en

IO_Col

Address Ar+Ac

Address Masker

Remapping registers

TDI

[T. W. Tseng, et. al, ITC06] Advanced Reliable Systems (ARES) Lab., EE. NCU

Jin-Fu Li

61

Evaluation of Repair Efficiency ¾ Repair rate ¾The ratio of the number of defective memories to the number of repaired memories

¾ A simulator i l t was implemented i l t d to t simulate i l t the th repair rate [R.-F. Huang, et. al, IEEE D&T, 2005 (accepted) ¾ Simulation setup ¾Simulated memory size: 4096x128 ¾Simulated memory samples: 500 ¾Poisson defect distribution is assumed ¾Original g yield y is about 60% Advanced Reliable Systems (ARES) Lab., EE. NCU

Jin-Fu Li

62

Repair Rate ¾ Case 1: 100% single-cell faults Repair p Rate (%) ( ) 100

81.2 87.6

90 80

67.4 67.4

70 60

97.2 99.6 96.6 99.8 93.2 93 2 99.4 96.6 93.4 87.0 87.0

93.2 97.0 83.2 83.4 62.4 62.4

57.2 57.4 44.0 44.0

50

RCFA

40 29 29.8 8 29.8 30 20

Opt. 12.6 12.6

10 0

(0,2) (0,4) (1,0) (1,2) (1,4) (2,0) (2,2) (2,4) (3,0) (3,2) (3,4) (4,0) (4,2) (4,4)


Jin-Fu Li

(R C) (R,C) 63

Repair Rate ¾ Case 2: 50% single-cell faults, 20% faulty rows, 20% faulty columns, and 10% column twin-bit faults Repair Rate (%) 100

81.2 85.8

90

96.6 96 6 98 8 98.8 94.8 99.8 89.8 98.2 96.4 92.8 86.6 86.6

92.4 93.8 82.0 82.2

80

67.0 67.0

70

61.8 61 8 61.8

57.4 57 4 57.8

60

44.0 44 0 44.0

50 40 30

RCFA Opt.

28.2 28.2 12.4 12.4

20 10 0

(0,2)

(0,4)

(1,0)

(1,2)

(1,4)


(2,0)

(2,2)

(2,4)

(3,0)

Jin-Fu Li

(3,2)

(3,4)

(4,0)

(4,2)

(4,4)

(R,C) 64

ReBISR Implementations ¾ FTC 0.13um standard cell library is used ¾ Three cases are simulated Case 1

Case 2

Case 3

Core 0

64x2x8

64x2x16

64x2x32

C Core 1

128 4 16 128x4x16

128 4 32 128x4x32

128 2 64 128x2x64

Core 2

256x8x32

256x8x64

256x4x128

Core 3

512x16x64

512x8x128

512x4x256


Jin-Fu Li

65

Simulation Results ¾ Delay D l andd area overhead h d ReBIRA Parameter

Memory Area (um2)

ReBIRA Area (um2)

Ratio (%)

Delay (ns)

512x16x64

1496258.4

18766

1.25

2.5

512 8 128 512x8x128

1497561 6 1497561.6

20303

1 36 1.36

25 2.5

512x4x256

1528848

23255

1.52

2.5

¾ BIRA time i overhead h d w.r.t. a 14N March M h test with i h solid lid data background ReBIRA Parameter

Repair Rate (%)

ReBIRA Cycles

BIST Cycles

Ratio (%)

512x16x64

83.6

29952

47939584

0.06

512x8x128

82.3

30698

23605658

0.13

512x4x256

83.8

30404

12013568

0.25


Jin-Fu Li

66

NCU/FTC BISR Scheme ¾ Layout view for an experimental case

SPA ARE ROW 2

BISR

MEMORY 2

MEMORY 0 C1

MEMORY 1

Jin-Fu Li

SPARE E ROW 1


E ROW 3 SPARE

MEMORY 3

SPAR RE ROW 0

C0

C2 C3

67

Infrastructure IP ¾ What is Infrastructure IP ¾Unlike the functional IP cores used in SOCs SOCs, the infrastructure IP cores do not add to the main functionality of the chip. chip Rather, Rather they are intended to ensure the manufacturability of the SOC and to achieve lifetime reliability

¾ Examples of such infrastructure IPs ¾Process monitoring IP, test & repair IP, diagnosis IP, timing measurement IP, and fault tolerance IP


Jin-Fu Li

68

Infrastructure IP – STAR ¾ STAR IIP Mem.

Mem.

Mem.

Mem.

IW

IW

IW

IW Fuse Box

STAR Processor 1

1149.1 1

P1500 STAR Processor 2

Mem. IW [Y. Zorian, ITC02]


Jin-Fu Li

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Infrastructure IP – STAR ¾ The infrastructure IP is comprised of a number of hardware components, p , including g ¾A STAR processor, a fuse box, and intelligent wrappers (IWs)

¾ The STAR Processor ¾Performs all appropriate test & repair coordination of a STAR memory ¾It is programmed by a set of instructions to control the operation of the internal modules

¾ The Intelligent Wrapper ¾Address counters, ¾Add t registers, it data d t comparators t andd multiplexers Advanced Reliable Systems (ARES) Lab., EE. NCU

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Infrastructure IP – Repair Strategies ¾ Hard Repair

repaired unrepaired i d

¾ Soft Repair repaired i d Powered up unrepaired

¾ Combinational Repair

P Powered d ddown

Hard failures repaired

¾ Cumulative Repair unrepaired

repaired p Reliabilityy failure f Powered down

progressively repaired

progressively repaired repaired

unrepaired 71

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Infrastructure IP – ProTaR ¾ ProTaR [C.-D. Huang, J.-F. Li, and T.-W. Tseng, IEEE TVLSI, 2007 (accepted)]

¾Processor for Test and Repair of RAMs

¾ The infrastructure IP is comprised of a number of hardware components, including ¾A P ProTaR T R processor ¾A wrapper

¾ Features ¾Parallel test and diagnosis ¾Serial repair ¾ ¾Support multiple redundancy analysis algorithms Advanced Reliable Systems (ARES) Lab., EE. NCU

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Architecture of the Proposed IIP OP TM_sel Scan_en Scan_out CNT

ProTaR

Scan en Scan_en Scan_out

Controller

Wrrapper

TM_sel 2

TGO0 TGON-2

Global BIRA

ERRN-2

Done

ERR0

U Unrepair i

Shift_en Clk

Wrappeer

Instr_in

Instruction Memory

Rst

RAM 0

RAM N-1

ERR TGO [C.-D. Huang, J.-F. Li, and T.-W. Tseng, IEEE TVLSI, 2007 (accepted)] Advanced Reliable Systems (ARES) Lab., EE. NCU

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Multiple Redundancy Analysis Algorithms Support ¾ In the IIP, IIP the ProTaR has one global BIRA module and each wrapper has one local BIRA mod le module ¾ The local BIRA module performs the mustrepair phase of a redundancy analysis algorithm ¾ Then, Then the global BIRA module performs the final-repair phase of the redundancy analysis algorithm l ih


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Global/Local Bitmaps and RA Instructions

R0 R1 R2 R3

Local bitmap

Global bitmap

C0 1 0 0 0

c0 1 0 0 0

C1 0 1 1 0

C2 0 0 0 1

C3 CAR 0 1 0 0

r0 r1 r2 r3

c1 0 1 1 0

c2 0 0 0 1

c3 CID 0 1 0 0

RID

RAR RA algorithm

Instructions

Local repair-most (LRM) alg.

LRM

E Essential ti l spare pivoting i ti (ESP) alg. l {FHFR, {FHFR ROW_FIRST, ROW FIRST COL_FIRST} COL FIRST} Row first alg.

{ROW_FIRST, COL_FIRST}

Column first alg. alg

{COL FIRST ROW_FIRST} {COL_FIRST, ROW FIRST}


[C.-D. Huang, J.-F. Li, and T.-W. Tseng, IEEE TVLSI, 2007 (accepted)] Jin-Fu Li 75

Block Diagram of the ProTaR Done

CNT

Shift_en

ERR

Instr_in

PC CTR_P

TM_sel Clk Rst

OP

Instruction Memory BIRA

Unrepair

ERR

Bitmap

Scan_out

FSM

Scan_out Shift Shift_out t

Scan_en



Block Diagram of the Wrapper TGOi-1

ERRi-1

OP

Address Generator

TM_sel

Data Generator

CNT S Scan_en

CTR W CTR_W Comparator

Scan_out

Addr_t DI_t

DO_M CEN_t WEN_t

Bitmap Addr DI DO TGOi

Address Remapping Register

DO S DO_S

ERRi



Area Cost of the Wrapper ¾ Area overhead of the Wrapper is defined as the ratio of the area of the wrapper to the area of the corresponding memory p results for an 8Kx64-bit memoryy ¾ Experimental Redundancy Configuration

Wrapper Area

Area Overhead

2R2C

6739 gates

2.3%

2R3C

7342 gates

2.5%

3R3C

8317 gates

2.8%

¾ Area cost of Wrappers for different memory sizes Memory Configuration

Wrapper Area

Area Overhead

8K x 16

3944 gates

4.6%

4K x 32

4825 gates

5.8%

2K x 64

6501 gates

7 1% 7.1%


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Area Cost of the IIP ¾ An IIP for four memories is implemented ¾ The size of Mem0, Mem0 Mem1, Mem1 Mem2, Mem2 and Mem3 are 8Kx64, 8Kx64 8Kx64, 4Kx14, and 2Kx32, respectively ¾ The redundancyy configurations g of the Mem0,, Mem1,, Mem2, and Mem3 are (3x3), (2x2), (2x2), and (2x2), respectively

¾ ¾ ¾ ¾

The area of the four memories is 6798472um2 The area of all the redundancies is about 896060um2 The area of the IIP is only about 309893um2 Th the Thus, th area overhead h d off the th IIP iis only l about b t 4.56%


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Layout View of the IIP ¾ Layout view of the proposed IIP for four RAMs



Conclusions ¾ Embedded memories represent more and more area off system-on-chip t hi (SOC) designs d i ¾ The yield of memory cores dominates the yield of chips

¾ Various BIRA techniques have been presented ¾Different BISR techniques for memories in SOCs h have bbeen presented t d


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References 1. 2. 3. 4. 5.

6. 7.

8 8.

9. 10.

T. Kawagoe, J. Ohtani, M. Niiro, T. Ooishi, M. Hamada, and H. Hidaka, “A built-in self-repair analyzer (CRESTA) for embedded DRAMs,” in Proc. Int’l Test Conf. (ITC), 2000, pp. 567.574. V. Schober, S. Paul, and O. Picot, “Memory built-in self-repair using redundant words,” in Proc. Int’l Test Conf. (ITC), Baltimore, Oct. 2001, pp. 995-1001. Y. Zorian, “Embedded memory test & repair: Infrastructure IP for SOC yield,” in Proc. Int’l Test Conf. (ITC), Baltmore, Oct. 2002, pp. 340.349. C.-T. Huang, C.-F. Wu, J.-F. Li and C.-W. Wu,”Built-in redundancy analysis for memory yield improvement,” IEEE Trans. Reliability, vol. 52, no. 4, pp. 386-399, Dec. 2003. J.-F. Li, J.-C. Yeh, R.-F. Huang, C.-W. Wu, P.-Y. Tsai, A. Hsu, and E. Chow,”A built-in self-repair scheme for semiconductor memories with 2-D redundancies,” in Proc. IEEE Int. Test Conf. (ITC), (Charlotte), pp. 393-402, Sept. 2003. J.-F. Li, J.-C. Yeh, R.-F. Huang, and C.-W. Wu,”A built-in self-repair design for RAMs with 2-D redundancies,” d d i IEEE Trans. Very Large Scale l Integration Systems, vol.13, l no.6, pp. 742-745, June, 2005. S.-K. Lu, Y.-C. Tsai, C.-H. Hsu, K.-H. Wang, and C.-W. Wu, “Efficient built-in redundancy analysis for embedded memories with 2-D redundancy,” IEEE Trans. on VLSI Systems, vol. 14, no. 1, pp. 34–42, Jan. 2006. T W Tseng, T.-W. T J.-F. J F Li Li, C.-C. C C H Hsu, A A. P Pao, K K. Chi Chiu, and dE E. Ch Chen, "A reconfigurable fi bl bbuilt-in il i self-repair lf i scheme for multiple self-repairable RAMs in SOCs," in Proc. IEEE Int. Test Conf. (ITC), (Santa Clara), Paper 30.2, pp. 1-8, Oct. 2006. C.-D. Huang, J.-F. Li, and T.-W. Tseng,”ProTaR: an infrastructure IP for repairing RAMs in SOCs,” IEEE Trans. Trans Very Large Scale Integration Systems Systems, vol.15, vol 15 no.10, no 10 pp pp. 1135-1143, 1135 1143 Oct Oct. 2007. 2007 R.-F. Huang, J.-F. Li, J.-C. Yeh, and C.-W. Wu,”RAISIN: a tool for evaluating redundancy analysis schemes in repairable embedded memories,” IEEE Design and Test of Computers, vol.24, no.4, pp. 386396, July-August 2007.


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