Characterization of GaN MOSFETs on AlGaN/GaN ... - IEEE Xplore

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IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 61, NO. 2, FEBRUARY 2014

Characterization of GaN MOSFETs on AlGaN/GaN Heterostructure With Variation in Channel Dimensions Qingpeng Wang, Ying Jiang, Student Member, IEEE, Liuan Li, Dejun Wang, Yasuo Ohno, Member, IEEE, and Jin-Ping Ao, Senior Member, IEEE Abstract— GaN MOSFETs were developed on an AlGaN/GaN heterostructure in which the drain and source ohmic contacts were fabricated on the AlGaN/GaN heterostructure, and the electron channel was formed on the GaN buffer layer by removing the AlGaN barrier layer. For devices with different types and sizes, discrepant field-effect mobilities were observed and the origins of the discrepancy were analyzed. One reason causing the discrepancy is the discrepancy of gate dimension between the design and fabrication. In devices with only mesa as the device isolation, the real channel width would be larger than the mesa width because a parallel channel might have formed in the isolation region just outside the device mesa. Boron ion implantation was found to be effective to cutoff the current path in the isolation region. Another reason causing the discrepancy is that the real channel length would be larger than the designed one owing to the lithography and gate dry recess process. To extract the correct mobility and effective channel length of the GaN MOSFET fabricated on AlGaN/GaN heterostructure with variation in the channel dimensions, several methods were proposed and compared basing on ring-type MOSFETs. Index Terms— Dry recess, effective channel length, field isolation, GaN MOSFET.

I. I NTRODUCTION

G

ALLIUM NITRIDE (GaN) has great potential in the application of power electronics owing to its wide bandgap of 3.4 eV [1], [2]. Recent years, excellent results have been reported in AlGaN/GaN heterostructure field-effect transistors (HFETs). However, most of them showed normallyon operation, which will increase the power consumption of circuit system [3], [4]. For safe operation and low power consumption, enhancement mode (E-mode) operation of the FETs Manuscript received October 22, 2013; revised November 29, 2013; accepted December 16, 2013. Date of current version January 20, 2014. The work of Q. Wang and Y. Jiang was supported by the State Scholarship Fund of China Scholarship Council. The review of this paper was arranged by Editor G. Ghione. Q. Wang and Y. Jiang are with the School of Electronic Science and Technology, Dalian University of Technology, Liaoning 116024, China, and also with the Institute of Technology and Science, The University of Tokushima, Tokushima 770-8506, Japan (e-mail: [email protected]; [email protected]). L. Li and J.-P. Ao are with the Institute of Technology and Science, The University of Tokushima, Tokushima 770-8506, Japan (e-mail: [email protected]; [email protected]). D. Wang is with the School of Electronic Science and Technology, Dalian University of Technology, Liaoning 116024, China (e-mail: [email protected]). Y. Ohno was with the Institute of Technology and Science, The University of Tokushima, Tokushima 770-8506, Japan. He is now with e-Device Inc., Sapporo 063-0801, Japan (e-mail: [email protected]). Digital Object Identifier 10.1109/TED.2013.2296094

is required. Basically, E-mode operation requires two points: 1) positive threshold voltage and 2) high current conduction at positive gate voltage. In case of silicon MOSFETs, the threshold voltage can be adjusted by substrate doping, so the positive threshold voltage can be realized easily compared with other issues. GaN MOSFET on AlGaN/GaN heterostructure is an interesting candidate for the easy fabrication of source and drain ohmic contacts. A lot of works have been done to improve channel mobility [5]–[8]. Im et al. [6] reported a device with mobility of 225 cm2 V−1 s−1 using atomic layer deposited Al2 O3 as the gate oxide based on a device with gate length of 0.25 μm. Field-effect mobility of 201 cm2 V−1 s−1 based on a device with gate length of 5 μm was reported in [7]. Most of the results on mobility were evaluated based on a capacitance–transconductance (C–G m ) method, in which the carrier mobility is calculated from the gate capacitance and transconductance in linear region. So to evaluate the electron mobility precisely, the device structure and the definition of gate length and gate width should be evaluated carefully. Otherwise, estimation error will occur due to the discrepancy between the designed and the real dimensions. In this paper, we will report a phenomenon of parallel channel, which can widen the effective channel width if the device is fabricated with only mesa instead of field isolation process. The extended channel width will lead to an overestimated mobility if the mobility is extracted from the C–G m method based on a bar-type device. Field isolation with boron ion implantation can solve this problem effectively. Also, the channel length of GaN MOSFETs on AlGaN/GaN heterostructure may be larger than the designed size due to the lithography and dry recess process. The variation on the gate length will bring underestimation on the mobility, especially mobility of devices with relatively short channel. Accurate channel length determination is difficult but important for short channel devices. To avoid dimensional variation and characterize the mobility and channel length precisely, several methods to characterize GaN MOSFETs are proposed and compared basing on ring-type MOSFETs. II. D EVICE S TRUCTURE AND FABRICATION The structure of the GaN MOSFET is showed in Fig. 1, which is made on an AlGaN/GaN HFET structure formed

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WANG et al.: CHARACTERIZATION OF GaN MOSFETs ON AlGaN/GaN HETEROSTRUCTURE

Fig. 1.

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GaN MOSFET structure on AlGaN/GaN heterostructure. Fig. 3.

I –V characteristics of a long channel ring-type MOSFET.

Fig. 2. Three types of MOSFETs. (a) Long channel ring type. (b) Short channel ring type. (c) Short channel bar type.

on sapphire substrate with sheet resistance of ∼400 /. To eliminate the current collapse effect by the electron injection at the source and drain surface, n-type AlGaN barrier layer and GaN cap layer with doping density of 1 × 1019 cm−3 were used [9]. From top to bottom, the n-GaN, n-AlGaN, and u-GaN are with 10 nm, 20 nm, and 2-μm thick, respectively. Device isolation by inductively coupled plasma (ICP) etching with SiCl4 gas was first done for ∼100 nm with ICP power of 50 W and bias power of 100 W. After that, part of the samples was given boron ion implantation process outside the mesa region. Then, the 2-DEG layer in the channel region was recessed for ∼40 nm at a low etching rate to avoid etching damage. The ICP and bias power are 100 and 20 W, respectively, with an etching mask of SiO2 (500 nm). After etching, the samples were treated in HNO3 :BHF = 1:1 solution to remove the possible Si contamination on the etched surface. Then, silane-based SiO2 insulator with aimed thickness of ∼100 nm (104-nm measured with ellipsometer) was deposited using PD-220LC (SAMCO) and annealed at 1000 °C for 10 min in N2 ambient. The ohmic contact was then formed using Ti/Al/Ti/Au (50/200/40/40 nm) with annealing temperature of 850 °C for 1 min in N2 ambient. Finally, Ni/Au (70/30 nm) was deposited as the gate metal. The ohmic contact resistance is 0.3–0.5 ·mm. Three types of MOSFETs were prepared [Fig. 2(a)–(c)], which were: 1) long-channel ring type; 2) short-channel ring type; and 3) short-channel bar type. For simplicity, they were called LR, SR, and SB, respectively. III. D EVICE C HARACTERIZATION AND D ISCUSSION A. Evaluation of Mobility With Different Device Structures Based on the gradual channel approximation, a long channel MOSFET was first utilized for device evaluation in which the effects from the series resistance and the discrepancy of gate dimension between the design and fabrication can be ignored [5]. Instead of bar-type one, LR device with outer and inner gate recess radii of 89 and 183 μm (L = 94.0 μm and

Fig. 4. (a) C–V characteristic. (b) Transfer and mobility characteristics. (c) Transfer characteristics in semilogarithm.

Weff = 819.3 μm), respectively, was used to avoid the leakage current from the isolation region. Current–voltage (I –V ) characteristics were measured using an Agilent 4155C semiconductor parameter analyzer with sufficient delay time and integration time. Capacitance–voltage (C–V ) characteristics were measured using an HP 4284A impedance analyzer under a frequency of 100 kHz with the drain and source electrode connected. The I –V characteristics of a long-channel ring-type MOSFET is shown in Fig. 3. Device operation up to gate voltage of 10 V was confirmed. Fig. 4(a) shows the C–V curves. Fig. 4(b) shows transfer characteristics and field-effect mobility under Vd = 0.1 V. Fig. 4(c) shows the transfer characteristics in semilogarithm, from which the subthreshold swing of 0.18 V/decade was obtained with the Id /Weff from 10−11 to 10−13 A/μm. Interface state density around 4 × 1011 cm−2 eV−1 can be further calculated from the swing. In both I –V and C–V characteristics, the hysteresis between the forward and reverse curves was not obviously observed, which indicates a good stability of the devices. The field-effect mobility is directly obtained by (1), which we call C–G m method L Gm μFE = (1) Cox Weff Vd here 2π(r2 − r1 ) Weff = (2) ln(r2 /r 1 )

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TABLE I D EVICE D IMENSIONS IN D ETAIL

Fig. 5. (a) Mobility characteristics of SB type. (b) Comparison of mobilities of LR, SB, and SR type.

where Weff is the effective channel width, r1 is the inner radius, r2 is the outer radius, Cox is the oxide capacitance per unit area, which could be obtained from the ratio of the measured gate capacitance to the gate metal area. The maximum mobility was 143 cm2 V−1 s−1 at a gate bias of 3 V. It is considered to be a credible value of mobility for the affect from the series resistance and dimensional variation can be ignored. In our experiment, SB- and SR-type devices with series of sizes are also prepared. Furthermore, SR-type devices can be divided into two groups. They are SRI for the common SR with the same inner radius of 89 μm, gate length 5–20 μm, and SRII for the special SR devices with 1/r1 + 1/r2 = 0.0296 μm−1 and the item ln(r2 /r1 ) from 0.14–0.67. The detailed device dimensions are listed in Table I. The mobilities of MOSFETs of the SB group with only mesa isolation extracted by C–G m method with the designed dimensions are showed in Fig. 5(a) and (b) shows a comparison of mobilities of LR-, SB-, SRI-, and SRII-type devices on the same chip. Obvious discrepancy on the field-effect mobility was observed depending on both the device type and channel length. The estimated mobilities of SR type were much lower than that of LR and would increase and close to LR type in region of longer channel length. In the situation of SB-type device, the estimated mobility was larger than that of LR in the region of longer channel and obviously decreased and closed to SR in the region of short channel.

Fig. 6.

Current flow paths in bar-type MOSFET with mesa isolation.

Fig. 7.

Mobility characterization of bar-type and ring-type devices.

Since the mobility should be with little difference on the same chip if we take the mobility of LR type as standard one the mobility of SB type with longer channel were obviously overestimated and the mobility of SR type was obviously underestimated. Based on (1), it is considered that the discrepancy in mobility is caused by the difference between the real channel size and the designed one. Since the mobility was calculated by the designed size, if the real channel width becomes wider, the mobility will be overestimated. If the real channel length becomes larger, the mobility will be underestimated. Furthermore, series resistance can also lead an underestimation of the mobility. B. Field Isolation With Boron Ion Implantation to Define Channel Width The overestimation of mobility only appeared in bar-type devices, so SB-type devices were carefully investigated. As a result, a phenomenon of parallel channels was observed here. As showed in Fig. 6, parallel channels may exist under the redundant gate at the isolation region for device with only mesa process as the device isolation, thus the real channel width of the bar-type MOSFET may be larger than the designed one. Theoretically, phenomenon of parallel channels could not be directly observed if the threshold voltages of the parallel channel are lower than that of the main channel in Fig. 6. It is reported that the threshold voltage may become deeper if higher bias power of ICP system was used, which may be related with higher surface damages (such as VN ) [10], [12]. Thus, parallel channels may be observed when the ICP etching bias power of mesa isolation is larger than that of gate recess. In our samples, as showed in the enlarged graph of Fig. 5(a), tails are observed below the threshold in the mobility characteristics. Furthermore, if the bias power of mesa process is much larger, instead of the tails, a phenomenon of two-piece mobility will appear. As showed in Fig. 7, our previous work in [13] showed two-piece mobility in the bar-type devices with

WANG et al.: CHARACTERIZATION OF GaN MOSFETs ON AlGaN/GaN HETEROSTRUCTURE

Fig. 8. (a) Left half part of the device structure with boron ion implantation. (b) I –V characteristics.

the bias power of 200 and 20 W for the mesa and gate recess, respectively. It should be mentioned that this effect will be not obviously observed but still exist when the etching bias power of mesa isolation is the same or smaller than that of recess etching. Also, it will become weaker in devices with shorter channel because the parallel channel width is relatively narrow. In this condition, unintentional overestimation of mobility will easily happen if C–G m method is used. Actually, the negative threshold voltages in Figs. 4 and 5 may be also related with the dry etching damages beside the possible higher electron concentration in u-GaN. Thus, reducing dry etching damage by optimizing the dry etching parameters and replacing u-GaN with weak p-GaN are possible methods to obtain a positive threshold voltage. The original idea for mesa process is to remove the 2-DEG layer for device isolation between the AlGaN/GaN HFETs. However, for the GaN MOSFET on AlGaN/GaN heterostructure described here, a channel can appear even in the isolation region if a MOSFET like structure is formed and lead to a parallel channel. To overcome this problem, field isolation is also necessary to eliminate the possible channel formation outside the mesa as the silicon field isolation technologies [14]–[16]. If effective field isolation can be realized, the device gate width can be also defined precisely. In our experiment, boron ion implantation was used for field isolation [Fig. 8(a)]. Two steps ion implantation was conducted. The implantation energy, dose was 110 keV, 7 × 1014 cm−2 and 30 keV, 5 × 1014 cm−2 , respectively. The mask for implantation was the double layers of 2-μm positive photoresist (HPR 1183L, Fuji film) and 500-nm SiO2 [17]. The implanted depth is estimated as 330 nm. Based on the Gaussian’s distribution, 95% of the implanted ions are located in the range form surface to the depth of 330 nm. All of the following discussion will be based on the devices with boron ion implantation outside the mesa region. Figs. 8(b) and 9(a) showed the I –V and transfer characteristics of a LR-type device. The mobility of LR-type device was ∼131 cm2 /V s characterized by C–G m method. Fig. 9(b) showed the comparison of mobility of devices with different types and dimensions. We can see that both of SB-, SR-type devices showed similar trend on the relationship between mobility and channel length. There is no overestimation on the mobility of SB-type device. It demonstrates that boron implantation is an effective way for cutting off the parallel channel. The mobility of LR-type device with ion

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Fig. 9. (a) Transfer and mobility characteristics. (b) Comparison of mobilities of LR-, SB-, and SR-type devices.

Fig. 10.

Detailed sizes of the device structure.

implantation is a little lower than that of the only mesa one due to the possible implantation damage. The implantation condition should be further adjusted to avoid the problem. However, the underestimation of mobility in the short channel devices still exists due to the existence of gate length discrepancy and series resistance. C. Methods to Extract Mobility and Real Channel Length The underestimation of mobility was commonly observed in SR- and SB-type devices. In silicon MOSFET, this underestimation was commonly considered to be caused by the series resistance. The discrepancy between effective channel length and the designed gate length will also reduce the accuracy of mobility evaluation. In GaN MOSFET on AlGaN/GaN heterostructure with recessed gate, it may be also caused by the extension of channel length due to overetching in ICP dry recess process. Method to extract effective channel length in SB-type with effective field isolation was presented in [18], we call it Chern method for simplicity in the following discussion. But in GaN MOSFET, especially device with only mesa isolation, it may not be proper for the change of both channel length L and channel width W . To avoid the variation of channel width by parallel channels and the leakage current from the isolation region, method with ring-type MOSFET is more preferable. In ring-type devices, the Chern method above is no longer proper because the effective channel width Weff and series resistance will change with the device dimensions so that uniform slopes and intersect point could not be obtained. In this condition, detailed relationship between the resistances and device dimensions in ring-type devices should be carefully investigated. Fig. 10 shows the detailed device structure of the source side in sectional view. From drain to source, four kinds of resistance exist in the GaN MOSFET, which are ohmic contact resistance (Rc ) of source and drain ohmic electrodes, sheet resistance (Rsh ), MIS-HFET resistance (Rh ), and the channel

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resistance (Rch ). As the sheet resistance of MIS-HFET formed on highly doped n-GaN/n-AlGaN structure with 100-nm-thick oxide layer would almost not change with the positive bias due to the deeper threshold voltage and current saturation at positive bias. In later deduction process, Rh = Rsh could be taken for simplicity. In the situation of ring-type MOSFET, effective channel width Weff can be calculated by (2). Similar with Chern method, the total resistance Rt from source to drain can be obtained from the I –V data by (3). Rs and Rch are the series resistance and channel resistance, respectively. Different from that in bar-type devices, they will change with the device dimensions. Detailed relationship between the resistances and designed device dimensions is shown as (4) and (5). Proper approximation was done according to the tailor’s expansion the detailed expression for Rt , Rs and Rch are as follows: Rt = Rs =

≈ = Rch = ≈

∂ Vd = Rs (r1 , r2 ) + Rch (r1 , r2 , Vg ) ∂ Id 1 1 Rc + 2π r1 − 9 r2 + 9 r1 − r r2 + 9 Rsh ln + ln + 2π r1 − 9 r2 + r 1 1 1 [Rc + (9 − r ) Rsh ] + 2π r1 r2 1 1 Rs + 2π r1 r2 L mask + L (Wmask + W ) μFE Cox Vg − Vt

ln rr21 + r r11 + r12 2πμFE Cox Vg − Vt

(3)

(4)

(5)

where Wmask , L mask , and r and L are the designed channel width, the designed channel length, and the variation of radii and channel length between the designed and actual ones. Rs is a constant. Obviously, L equals to 2r μFE , Cox , Vg , Vt , and Vd are the field-effect mobility, gate oxide capacitance, gate voltage, threshold voltage, and drain-source voltage, respectively. Then, from (3)–(5), the total resistance Rt can be obtained as the following:

ln rr21 + r r11 + r12 (6) Rt = Rs + 2πμ F E Cox Vg − Vt . Different from the Chern method, according to (6), Rt would have a linear relationship with the item ln(r2 /r1 ) if the device was specially designed with a constant (1/r1 + 1/r2 ) under a certain gate bias. Then, the field-effect mobility μFE can be extracted from the slope of the line. The variation of the channel length r can be extracted from the intersect point of lines of Rt ∼ ln(r2 /r1 ) at different gate bias of (Vg –Vt ). (Vg –Vt ) was used instead of Vg to avoid the influence of smaller variation of Vt . In our samples of SRII-type devices, the (1/r1 + 1/r2 ) was just specially designed as 0.0296 μm−1 for this method. Fig. 11 are the series of Rt ∼ ln(r2 /r1 ) plots under Vg –Vt from 3 to 10 V for SRII-type MOSFETs with

Fig. 11.

Rt versus ln(r2 /r1 ) at Vg –Vt from 3 to 10 V for SRII MOSFETs.

ln(r2 /r1 ) from 0.1–0.7. L of ∼2–2.7 μm were obtained. The field-effect mobility μFE was ∼129–132 cm2 V−1 s−1 under Vg –Vt of 3–10 V, which agreed quite well with that of the LR MOSFET. However, one problem is that it is difficult to obtain the specific L for these lines are not intersecting in one point. This is caused by the approximation in the equations above. Especially, Rs will change with both the device dimensions and gate bias. Also, the variations of Cox and field-effect mobility with gate bias will change the slopes. Specific value of the L and μFE is preferred in characterization of GaN MOSFET. To obtain single value of L and μFE , the variation of Rs and gate bias-dependent mobility is main problems. To eliminate the influence of discrepant Rs , d(Rt Weff )/d[1/(Vg –Vt )], the first derivative of (Rt Weff ) with respect to 1/(Vg –Vt ), can be used instead of Rt since (Rs Weff ) is not a function of 1/(Vg –Vt ). In the linear region of the Id –Vg curve, the value d(Rt Weff )/d[1/(Vg –Vt )] seems to be constant. But actually, d(Rt Weff )/d[1/(Vg –Vt )] will have small fluctuation with 1/(Vg –Vt ), which is due to the variation of u FE with gate bias. To overcome this problem, slopes k from the fitting line of the Rt Weff ∼1/(Vg –Vt ) curve could be used instead of a series value of d(Rt Weff )/d[1/(Vg –Vt )]. By plotting the line k ∼ L mask , mobility and L could be extracted from the slope and the intercept of the line, respectively. The mathematical expression is showed in k≈

L mask + L ∂ R t = μFE Cox ∂ 1 Vg − Vt

(7)

here Rt = Rt · Weff .

(8)

Very similar method using bar-type devices has been presented in [19]. With the introduction of Rt Weff , our method can be used in both bar-type and ring-type devices. It should be mentioned that for the existence of L, the real channel width in a ring-type device could not be known, with inner and outer radii changed r , variation of channel width was described as follows:

r 2 ln rr21 + rr12 − rr21 . (9) W ≈ 2 r2 ln r1 For r1 ≥ 50 μm, r2 ≤ 200 μm, and r ≤ 2 μm, then W will be 3 V, where the Id –Vg cure is affected little by nonlinearity from obvious mobility degradation and the series resistance. Fig. 12(a) shows the curve of Rt ∼1/(Vg –Vt ) of SRI type. The slopes k obtained from the fitting lines are showed in Fig. 12(b). Field-effect mobility of 132.5 cm2 /Vs was obtained from slop. L of −2.2 μm was obtained from intercept of the x-axis. As introduced above, this method can be applied for both SR- and SB-type devices. Similar results are also obtained from SRII and SB devices. The extracted field-effect mobility and L are 129.5 cm2 /Vs, 2.32 μm from SRII-type devices and 132.46 cm2 /Vs, 2.29 μm from SB-type devices. The variation of the channel length L may come from the over exposure of positive-type photoresist and overetching in wet process of SiO2 etching mask, also the sidewall etching during the ICP etching. Furthermore, etching damage or surrounding field, which may remove 2-DEG layer near the side wall and the parasitic MOSHFET may also bring extension to the channel length [20]. Theoretically, the series resistance can also be extracted from Figs. 11 and 12(a) of our method. Unfortunately, the extracted value of Rs are ∼0 and it is very difficult to obtain precise value for the range of Y value of the intersect points are much wider than that of X value, which was used to extracted L. Since series resistance Rs are very small compared with Rch , even small fluctuation of Rch in different part of the GaN wafer may totally affect the accuracy of extracted Rs . In comparison, two methods above were used to calculate the L and mobility, the extracted L and mobility were listed in Table II. Mobility of LR-type by C–G m method was listed as standard value for comparison. Comparison of SRI-, SRII-, and SB-type devices of k–L mask plot with method II are showed in Fig. 13. Little difference

was found in intercepts and small variation of the slopes exists, which may be due to the inhomogeneity of the wafer. Both method I and method II can obtain the correct value of mobility, which agreed with the value obtain by C–G m method with LR-type device. Method II can be applied in both SR- and SB-type and obtained specific value of both mobility and real channel length if the device is with effective field isolation. IV. C ONCLUSION GaN MOSFETs based on AlGaN/GaN heterostructure were fabricated and characterized. Widened channel width was found in devices with only mesa as the field isolation process. It would lead a phenomenon of parallel channel in the isolation region of the bar-type MOSFETs, which would finally lead to overestimation on the mobility. It is found that field isolation with boron ion implantation can solve this problem effectively. Extension of channel length is also found, which may be due to the ICP dry recess process. This variation brings underestimation on the mobility, especially the mobility of devices with relatively shorter channel. Finally, two methods to characterize mobility and real channel length are presented and analyzed. These methods can avoid the misestimate of the mobility by the variation of channel dimensions and obtained correct field-effect mobility and real channel length. ACKNOWLEDGMENT The authors would like to thank SAMCO INC, Toyota Motor Corporation, and Prof. S. Shinkai of Kyushu Institute of Technology for their support. R EFERENCES [1] J. W. Milligan, S. Sheppard, W. Pribble, Y.-F. Wu, S. Muller, and J. W. Palmour, “SiC and GaN wide bandgap device technology overview,” in Proc. IEEE Radar Conf., Apr. 2007, pp. 960–964. [2] A. Christou and F. Fantini, “Introduction to the special issue on GaN and related nitride compound device reliability,” IEEE Trans. Device Mater. Rel., vol. 8, no. 2, p. 239, Jun. 2008. [3] J.-P. Ao, D. Kikuta, N. Kubota, Y. Naoi, and Y. Ohno, “Copper gate AlGaN/GaN HEMT with low gate leakage current,” IEEE Electron Device Lett., vol. 24, no. 8, pp. 500–502, Aug. 2003. [4] U. K. Mishra, P. Parikh, and Y. F. Wu, “AlGaN/GaN HEMTs—An overview of device operation and application,” Proc. IEEE, vol. 90, no. 6, pp. 1022–1031, Jun. 2002. [5] J.-P. Ao, K. Nakatani, K. Ohmuro, M. Sugimoto, C.-Y. Hu, Y. Sogawa, et al., “GaN metal-oxide-semiconductor field-effect transistor with tetraethylorthosilicate SiO2 gate insulator on AlGaN/GaN heterostructure,” Jpn. J. Appl. Phys., vol. 49, no. 4, pp. 04DF09-1–04DF09-4, Apr. 2010.

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Ying Jiang (S’13) received the B.S. degree in electronic science and technology from Dalian Jiaotong University, Dalian, China, in 2008. She is currently pursuing the Ph.D. degree with the Dalian University of Technology, Dalian, and the University of Tokushima, Tokushima, Japan. Her current research interests include the design, fabrication, and characterization of GaN based electronic devices.

Qingpeng Wang received the B.S. and M.S. degrees in electrical and electronic engineering from the Dalian University of Technology, Dalian, China, in 2010 and 2013, respectively. He is currently pursuing the Ph.D. degree with the Dalian University of Technology and the University of Tokushima, Tokushima, Japan. His current research interests include the design, fabrication, and characterization of GaN based electronic devices.

Jin-Ping Ao (SM’10) received the B.S. degree in physics from Wuhan University, Wuhan, China, in 1989, the M.S. degree in semiconductor physics and semiconductor device physics from the Hebei Semiconductor Research Institute, Hebei, China, in 1992, and the Ph.D. degree in electronic engineering from Jilin University, Jilin, China, in 2000. He joined the University of Tokushima, Tokushima, Japan, in 2001, and he is currently an Associate Professor.

Liuan Li received the B.S. and M.S. degrees from Jilin University, Changchun, China, in 2007 and 2010, respectively. He has been with Tokushima University, Tokushima, Japan, since 2012, involved in the investigation of high frequency and high-power AlGaN/GaN field effect transistors.

Dejun Wang received the B.S. and M.S. degrees in semiconductors from Jilin University, Changchun, China, in 1990 and 1993, respectively, and the Ph.D. degree in materials science from Tsinghua University, Beijing, China, in 1997. He is with the Dalian University of Technology, Dalian, China, as a Professor of microelectronics. His current research interests include power semiconductor materials and devices, Si3DP/GSI technologies, real time and embedded systems, and wireless sensor network.

Yasuo Ohno (M’01) received the B.A. degree in pure and applied science from Tokyo University, Tokyo, Japan, in 1970, and the Ph.D. degree in electrical engineering from the Tokyo Institute of Technology, Tokyo, in 1994. He was a Professor with the Institute of Technology and Science. In 2012, he established e-Device, Inc., Sapporo, Japan, and is currently the Director of e-Device, Inc.