Characterization of High-Voltage SiC MOSFETs ...

Characterization of High-Voltage SiC MOSFETs under UIS Avalanche Stress L Yang*, A Fayyaz, A Castellazzi *University of Nottingham, UK, [email protected],

avalanche condition and the evolution of gate threshold voltage (Vth), drain leakage current (idss) and body diode forward voltage (Vf) of SiC power MOSFETs under repetitive-pulse avalanche stress at high temperature has been monitored with a view to shedding some light on the causes of the avalanche breakdown of SiC MOSFET devices.

Keywords: SiC MOSFET, Degradation, UIS Avalanche.

Abstract In this work, the capability of high-voltage SiC MOSFETs to dissipate energy during avalanche breakdown under singlepulse UIS (Unclamped Inductive Switching) test condition at high temperatures is assessed. And the degradation has also been identified under repetitive-pulse avalanche stress condition, by means of monitoring three crucial parameters, namely gate threshold voltage, drain leakage current and body diode forward voltage at regular pulse intervals throughout the test.

2 Experimental procedure 2.1 Test description The UIS test schematic circuit is shown in Figure 1. An auxiliary high voltage IGBT (3KV) is connected in parallel to the MOSFET device under test (DUT) for charging the inductor current without heating the DUT before avalanche stress is applied. The IGBT is driven with a 16V gate signal.

1 Introduction Power MOSFETs fabricated in SiC are becoming technologically mature as commercial products. Consequently, the assessment of stability and reliability becomes essential for the development of these devices [1].

L

iD

MOSFETs are often used in high speed switching applications. Back EMF (electromagnetic force) produced during device turn-off due to the abrupt change of drain current as a result of inductive loads may force the MOSFET into drain-to-source avalanche and damage the device [2]. Therefore understanding the cause of the failure under avalanche condition is essential.

DUT +

Power supply

-

VDS

VDD

RG IGBT

VGS

Avalanche breakdown of Si-based power MOSFETs is usually attributed to the activation and subsequent secondary breakdown of the parasitic bipolar junction transistor. When power is turned off, avalanche current flows to the base resistor in the source channel via intrinsic drain-source capacitor as a result of sudden change in drain voltage. The parasitic bipolar junction (BJT) is activated by the voltage fall on the base-emitter junction if the over current is large enough. Current concentrates because the BJT is switched on locally due to the high electric field intensity at the junction curvature, which causes catastrophic thermal runaway. Compared to Si p-n junction whose forward voltage is around 0.7V, the forward voltage of SiC p-n junction has much higher value (2-3V) and is less dependent on temperature [3]. Therefore the avalanche breakdown mechanism of SiC MOSFETs can be very different.

Figure 1: Schematic of the UIS test circuit Avalanche energy E is the amount of energy absorbed by the devices in the avalanche region (tAV) and theoretically can be derived by calculating the time integral of the product of the drain-source voltage VDS and the drain current ID, as shown in equation (1):

E

t t AV

t 0

VDS (t )  I D (t )dt

(1)

Then the energy can be obtained approximately by equation (2):

E

In this work, the maximum energy dissipation rate is assessed for state-of-the-art SiC MOSFET devices under single-pulse

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1 I AV VBR ( eff ) t AV 2

(2)

VBR(eff) is the effective drain-to-source breakdown voltage at peak discharge current. It is much higher than the rating breakdown value VBR(dss) in the datasheets. IAV is the peak avalanche current at which the DUT is switched off. tAV is the time it takes for the avalanche energy to dissipate.

avalanche which is much higher than the rated breakdown drain-source voltage.

2.2 Test setup

3.1 Single-pulse test results

The tested SiC MOSFET devices are commercial-off-theshelf products with the voltage and current rating of 1200V and 42A respectively [4]. During the test, the device under test was tightly screw pressed on a hotplate. Figure 3 shows the photo of the test bench.

Single-pulse tests were carried out under supply voltage (VDD) of 400V and 800V respectively. At each voltage level, case temperature was set to 75°C, 90°C and 150°C. Rated single pulse avalanche energy (EAV=1.2J) in the datasheet is applied in each event. Gate driving pulse width is gradually increased until the energy value is reached. By varying the inductance value, different peak avalanche current values can be reached and different avalanche energy dissipation rate can be made. The transient avalanche current waveforms for each test condition were plotted in Figure 4 to 9.

3 Results and discussions

Figure 4 to 6 are showing the current waveforms for 400V power supply.

Figure 2: UIS test bench The DUT is switched on when the gate of the IGBT is turned on. The inductor value and pulse width are varied and once the desired peak current and avalanche energy is reached, the gate drive is switched off which abruptly turns off the MOSFET. BK Precision 4033 programmable pulse generator is used to allow accurate adjustment of the pulse width. Figure 3 shows a set of UIS waveforms for a SiC MOSFET under one of the above test conditions.

Figure 4: Single-pulse UIS waveforms at T case=75°C, VDD=400V with various values of inductor

Figure 3: A set of UIS waveforms under a single pulse VCE is the gate pulse applied to the IGBT; iL is the drain current and VDS demonstrates the drain-to-source over voltage transient during turn-off.


It can be seen that VDS initially equals to supply voltage VDD=400V and reached approximately 1900V during the UIS

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With a power supply of 800V, the drain current at which the DUT suffered avalanche failure at case temperature of 75°C, 90°C and 150°C is 40.1A, 35.1A and 27.9A respectively.

It can be seen that with a power supply of 400V, the drain current at which the DUT suffered avalanche failure at case temperature of 75°C,90°C and 150°C is 46.1A, 39.7 and 30.1A respectively.

The single-pulse test results have shown that for a fixed supply voltage, the critical current at which DUT suffered avalanche failure decreases as the case temperature increases. It appears that the failure is related to temperature of the chip during avalanche breakdown and to the magnitude of current that is being turned off.

Figure 7 to 9 are showing the drain current waveforms for 800V power supply.

On the other side, at a fixed temperature, the energy can be safely handled during avalanche breakdown until the peak current (IAV) reaches a critical value. Moreover, while the peak current increases as the result of decrease of inductance, the time it takes for the avalanche energy to dissipate (tAV) decreases. Therefore the avalanche failure limits of power MOSFETs are in fact determined by the energy dissipation rate and not the energy value alone [5]. And the maximum energy dissipation rate that the DUT can withstand decreases as the case temperature increases. Figure 7: Single-pulse UIS waveforms at T case=75°C, VDD=800V with various values of inductor

Compared to Si p-n junction whose forward voltage is around 0.7V, the forward voltage of SiC p-n junction has much higher value (2-3V). Thus the avalanche failure in SiC MOSFETs is more likely thermal induced. It occurs when the cell temperature reaches the intrinsic temperature limit beyond which the intrinsic carrier concentration exceeds the epi doping concentration and is too high for the device to support the applied voltage [6]. 3.2 Repetitive-pulse test results For the repetitive-pulse test, two devices were tested. Tests were carried out under supply voltage (VDD) of 400V. The devices were switched off at IAV of 35A which brought about 0.7J avalanche energy. DUTs were repeatedly subjected to this avalanche condition at a case temperature of 115°C to gradually induce degradation in the devices as the number of pulses progressed. Ten seconds intermission is set between two pulses to cool the device down.


Three parameters, namely the gate threshold voltage (Vth), drain leakage current (idss) and body diode forward voltage

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(Vf) were measured at regular pulse intervals to record the evolution as the number of UIS pulses increases. The Vth is defined as the gate-source voltage at which the drain current id=5mA when VDS=VGS; and Vf is measured at if=500mA; drain leakage current was measured with a drain-source reverse bias voltage of 960V. All measurements were performed at case temperature of 115°C. The change of the three parameters Vth, Vf and iDSS as a function of the number of UIS pulses is plotted in Figure 10 to 12.

Figure 11: Evolution of body-diode forward voltage during repetitive-pulse UIS test In Figure 12, it is shown that the drain leakage current has increased during repetitive avalanche test. Drain leakage degradation after long-term high temperature drain-source biased stress is driven mainly by surface-defect-assisted tunnelling occurring in the deep-depletion layer in the gate-todrain overlap region which is formed when high voltage is applied to the drain with the gate grounded [9, 10]. In this UIS test, drain-source repeatedly suffers around 1900V breakdown voltage. Figure 10: Evolution of threshold voltage during repetitivepulse UIS test Figure 10 shows decrease of Vth in both DUTs. This may be resulted from increased oxide charge defects due to repetitive avalanche. The direction of the shift in threshold voltage is dependent on the polarity of the trapped charge [7]. Since in this test, the MOSFET gate is grounded (VGS=0V) in repetitive avalanche events, electrons generated from impact ionization are swept into the drain by the electric field, whereas the holes generated from impact ionization are injected into the gate oxide which can cause parasitic bipolar latch-up [8]. Hence, the decrease of threshold voltage can be attributed to the hole trapping in the gate oxide in this case.

Figure 12: Evolution of drain leakage current during repetitive-pulse UIS test

Figure 11 reports the change of forward voltage of the body diode during the test. The reduction in the Vf during the avalanche cycles indicates an impact of avalanche stress on the p-n junction at drain.

4 Conclusion and future work Characterization of new generation of power SiC MOSFETs has been carried out under high temperature UIS avalanche conditions. The hardware implementation is described in details. The experimental results of avalanche withstand capability of SiC-based power MOSFETs during single-pulse UIS avalanche under various test conditions have been presented and discussed as well as the investigation of degradation under repetitive-pulse condition in terms of several electrical parameters. For the single-pulse tests, we have shown that at a fixed temperature, the rated avalanche energy can be safely dissipated during single-pulse UIS until the peak current (IAV) reaches a critical value. This current value, at which UIS

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Scaling”, Electron Devices Meeting, Vol. 33, pp. 718721, 1987 [10] G. Barletta, G. Currò, “Junction Leakage Current Degradation under High Temperature Reverse-Bias Stress Induced by Band-Defect-Band Tunnelling in Power VDMOS”, Microelectronics Reliability, pp. 994999, 2005

failure occurs, decreases as case temperature increases. And the maximum energy dissipation rate that the device can withstand decreases as the case temperature increases. In the repetitive-pulse tests, decrease of gate threshold voltage and drain-body diode forward voltage is observed as well as increase in drain leakage current as the number of avalanche cycle progressed. Although the changes in these parameters are not very significant throughout the test probably due to the insufficient number of avalanche pulses, they still show noticeable degree of degradation in the devices by repeated UIS avalanche stress. In the subsequent work, different values of avalanche energy will be applied to the DUTs at different temperatures and peak current in order to further investigate the influence of temperature, level of EAV and energy dissipation rate on device degradation caused by the stress applied on the device as a result of UIS avalanche energy dissipation.

References [1] M. Treu, R. Rupp and G. Sölkner, “Reliability of SiC Power Devices and its Influence on their Commercialization – Review, Status, and Remaining Issues”, IEEE IRPS, pp. 156-161, 2010. [2] K. Fischer, K. Shenai, “Dynamics of Power MOSFET Switching under Unclamped Inductive loading Conditions”, IEEE Transactions on Electron Devices, pp. 1007-1015, 1996 [3] B.J. Baliga, “Silicon Carbide Power Devices”, River Edge, NJ, USA: World Scientific, 2012 [4] http://www.cree.com/power/products/1200v-sic-

mosfetpackaged/packaged/~/media/Files/Cree/Power/Dat a%20Sheets/CMF10120D.pdf [5] D. L. Blackburn, “Power MOSFET Failure Revisited”, IEEE, Power Electronics Specialists Conference, pp.681-188, 1988 [6] C. Blake, T. McDonald, D. Kinzer, J. Cao, A. Kwan and A. Arzumanyan, “Evaluating the Reliability of Power MOSFETs,” Power Electronics Technology, pp. 40-44, 2005 [7] A. Lelis, D. Habersat, R. Green, A. Ogunniyi, M. Gurfinkel, J. Suehle and N. Goldman, “Time Dependence of Bias-Stress-Induced SiC MOSFET Threshold Voltage Instability Measurements”, IEEE Transactions on Electron Devices, Vol. 55, No. 8, pp. 1835-1840, 2008 [8] O. Alatise, I. Kenndy, G. Petkos, K. Heppenstall, K. Khan, J. Parkin, A. Koh, and P. Rutter, “The impact of repetitive unclamped inductive switching on the electrical parameters of low-voltage trench power nMOSFETs,” IEEE Trans. Electron Devices, Vol. 57, No. 7, pp. 1651– 1658, July. 2010 [9] T. Y. Chan, J. Chen, P. K. Ko and C. Hu, “The Impact of Gate-Induced Drain Leakage Current on MOSFET

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