Chip-level integration of RF MEMS on-chip ... - Semantic Scholar

Microsyst Technol (2008) 14:1429–1438 DOI 10.1007/s00542-007-0532-9

TECHNICAL PAPER

Chip-level integration of RF MEMS on-chip inductors using UV-LIGA technique Daniel Sang-Won Park Æ Youngkyun Jeong Æ Jeong-Bong Lee Æ Sungyong Jung

Received: 12 July 2007 / Accepted: 16 December 2007 / Published online: 8 January 2008 Ó Springer-Verlag 2008

Abstract This paper presents a chip-level integration of radio-frequency (RF) microelectromechanical systems (MEMS) air-suspended circular spiral on-chip inductors onto MOSIS RF circuit chips of LNA and VCO using a multi-layer UV-LIGA technique including SU-8 UV lithography and copper electroplating. A high frequency simulation package, HFSS, was used to determine the layout of MEMS on-chip inductors with inductance values close to the target inductance values required for the RF circuit chips within the range of 10%. All MEMS on-chip inductors were successfully fabricated using a contrast enhancement method for 50 lm air suspension without any physical deformations. High frequency measurement and modeling of the integrated inductors revealed relatively high quality factors over 10 and self-resonant frequencies more than 15 GHz for a 1.44 nH source inductor and a 3.14 nH drain inductor on low resistivity silicon substrates (0.014 X cm). The post-IC integration of RF MEMS onchip inductors onto RF circuit chips at a chip scale using a multi-layer UV-LIGA technique along with high frequency measurement and modeling demonstrated in this work will open up new avenues with the wider integration feasibility of MEMS on-chip inductors in RF applications for costeffective prototype applications in small laboratories and businesses.

D. S.-W. Park (&) J.-B. Lee The University of Texas at Dallas, Richardson, TX, USA e-mail: [email protected] Y. Jeong S. Jung The University of Texas at Arlington, Arlington, TX, USA

1 Introduction With the recent growth in wireless communication applications including wireless personal communication systems such as cellular phones, satellite communications, and military communications, a significant amount of research and work has been carried out to further develop highly integrated radio-frequency (RF) systems with high RF performance and low cost. Even though GaAs and SiGe bipolar technologies can provide high RF performances including high gain, high linearity, and low noise (Dodo et al. 2003; Erben and Sonmez 2004; Nishikawa et al. 2002; Reynolds et al. 2003), CMOS technology has been the mainstream process because of the advantages in the high level of integration and cost reduction over GaAs and SiGe technologies (Vassiliou et al. 2003; Woerlee et al. 2001). However, fully integrated CMOS RF circuits such as low noise amplifiers (LNAs) and voltage-controlled oscillators (VCOs) on standard CMOS silicon substrates show poor RF performances in noise figure, phase noise, and power consumption, because the monolithic, planar onchip inductors used along with LNA and VCO suffer from a low quality factor (Q-factor) due to the metal ohmic loss and conductive substrate loss (Tilmans et al. 2003). Hence off-chip discrete inductors and bond-wire inductors (Dec and Suyama 2000; Svelto and Castello 2002) have been used in the RF applications to provide high quality factor so as to improve the overall RF system performances. But off-chip inductors usually occupy large areas of the RF systems, and bond-wire inductors have a limitation in process repeatability. RF microelectromechanical systems (RF MEMS) technology has been emerging as an alternative to provide major advantages on the existing RF architectures in

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wireless communication applications such as reduced weight, size, cost, noise, and power consumption over the conventional counterparts (Katehi et al. 2002; Tilmans et al. 2003; Yao 2000). Many research work for RF MEMS inductors have been carried out to improve Q-factor and self-resonant frequency (SRF) using the partial removal of the Si substrate underneath the planar spiral inductors (Chang et al. 1993), self-assembly of the out-of-plane inductors (Chua et al. 2003), and solenoid-based inductors (Lu et al. 2004). However, still the integration of MEMS inductors onto real microelectronics circuitry is challenging. Park et al. reported the integration of air-suspended rectangular spiral inductors onto electronic circuits for VCO applications using positive photoresist based surfacemicromachining techniques at a wafer-level (Park et al. 2003). Such a wafer level integration of RF-MEMS inductors might not be affordable in small laboratories and businesses. In this work, a chip-level integration of RF MEMS airsuspended circular spiral on-chip inductors onto RF circuitry was carried out to demonstrate the usefulness of the RF MEMS inductors for RF applications when low resistivity silicon substrates (0.014 X cm) were used. Such integration performed at a chip-level can satisfy the high demands for prototype integration in small laboratories and businesses.

2 Circuit design for LNA and VCO Generally the RF performances in LNA and VCO such as noise, gain, and power consumption in typical RF circuits and systems depend on the circuit topology used, the minimum noise figure (Fmin) of the active device, and the quality factor of inductors (Kim et al. 1998; Rebeiz 2003; Tang et al. 2002). The phase noise is inversely proportional to the square of the quality factor of an LC tank used in VCO (Park et al. 2003). Hence high-Q RF MEMS on-chip inductors can be used for reduced noise and power consumption, and increased gain in LNA, and for lower phase noise and power consumption in VCO in general wireless transceiver applications. Two examples of RF circuits including LNA and VCO were designed to take advantages of RF MEMS on-chip inductors using RF circuit simulation tools such as ADS 2002C and Hspice (Jeong et al. 2004).

2.1 LNA A simple single stage circuit employing a common source with inductive source degeneration type was used for the design of the LNA circuit, as shown in Fig. 1a. The channel width of the transistor, 400 lm, was used for

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Fig. 1 Circuit diagrams for a LNA and b VCO

the low minimum noise figure (Fmin) and high gain. The source inductor Ls and the gate inductor Lg were used for input matching, and the drain inductor Ld was used for output load and matching. RF Simulation was carried out to determine the proper values of RF MEMS on-chip inductors on the LNA with the target operating frequency of 1.45 GHz, gain of over 10 dB, and noise figure (NF) of less than 3 dB. From the simulation, the inductance values of the source inductor, the drain inductor, and the gate inductor were determined as 1.50, 3.44, and 7.66 nH, respectively. Off-chip LC matching and DC block capacitors for effective impedance matching can be used on a printed circuit board for performance measurement.

2.2 VCO As an another example for the integration of RF MEMS on-chip inductors with RF circuitry, a cross-coupled differential VCO scheme was selected because of its large voltage swing and robustness against parasitic effects. Figure 1b shows a schematic representation of VCO with MEMS inductors and MOS varactors. Two cross-coupled MOS transistors can provide transconductance to improve the RF performance. The values of the resonance for RF MEMS inductors and MOS varactors were decided for the


target resonant frequency of 2.4 GHz, the power consumption of less than 25 mA, and the range of tuning frequency over 740 MHz (2.2–2.94 GHz) with MOS varactor bias voltages of 0–5 V. The widths of nMOS transistors were optimized for the minimum thermal noise. The determined inductance values of the RF MEMS on-chip inductors and the capacitance of the MOS varactor for 2.4 GHz operations were 1.5 nH and 2.8 pF, respectively.

3 HFSS simulation In order to more accurately predict the RF performance of MEMS on-chip inductors, high frequency computer simulation using finite element modeling technique is essential. A commercial high frequency simulation package, HFSS, was employed to determine the layout of MEMS on-chip inductors on RF circuit chips in the overall dimensions of 500 lm by 500 lm for LNA inductors and 400 lm by 400 lm for VCO inductors. Since the RF circuit chips were fabricated using Taiwan Semiconductor Manufacturing Company (TSMC) 0.35 lm technology (MOSIS, http://mosis.org/products/fab/vendors/ tsmc/), information about the substrate is of great

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importance for accurately simulating the RF MEMS onchip inductors on MOSIS substrates and obtaining the required inductance values used in LNA and VCO. The TSMC 0.35 lm technology uses a low resistivity 250 lm thick substrate (0.008–0.020 X cm) with passivation layers of 2 lm thick silicon dioxide and 4 lm thick silicon nitride. In HFSS simulation, 250 lm thick silicon substrates with the resistivity of 0.014 X cm were used along with passivation layers of silicon dioxide and silicon nitride. Figure 2 shows the configurations of RF MEMS on-chip inductors simulated in HFSS. The dimensions used for all air-suspended circular spiral inductors were width and spacing of 10 lm and air suspension gap of 50 lm with a coil thickness of 15–20 lm to provide wide fabrication process margin. The air gap of the inductor coils from the substrate was chosen as 50 lm to reduce the substraterelated parasitic loss and the thickness of the circular onchip inductors was selected to be 15–20 lm in order to obtain low series resistance. The outer diameter of the inductor coils and number of coil turns were varied in order to obtain the inductance values to closely match to the target inductance values while keeping enough inner diameter of the inductor coils to minimize the proximity effects due to eddy current produced from the magnetic field of the inductor coil.

Fig. 2 Geometries of RF MEMS on-chip inductors in HFSS simulation: a LNA source inductor, b LNA drain inductor, c LNA gate inductor, and d VCO inductor

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In order to eliminate parasitic effects from ground planes and signal pads from the device under the test (DUT) inductors, de-embedding of these parasitic was essential (Arcioni et al. 1998). Two sets of high frequency simulations were carried out for all MEMS on-chip inductors (one for the DUT inductor with ground planes and signal pads and the other for no inductor with ground planes and signal pads) to obtain scattering parameters (S-parameters). S-parameters from each set were converted into y-parameters. The parasitic effects of the ground planes and signal pads next to the DUT inductor was removed by subtracting y-paramters for no inductor with ground planes and signal pads from y-parameters for DUT inductor with ground planes and signal pads. Such subtracted y-parameters were used to obtain series inductance values from high frequency simulation using an equation of Ls = Im(-1/y12)/x where x = 2pf and f is a frequency. Table 1 shows the comparison between the target inductances and the simulated inductances at target frequencies. The simulated inductance values were close to the target inductance values within the range of 10%. Fig. 3 An optical photomicrograph of a MOSIS chip with LNA and VCO RF circuits

4 Fabrication As described, RF circuit chips were fabricated from MOSIS using TSMC 0.35 lm technology (MOSIS). Three optical masks were prepared using the electron beam lithography (EBL) system at UT-Dallas based on the MOSIS design file used for the fabrication of RF circuit chips and the layout of the RF MEMS on-chip inductors obtained from HFSS simulation. Because the integration process starts on an RF circuit chip (shown in Fig. 3), special attention should be given prior to the application of UV-LIGA technique for inductor fabrication. The small chip should be attached to a carrier substrate so that there is no handling problem in the subsequent processing (Park et al. 2004). The chip was placed at the center of 3-inch oxidized silicon wafer and four supporting Si pieces with nearly the same thickness of the chip were placed right next to the chip using SU-8 2002 (MicroChem Corp., Newton, MA, USA) as an adhesive (Fig. 4a). The chip and supporting Si pieces were gently pressed by a cotton swab to ensure the attachment. Table 1 Comparison between the target and simulated inductances Target

Simulation

Ls at 1.45 GHz

1.50 nH

1.44 nH

Ld at 1.45 GHz

3.44 nH

3.56 nH

Lg at 1.45 GHz

7.66 nH

7.30 nH

VCO inductor at 2.4 GHz

1.50 nH

1.65 nH

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Planarization of the chip and the Si pieces was made by clamping the stack of a transparency film/the chip with four supporting Si pieces/the carrier substrate within the sandwich configuration including a flat Si wafer, a thick PDMS sheet, and two flat glass plates (Fig. 4b) during a bakingstep in an oven. After removing the transparency film, the cover Si substrate, thick PDMS sheet, and glass plates, a bi-layer of 10 nm Cr/200 nm Cu seed layer was coated on the sample by magnetron sputtering. The thick 200 nm Cu seed layer was used to ensure the step coverage of the seed layer throughout the sample and a Cr layer was used as an adhesion layer. Figure 5 shows the overall process sequence for the post-IC integration of RF MEMS on-chip inductors onto RF circuit chips using a multi-layer UV-LIGA technique including SU-8 UV lithography and copper electroplating. For the 1st SU-8 layer process, OmnicoatTM (MicroChem, Newton, MA, USA) was applied by spin coating at 3,000 rpm for 30 s and baked at 65°C for 30 min in an oven. This OmincoatTM provided better adhesion between SU-8 and the copper seed layer, and it was removed in a typical de-scum process upon completion of the SU-8 process. Then, 10 lm thick SU-8 2010 was coated on the sample at 3,000 rpm for 30 s. After pre-baking of the sample with the two-step baking (2 min at 65°C and 2 min at 95°C) on a hot plate, it was exposed by a conventional UV lithography system (Quintel Ultraline 4000 series mask aligner, Morgan Hill, CA, USA) with a 1 kW broadband


Fig. 4 Schematics of a a MOSIS chip with four supporting Si pieces on a carrier Si substrate and b a sandwich method with clamps

mercury UV lamp at a dose of 130 mJ/cm2 and post-baked using the two-step baking (2 min at 65°C and 2 min at 95°C) on a hot plate. After cooling the sample to room temperature, the sample was developed in SU-8 developer, propylene glycol methyl ether acetate (PGMEA, MicroChem Corp.), for 2 min, rinsed by IPA, and dried in an oven at 65°C for 5 min. In order to de-scum the sample, the sample was cleaned using 100% oxygen plasma in a Technics Micro-RIE series 85 reactive ion etcher (RIE) at a working pressure of 150 mTorr and an incident power of 100 W for 3 min (Fig. 5a). Prior to electroplating process of the 1st bottom metal layer for underpass and signal pads, the sample was cleaned in 5% H2SO4 solution for 5 s to remove Cu oxide on the Cu seed layer. Then the sample was immersed in copper electroplating solution (CuSO45H2O (cupric sulfate) 250 g and H2SO4 (sulfuric acid) 50 ml in 1 l de-ionized water) and the current density was set at 5 mA/cm2 to obtain the first metal layer. It took approximately 2 h with a deposition rate of about 5 lm/h at room temperature (Fig. 5b). After rinsing the sample thoroughly in DI water and drying in air, SU-8 2025 was spun on the sample at

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2,100 rpm for 30 s for a 40 lm thick SU-8 2nd layer to get vias between the bottom metal layer and the top metal spiral coils. Then the sample went through prebaking (4 min at 65°C and 5 min at 95°C on a hot plate), UV-exposure, post-baking (2 min at 65°C and 3 min at 95°C on a hot plate), and development steps. Here a contrast enhancement method was applied using CEM388SS (ShinEtsuMicroSi, Phoenix, AZ, USA) as a contrast enhancement material and BC-7.5 as a barrier coat to improve the SU-8 lithography performance (Lu et al. 2007). The photo bleachable solution CEM-388SS is initially opaque to the UV light and later becomes nearly transparent to UV light during continuous UV exposure. It acts as a conformal contact mask so as to provide higher contrast in exposed regions than unexposed regions for enhanced lithography results. The BC-7.5 was used as barrier coat to prevent diffusion of CEM to SU-8. After pre-baking, a barrier layer was coated on top of the pre-baked SU-8 layer at 4,000 rpm for 30 s and dried in air. Then the CEM-388SS layer were spun on the sample at 2,000 rpm for 30 s and dried in air followed by the UV-exposure step. For a typical 40 lm thick SU-8 film, the UV exposure dose would be 250 mJ/cm2, but the 40 lm thick SU-8 with CEM required an increased dose of 350 mJ/cm2. The barrier coat and CEM layer were stripped away by DI water, followed by the two-step post-baking, SU-8 development, and IPA rinse. After drying the sample at 65°C for 5 min in an oven, a de-scum process was done by the same condition as for the first SU-8 layer (Fig. 5c). Electroplating was carried out by the same condition as the 1st layer metal electroplating process to obtain 40 lm thick via structures (Fig. 5d). Once electroplating for via structures was done, the sample was rinsed thoroughly in DI water and dried in air. Then a 20 nm Cu layer was coated by magnetron sputtering as a seed layer for the metallic spiral coils. This Cu seed layer did not require an adhesion layer such as Cr, because the adhesion between Cu and the 2nd SU-8 layer was good. Prior to the application of SU-8, OmnicoatTM was applied to enhance adhesion between SU-8 and the copper seed layer by the same process used for the 1st layer. Then the SU-8 3rd layer was formed using SU-8 2010 at 1,000 rpm for 30 s to yield 20 lm thick electroplating mold by the same UV-lithography step described above (Fig. 5e). The two-step pre-baking was done on a hot plate (2 min at 65°C and 3 min at 95°C). Then the contrast enhancement method with CEM-388SS and BC7.5 was used for the 3rd SU-8 layer process before the UVexposure with a dose of 330 mJ/cm2. After rinsing away the layers of CEM-388SS and BC-7.5 in DI water, the sample was post-baked on a hot plate (2 min at 65°C and 2 min at 95°C). Upon the development of the sample in

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Fig. 5 Overall process sequence for the integration of RF MEMS on-chip inductors on a RF circuit chip: a 1st layer SU-8 process, b 1st layer copper electroplating for pads and underpass, c 2nd layer SU-8 process, d 2nd layer copper electroplating for vias, e 3rd layer SU-8 process, f 3rd layer copper electroplating for inductor coils, and g a released inductor

SU-8 developer for 2 min and de-scum steps of the sample, the final electroplating was performed to obtain 15–20 lm thick spiral coils (Fig. 5f). In order to reveal the air-suspended MEMS spiral inductors, the removal of all the SU-8 mold structures (three layers) was needed. The top 20 lm thick SU-8 layer was removed in RIE with 20% CF4/O2 plasma at a working pressure of 300 m Torr and an incident power of 300 W for 30 min. Since there was a 20 nm thick Cu seed layer, which blocked further SU-8 etching in RIE, the Cu layer was etched away in Cu etchant (1:1:40 volume ratio of H2SO4:H2O2:DI water) for about 1–2 s. Then two steps of 30 min plasma etching using RIE were carried out to remove about 30 lm SU-8 from the 40 lm thick 2nd SU-8 mold structures for reduced stress from temperature variation during RIE process. Because it was difficult to remove SU-8 right under metallic spiral coils by anisotropic RIE plasma etching, it was necessary to use isotropic plasma ash (300 series MW plasma system, PVA Tepla America, Inc., Corona, CA, USA) to remove the remaining SU-8 layer. Such process was carried out in a microwave plasma asher

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using 25% CF4/O2 plasma at a working pressure of 700 m Torr with an incident power of 500 W until complete removal of SU-8 at a typical etch rate of 1 lm/min. Then the bottom copper seed layer was removed in the same Cu etchant and Cr layer was etched away in Cr etchant (a solution of 20 g:20 g:100 ml of NaOH:K3Fe(CN)6:H2O) (Fig. 5g). Figure 6 shows the scanning electron microscopy (SEM) photomicrographs of the micromachined air-suspended circular spiral inductors on the RF circuit chip. Figure 6a shows the overall top-view of the chip and Fig. 6b shows the top-view of the three MEMS on-chip inductors for LNA. The tilted views of three inductors (source, drain, and gate inductors) are shown in the following figures (Fig. 6c– e). Figure 7a shows the top-view of inductors for VCO with a tilted-view of a VCO inductor (Fig. 7b). All MEMS onchip inductors were suspended approximately 50 lm from the chip surface to minimize the capacitive parasitic coupling to the substrate. Electroplated copper in spiral coils had the thickness of 15–20 lm so that the Q-factor can be maximized due to low resistivity of copper.


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Fig. 6 Scanning electron microscopy (SEM) photomicrographs for a an overall top view of the MOSIS chip, b a top view of three inductors for LNA, and close-up views of c source inductor, d drain inductor, and e gate inductor

5 High frequency characterization of RF MEMS inductors on MOSIS chips In order to effectively remove parasitic effects from the ground planes and signal pads, two DUT inductors and de-embedding dummy pad structures of ground planes and signal pads without an inductor were also fabricated on two chip dies. Figure 8a shows a DUT inductor and dummy pad structures and Fig. 8b shows the tilted-view of the DUT inductor. In order to characterize the RF performances of such MEMS on-chip inductors on RF circuit chips, it was necessary to measure a series of S-parameters of the fabricated MEMS on-chip inductors on MOSIS chips in order to better understand the MOSIS substrate effects on the quality factor and inductances of the inductors. The S-parameters were obtained using an Anritsu 37369A integrated vector network analyzer (VNA) (40 MHz–40 GHz)

together with two Cascade HPC40-150 GSG RF probes. The measurements were made in a Cascade Summit 12k semi-automatic environmentally controlled probe station using Cascade’s WinCal v2.3 calibration software to perform a line-reflect-reflect-match (LRRM) probe-tip calibration. The measured S-parameters were converted into y-parameters, which were used for de-embedding process to eliminate parasitic effects from ground planes and signal pads in the DUT inductors. The de-embedded y-parameters were used for extraction of RF MEMS on-chip inductor parameters for the source and drain inductors with a lumped physical model (Fig. 9). Ls is a series inductance, Rs is a series resistance, and Cs is an inter-turn fringing capacitance and a metal overlap coupling capacitance between the spiral and underpass metal layers. Cp and Rp are parasitic capacitance and resistance due to the air gap, passivation layers, and substrate. The inductor parameters

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Fig. 7 SEM photomicrographs for a an overall top-view of inductors for VCO and b close-up view of VCO inductor

of Rs, Cp, Rp, and Q-factor were extracted using the follwing: RS ¼ Reð1=y12 Þ Imðy11 þ y12 Þ CP1 ¼ x 1 RP1 ¼ Reðy11 þ y12 Þ Imðy22 þ y21 Þ CP2 ¼ x 1 RP2 ¼ Reðy22 þ y21 Þ R xLs p Qinductor ¼ 2 Rs xLs Rp þ þ1 Rs Rs R2 Cs þ Cp 1 s x2 Ls Cs þ Cp Ls 1 Imðy11 Þ ¼ Reðy111 Þ

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Fig. 8 SEM photomicrographs for a an overall top-view of a DUT inductor and dummy pad structures, and b a close-up view of a DUT inductor

Fig. 9 A lumped physical model of a RF MEMS on-chip inductor


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The value of Cs was determined graphically using the equation for the Q-factor and the self-resonant frquency (SRF) was found in the graph of the Q-factor as a function of frequency. Figure 10 shows two graphs of the extracted Q-factors and the corresponding lumped physical models for source and drain inductors at 1.45 GHz on the MOSIS TSMC RF circuit chips. These models obtained on real MOSIS low resistivity Si substrate can be used in RF circuit simulations to achieve better RF performance optimizations. Table 2 shows the comparison between HFSS simulation results and measurement results for source and drain inductors. The differences between HFSS simulation and measurement results can be explained by

the variation in physical dimensions during processing sequence of the chip-level integration of RF MEMS onchip inductors. The measured results showed a relatively high quality factor of over 10 and self-resonant frequency of more than 15 GHz for a 1.5 turn, 1.44 nH source inductor and a 3.5 turn, 3.14 nH drain inductor by utilizing the thick electroplated copper for low metallic ohmic loss and the air suspension of 50 lm from the substrate for low conductive substrate loss. The results from simulation and measurement were in reasonably good agreement, confirming the use of high frequency electromagnetic simulation of HFSS can be used for highly accurate prediction of RF parameters of the MEMS on-chip inductors on low resistivity MOSIS Si substrates.

6 Conclusions

Fig. 10 High frequency measurement results of Q-factors and the corresponding lumped physical models (at 1.45 GHz) for a the source inductor and b the drain inductor Table 2 Comparison of HFSS and high frequency measurement results for source and drain inductors

Parameters

Integration of RF MEMS air-suspended circular spiral onchip inductors onto MOSIS RF circuit chips of LNA and VCO was demonstrated at a chip-level using a multi-layer UV-LIGA technique including SU-8 UV lithography and copper electroplating. A commercially available, high frequency simulation package, HFSS, was used to determine the layout of RF MEMS inductors with inductance values close to the target inductance values within the range of 10%. All MEMS on-chip inductors were successfully fabricated using a contrast enhancement method for 50 lm air suspension of the inductor coils from the substrate surface and did not show any physical deformations. High frequency measurement and modeling of the integrated inductors revealed the usefulness of the RF MEMS air-suspended circular on-chip inductors on conductive silicon substrates with relatively high quality factors over 10 and self-resonant frequencies of more than 15 GHz for a 1.5 turn, 1.44 nH source inductor and a 3.5 turn, 3.14 nH drain inductor by using the electroplated thick copper to minimize the resistive loss and the air suspension of 50 lm to minimize the conductive substrate loss on low resistivity Si substrates (0.014 X cm). The demonstration of the post-IC integration of RF MEMS on-chip inductors onto RF circuit chips at a chip level using a multi-layer UV-LIGA technique along with high frequency measurement and modeling will widen the

Ls (source inductor) HFSS

Ld (drain inductor) Measurement

HFSS

Measurement

Ls at 1.45 GHz

1.46 nH

1.44 nH

3.56 nH

3.14 nH

Peak Q

18 at 5.37 GHz

11.3 at 1.29 GHz

16.8 at 3.36 GHz

12.7 at 1.69 GHz

Q at 1.45 GHz

13.2

10.7

13.68

12.5

SRF

35 GHz

31.1 GHz

17 GHz

17 GHz

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integration feasibility of MEMS on-chip inductors in RF applications for cost-effective prototype applications in small laboratories and businesses. Further optimization in HFSS and the use of metallic, patterned ground shields underneath inductor coils (Carchon et al. 2004) can provide higher Q-factor for given inductances. The RF performance measurements of LNA and VCO together with RF MEMS on-chip inductors can be performed on printed circuit boards and such verification will lead to the further application of RF MEMS inductors to the other RF circuit blocks such as power amplifiers in wireless transceiver system applications. Acknowledgments This work was supported in part by the National Science Foundation under the grant ECS-0296108. The authors would like to thank PVA TePla for equipment support (TePla 300 microwave plasma etch system). The supports of UTD clean room staffs and UTD Micro/Nano Devices and Systems Laboratory are acknowledged.

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