2012 International Conference on Computing, Electronics and Electrical Technologies [ICCEET]
Clock Frequency Doubler Circuit for Multiple Frequencies and its Application in a CDN to Reduce Power
Abstract-
John Reuben
Abishek Anuroop & Dr.Harish M Kittur
SENSE, VIT University,
SENSE, VIT University,
Vellore, India
Vellore, India
[email protected]
[email protected]
The frequency doubler(FO) circuit has found
immense use in digital CMOS systems. Such a circuit is especially useful in a clock distribution network where the clock signal can be distributed at a low frequency and multiplied (clock frequency made 2 or 4 times) at the blocks where a higher frequency is needed. This reduces the power consumption
of
the
clock
distribution
network.
Tree
Clock
Frequency Multiplier circuits are also useful in chips to generate clock signals which are mUltiples of the available clock frequency generated by the oscillator. In this paper, we
Tnmk
have designed a clock frequency doubler circuit suitable to reduce power consumption in a clock distribution network.
M.. h
The FO doubles fixed frequencies namely 250 MHz, 500MHz and 1 GHz. It also doubles frequency 10% around these fixed frequencies. The simulated circuit consumes only 411 pW of power and has a propagation delay of only 43.75nS.This FigureI: The trunk, tree and mesh CON [5]
circuit was then connected at the 4 leaves of a H-tree global CON to double the clock frequency. This CON achieved 50.2 % power savings when compared to a CON distributing clock
The H-tree CON is particularly popular since it achieves
at the target frequency Keyword:
the same delay at all its leaf nodes. Suppose we have a circuit
Clock Distribution Network (CON),
scaling, distributed 3 segment
11:
at node 8(Figure2) in a H-tree CON which works at 1 GHz.
frequency
We can feed 500 MHz clock at node A and convert it to IGHz
RC model
clock when needed at 8 instead of sending I GHz clock from node A
I .1NTROOUCTION The
frequency
doubler(FO)
circuit
has
found
immense use in digital CMOS systems [6]. Such a circuit is especially useful in a CON. The CON constitutes one of the most important parts of a synchronous Very Large Scale
-
segment
Integration (VLSI) chip as it can significantly influence the
o l. 9 .o �-
needed [2]. Typically, global CON span the entire area of the chip
and
therefore
meters).Consider
they
FigureI
can
be
which
very shows
long
(in
different
milli clock
A eLK,
Figure 2: H-tree CON [2]
distribution strategies.
978-1-4673-0210-4112/$31.00 ©2012 IEEE
B lIffe r
752
2012 International Conference on Computing, Electronics and Electrical Technologies [ICCEET]
Hence the clock gets delayed by 0.5 nS(which is T/4 for a 500
Transporting the clock at a reduced frequency across the CON will achieve tremendous power savings according to the
MHz clock) at the output of Mux.(The propagation delay
well known CMOS power dissipation equation
through the Mux can be neglected because of its judicious design).Hence we will get 1 GHz clock at the output after xor
Power
=
CL.VDD
2
.f
operation.
(1)
CL - load capacitance, VDD - power supply and f is switching frequency of the signal
Clock f
The frequency doubler(FD) circuit to be used in a CON
---.----�
must be designed in such a way that the power consumed by it and the power dissipated in the CDN(at half the target
Select
lines
frequency) together must be lesser than the power dissipated if the
clock was distributed at the target frequency. Hence we
need a low power frequency doubler circuit. Secondly, we need the frequency doubler circuit to accommodate a wide range of input frequencies. Different parts of a chip may function at different frequencies and the FD circuit must be able to take any frequency(typically MHz to GHz) range and
Figure 4: Frequency doubler circuit
double it. In this paper, we are presenting such a circuit. Section II describes the design of the FD circuit. Section III describes the design of H-tree CMOS CON in TSMC 180 nm
The delay elements are designed using cascaded inverters
process. The simulation methodology and results are discussed
as shown in Figure 5.The capacitors are implemented using
in section IV. We conclude with possible future work in
transistors. The 4: 1 Mux is designed using Transmission
section V.
gates(TG) as shown in Figure 6.TG based Mux helps to reduce power consumption because they operate without power
II .FREQUENCY DOUBLER CIRCUIT
supply.
A. Fundamental concept of clockfrequency doubling Oelayby Tl4
ru�DNt ,
+
Figure 5 : Delay element
Clock of I)enod TI.
Clock of period T
T
Figure 3: Basic circuit so
�
When a symmetrical clock signal (50% duty cycle) is delayed by T/4 and XORed with itself, we get a clock of
DO
period T/2 [6] as shown in Figure3. Though the circuit is very simple, delaying the clock by T/4 is a complex task. The
50.
reason is the delay element must be adjustable because it has to delay clocks of different frequencies. Hence we cannot use
DJ.
a fixed delay element to double different frequencies.
s
B. Design ofFD circuit
=r
�
D2
5J.
5 ),"
The FD circuit (Figure 4) is designed using a Mux to
5J.
generate different delays according to the input frequency. We have designed this FD circuit to double 250 MHz, 500 MHz
D3
and 1 GHz frequencies. Based on the frequency to be doubled,
-r-
the select lines are chosen. This circuit can be extended to work for other frequencies by suitable modifications. Each
3:=
so
'0'
in the circuit represents a delay element of 0.25 nS delay. Two
Figure 6: TG based 4: 1 MUX
inverters cascaded can act as a delay element. When the input is 500 MHz, the select lines are so chosen that the first 2 delay elements (from left) are included at the input to the Mux.
753
2012 International Conference on Computing, Electronics and Electrical Technologies [ICCEET]
IV .SIMULATION METHODOLOGY AND RESULTS
With the appropriate select lines chosen, this FD circuit will be able to convert 250 Mhz, 500MHz and 1 GHz into 500
The FD circuit was designed and implemented in 0.18 11m
MHz,l GHz and 2 GHz respectively.
technology. We have used Design Architect tool of Mentor Graphics to do a transistor level simulation. The Figure
III. DESIGN OF H TREE CDN Parasitic resistance and capacitance of interconnect
(Figure 8) below shows the simulation result for a 500 MHz
has become a dominant factor as the minimum feature size of
clock doubled to 1 GHz clock. The propagation delay of the
IC chip is shrinking. Hence we need to consider them for
entire FD circuit is 43.75 nS and the power consumption is
accurate simulation. The resistance of a wire is proportional to
only 411 pW.
its length,
I and inversely proportional to its width, w.
a Transient Results (Wave:2)
Therefore, the resistance will increase if the wire length is longer and narrower. The wire capacitance has 2 major components: the parallel plate capacitance of the bottom of the wire to ground and the fringing capacitance arising from fringing fields along the edge of a conductor with finite thickness. In addition, the
� �
adjacent wire on the same layer can exhibit capacitance to the
�
neighbor
[9].
The
calculation
for
area
and
�
fringing
capacitances are given by equation (2) and (3) below. Area (parallel plate) capacitance, Care a = w, l C1
(2)
12 1.0
0.8 0.6 0.' 0.2 0.0
-to>! Delav: 43.752 Ps Y1 2.0 -,------+1.8 �_-"\Otltpul clock.1 GHz 1.6 1.4 12 1.0 0.8
\
� �
Fringing capacitance,
�
2( w+ l) . Cz (3) where wis wire width, I is wire length, C1 is inter-layer area Cfringe
Y1 2 . 0 -,----1.8 InlHlI Clock. 500 MHz 1.6 I..
=
�
0.6 0.4
0.2 0.0
capacitance per unit area, Cz is inter-layer fringing capacitance per unit length. C1 and Cz are bounded by the process
O.ON
parameters. Clearly, from equation (2) and (3), capacitance increases when both wand
(
I are increased.
O.SH
1.0N
l.SN
2.0N
lON
2.SN Time (5)
Figure 8: Simulation of FD circuit for 500MHz clock
To design a H- tree CDN, we have considered TSMC CMOS 0.18 11m process technology. In this process, top level metal layers(M4 ,M5,M6) are typically used for power,
B
ground and clock routing. We used the same parameters as in
A
[3] to model the H-tree CDN. We considered a 285.72 11m by 285.72 11m H-tree clock routed in metaI4(M4) layer. We modeled the interconnect M4 wire using a 3-segment
1t-
RC
model [7] to extract the parasitic resistances and capacitances of the interconnect wire. Modeling the interconnect wire by a 3-segment
1t
distributed RC model (Figure 7) achieves less
than 3% error which is reasonably accurate.
RI3
Rl3
L I
Rl3
3-seClinent 1T model 1_""""':'I:--_13-seClinent 1T model RC network RC network
� I
Input clock, f
FD . frequency doubler
A,B,C,D. output clock, 2f
Figure 7: Three-segment
1t
distributed RC model [3]
D
C
Figure 9: Simulation model of H-tree CDN with FD at leaf nodes.
754
2012 International Conference on Computing, Electronics and Electrical Technologies [ICCEET]
The final circuit we simulated is shown in figure 9.An input
10% tolerance for the input frequency to be doubled. For
clock of 500 MHz was fed and the output at nodes A,B,C and
example frequencies 450 MHz and 550 MHz are still doubled
o were observed. Figure 10 shows the 500 MHz input clock
by the FO circuit, except for a change in the duty cycle(not
and the doubled clock outputs observed at node A and
exactly 50%). Figure 11-a and 11-b verifies the same for 450
O.(Outputs at node B and C are not shown due to lack of
MHz and 550 MHz. For both these cases, there are two rising
space).We can see how the clock frequency gets doubled at
edges of the output clock within half the input clock.
the four nodes without any distortion and significant clock skew.
Yl 2.0
Y1 2.0 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0 0.4 > 0.2 0.0 -0.2
1.8 1.6
Inout clock. 500 MHz
� '"'" �
1.4
EY--
1.2
� '"01 �
1.0
0 >
Y1 2.0 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0 0.4 > 0.2 0.0 -0.2
0.6
04
.
0.2
0.0
-0.2
� '"'" �
Y1 2.0
- � 1.4 � 1.2 '"01 1.0 � 0.8 0 0.6 > 0.4 0.2 0.0 1.8
;---'\
1.6
Y1 2.0 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0 0.4 > 0.2 0.0 -0.2
� '"'" �
O.ON
O.SN
LON
1.SN
2.0N
J.ON
2.SN
J.SN
Time (5)
Figure 10: Input clock and outputs at node A and
4.0N
-0.2
O.ON
I LON
I UN
I 2.SN
I 2.0N
I J.ON
J Tir
1.8
1.6
1.4
� .,
Case I:We fed a I GHz clock as the input clock and
�
OJ
0 >
calculated the power dissipated in the H-tree CON when the
Case 2 : We fed a 500 MHz clock as the input clock and
- r 1.4 � 1.2 ., 1.0 OJ � 0.8 0 0.6 > 0.4 0.2 0.0 -
r
1.6
We conclude that we are able to achieve a 50.2 % power goal
0.4
1.8
network and the FO together was found out to be 1.2062 mW.
same
MEGHZ��
Yl 2.0
by the FO. The total power consumed by the clock tree
the
Frequencv: 550.06
0.6
-0.2
calculated the power dissipated after it was doubled to I GHz
achieving
1.0
0.8
0.0
to be 2.4024 mW.
while
1.2
0.2
clock reached the leaf nodes.(without FO circuit) We found it
2
'-------"
I O.SN
Yl 2.0
Next we calculated the power dissipation for these 2 cases:
Case
E�
Figure II-a: Simulation output for 450 MHz
0 of H
A. Power consumption
for
/
Time
tree CON
savings
Frequencv: 454.55 MEGHz
0.8
of
distributing a 1 GHz clock to the four comers of a global CON.
B Bandwidth o/the FD circuit
-0.2
O.ON
Though the FO circuit is designed to work exactly for 3 frequencies (250 MHz, 500 MHz and I GHz),it can be extended to work for other frequencies. This FO circuit has
� I O.SN
Time
I 1.0N
"-----l I I.SN
� I 2.0N
Figure II-b: Simulation output for 550 MHz
755
I
Peri
I 2.SN
2012 International Conference on Computing, Electronics and Electrical Technologies [ICCEET]
John Reuben holds a BE(Honors') degree in Electrical and Electronics
V.CONCLUSION AND FUTURE WORK
Engineering from BIIS,Pilani and M.Tech in Communication Engineering from VII University, Vellore. He is currently Assistant professor with VIT
The FD circuit designed is able to work for a wide range of frequencies.
It
consumes
less
power and
has
University, Vellore where he is pursuing his PhD
negligible
Abishek Anuroop is pursuing B.Tech degree in Electronics and
propagation delay. When this FD circuit is used at the leaves
Instrumentation Engineering from VIT University, Vellore .
of a CDN, it achieves 50.2 % power savings compared to the case
when
the
clock
signal
is
distributed
at
its
target
frequency.
Dr.Harish M Kittur received the B. Sc. degree in Physics, Mathematics and Electronics from the Karnataka University, Dharwad, in 1994. M. Sc. in
Since we are moving fast towards ultra deep sub micron
Physics from the Indian Institute of Technology, Mumbai, in 1996. M. Tech.
technology(less than 100 nm), we have to design and study the FD circuit and the H-tree CDN at 90
nm
in Solid State Technology in the year 1999 from the Indian Institute of
technology and
Technology, Madras, and Ph. D. in Physics from the RWTH Aachen in the
lesser. This will be our future work.
year 2004. He is currently Associate Professor with VII University, Vellore
Also, the select lines of the Mux (in the FD circuit) have to be generated using a suitable circuitry. A possible future work could be to design a state machine circuit to generate the select lines to the Mux based on the input clock frequency.
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