Clock Jitter Reduction and Flat Frequency Generation in ... - IEEE Xplore

1832

IEEE TRANSACTIONS ON COMPONENTS, PACKAGING AND MANUFACTURING TECHNOLOGY, VOL. 7, NO. 11, NOVEMBER 2017

Clock Jitter Reduction and Flat Frequency Generation in PLL Using Autogenerated Control Feedback Suman Bhowmik, Sambhu Nath Pradhan, and Bidyut K. Bhattacharyya, Fellow, IEEE

Abstract— In this paper, a method has been proposed by which one can reduce the clock jitter and achieve almost flat frequency clock output from the phase-locked loop (PLL), independent of the power supply voltage fluctuation. These voltage fluctuations occur when a given chip comes out from the sleep mode to the active mode. This causes the chip to draw a hasty current, which in turn produces LdI/dt noise. That causes the voltage to drop and also to oscillate at the power delivery network’s resonance frequency. This power supply noise causes clock jitter. The voltage-controlled oscillator of the proposed PLL is designed at 45-nm technology such that when there is supply voltage variation, it is automatically corrected by a feedback methodology having only 11-ps response time delay, compared to 588-ps clock period. Simulation result shows that, for the proposed new PLL design, the number of places where the clock periods are altered due to this power supply voltage fluctuation is reduced. The performance of the proposed PLL design in terms of reduction of clock jitter, caused by the variation of power supply voltage and the flatness of the frequency versus power supply voltages, is tested by feeding the clock to a circuit (c17 of ISCAS’85) for the conventional methodology and also for our new methodology. It has been shown that, using the proposed method, the clock jitter caused by the power supply noise can be reduced by about 50% compared to the conventional design methodology. Index Terms— Clock jitter, feedback, phase-locked loop (PLL), power supply noise, ring oscillator, voltage-controlled oscillator (VCO).

I. I NTRODUCTION

C

LOCK circuitry is one of the fundamental elements for electronic chip. Ring oscillator is one kind of clock generator circuit that has an odd number of identical CMOS inverters connected back to back. If the delay of each CMOS inverter is τ for a given power supply voltage V P and if there are n number of inverters, the ring oscillator will oscillate with frequency 1 fR ∼ = 2nτ (V P )

Manuscript received November 15, 2016; revised May 26, 2017 and August 17, 2017; accepted September 5, 2017. Date of publication October 6, 2017; date of current version October 26, 2017. This work was supported by Deity, Government of India, through the SMDP-C2SD Project. Recommended for publication by Associate Editor M. Cases upon evaluation of reviewers’ comments. (Corresponding author: Suman Bhowmik.) S. Bhowmik and S. N. Pradhan are with NIT Agartala, Jirania 799046, India (e-mail: [email protected]; [email protected]). B. K. Bhattacharyya is with the Electrical Interconnect Consultation, TORIT, San Jose, CA 95125 USA (e-mail: [email protected]). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TCPMT.2017.2751742

where n is an odd number, V P is the effective voltage applied to the device, and it is different from the power supply voltage V0 , which is the voltage of voltage regulator module (VRM), situated in the printed circuit board (PCB) [1], [2]. The position of V P will be outlined later in Fig. 2, while discussing the power delivery network (PDN). Here τ represents the time delay of a single inverter that is used in the ring oscillator. It is important to note that the value of τ depends on V P , and voltage V P fluctuates as a function of time due to LdI/dt (Lenz’s law). Ideally, ring oscillator generates constant output frequency for a given power supply voltage and fixed junction temperature. Due to Ld I /dt noise, power supply voltage fluctuates, and this fluctuation changes the time period of the oscillation at the output of the ring oscillators [3]. Voltage-controlled oscillator (VCO) is a part of phase-locked loop (PLL), and VCO can be designed using ring oscillator circuit for clock generation. Due to sudden current drawn by the device, as described before, power supply voltage fluctuates near the device, and that makes the frequency of oscillation at the output of PLL varying. This happens when the chip comes out from the sleep mode or the activity of the chip changes. This phenomenon causes clock jitter and also it changes the clock frequency as long as there are fluctuations of voltage V P . This change of frequency causes setup time violation and holdtime violation that eventually generate the functional failure of circuit operation [4]. Power supply noise induced jitter in CMOS PLL has been discussed in [5] and [6]. It has been observed that the operating frequency of the present day’s silicon reduces by (2.2–2.3) MHz per mV voltage drop in the power supply [7]. It means if a part runs at 3 GHz at 1 V and the operating voltage fluctuates by 100 mV, then the operating frequency of the chip will reduce by 220 MHz, and thus effective operating frequency will be 2.78 GHz, which is less than specified value of 3 GHz. Therefore, one has to sell the chip at a lower frequency for high-volume manufacturing environments when this phenomenon will get coupled with the process files. In this paper, a new PLL design methodology using 45-nm silicon technology is proposed, which generates low jitter clock. The output of the PLL is normally a higher frequency clock that is produced by VCO. In our case, VCO, as mentioned before, is designed utilizing ring oscillator. Another circuit has also been developed to detect the occurrence of the average number of clock jitter over some

2156-3950 © 2017 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.

BHOWMIK et al.: CLOCK JITTER REDUCTION AND FLAT FREQUENCY GENERATION

Fig. 1. Clock period variation inside the chip when power supply voltage varies as a function of time.

Fig. 2.

Schematic of PDN and all device blocks.

clock periods. To understand the improvement in performance using the proposed methodology, benchmark circuit, c17 of ISCAS’85, proposed PLL and the testing circuit have been developed and tested using Cadence tool in 45-nm process file. In Fig. 1, the clock jitter together with the frequency variation of the clock that is generated due to the supply voltage variation inside the chip by PLL is shown. Signal A is ideal clock signal when the power supply voltage is constant in the device. Signal B is the clock signal when the power supply voltage varies as a function of time near the device. The jitter in this paper is defined as the difference in clock period between two consecutive clock pulses that are presented in Fig. 1. When the chip has to deal with a signal like B as shown in Fig. 1, then it is hard to understand what will be the actual operating frequency of the chip. This kind of clock jitter creates functional failures. The proposed method, which helps to prevent functional failure due to clock jitter, has been discussed in Section V of this paper. In [8], a clockjitter detector circuit is shown, where a reference clock is employed for jitter detection. In this paper, the proposed circuit compensates the voltage variation to reduce jitter, by using a feedback loop. II. P ROBLEM D ESCRIPTION In Fig. 2, the schematic of the PDN and all the other functional logic blocks is shown [1]. The problem is, when all the logic gates start drawing current I (t) as the silicon device starts waking up from the sleep mode [9], [10] to the active mode, the voltage at node P, called V P , drops below the specified power supply voltage V0 . Due to this voltage

1833

drop, the speed of each inverter reduces and thus operating frequency of the chip also decreases. In Fig. 2, L PCB , CPCB , and RPCB are the inductance, capacitance, and resistance of the power supply path from the package pin and socket to the PCB connecting to the power supply, which has almost constant voltage V0 . L PIN and RPIN are the package pin and socket inductance. L PKG is the inductance of the package starting from the C4 bumps [11] of silicon up to the package decoupling capacitance, which is represented by CPKG in Fig. 2. RPKG is the corresponding value of the effective resistance of these decoupling capacitances and also the package traces. There are normally many ceramic capacitors (in the range of 10–50) mounted on the land side of the package. They are located normally on the land side [12] of the packages where the pins are attached, which makes the connection to the PCB via socket. RDIE and CDIE are the die resistance and die decoupling capacitance, respectively. These are originated from all the switching and nonswitching gates [13] since each CMOS gate inside the device contributes to the value of the die decoupling capacitance, CDIE , and die resistance RDIE . Normally, CDIE maintains the voltage V P at node P close to V0 , which is the desired power supply voltage. RDIE reduces the oscillation amplitude continuously until the current reaches its maximum peak value [14]. RVIA and L VIA represent via resistance and via inductance, respectively. If this voltage V P reduces, the switching speed for any inverter also reduces, and if this voltage increases, then the switching speed also increases [15], and that makes the frequency of any ring oscillator be a function of the voltage V P at the node P. In Fig. 2, we show how the PDN, clock circuit PLL, and functional blocks are connected together. The input of PLL is a low-frequency clock called BCLK and is in the range of 400–800 MHz. The output of this PLL block is a high-frequency clock that is in the range of 2–5 GHz. This high frequency is generated from VCO, which controls the current through the ring oscillator, in order to control the operating frequency of the PLL output. A functional block also has been designed that describes the possible failure, when the clock frequency changes as a function of time. This functional block has the high-frequency clock input, which is in our case is about 2 GHz. The silicon device in our case is represented by the current I (t), as shown in Fig. 2. I (t) is the current that is drawn by all the logic gates when the device is getting turned on from the sleep mode to the active mode. Normally, if the clock frequency for the CPU is 3 GHz, then in ten clock cycles, the current can ramp up to 100 A (I0 ) for present days CPU or any high-powered chip [16]. The technique for reducing the power supply and ground noise, and also the implementation of VRM, have been analyzed in [17]. In our methodology, we have injected about 100 A current in 3 ns. Our PLL output is 2 GHz, and the low-frequency external clock is about 250 MHz, which is the input frequency for our PLL. The oscillation set up in the PDN comes mainly from (L PKG +L VIA ) and CDIE as shown in Fig. 2. The corresponding value in our case for these two parameters is 24 pH and 35 nF, respectively [18]. V0 is the constant power supply of 1 V provided by VRM. The functional block that is shown in Fig. 2 is a benchmark circuit whose inputs and outputs are Q, R, S

1834


and X, Y respectively. However, the number of inputs and outputs may vary according to the circuit. Over the years, several approaches have been developed to reduce clock jitter for better performance of the electronic chip. Jitter characteristics of PLL, depending upon the selfimpedance profile of core and I/O circuits, have been analyzed in [19]. A low-jitter clock generator circuit is designed with the help of spread spectrum clock generator for serial advanced technology attachment application in [20]. A frequency boost technique inside ring oscillator using frequency divider has been presented in [3] to reduce clock jitter. A PLL with separate power supply but sharing the same ground with the digital circuitry reduces jitter in PLL operation [21]. Another design of low-jitter PLL is shown in [22], where ferroelectric capacitor is used in relaxation oscillator-based VCO as timing element. Lee et al. [23] introduced a new charge pump circuit in PLL and showed that it operates in low jitter compared to while using conventional charge pump. A different kind of PLL configuration has been designed in order to reduce both the incoming and the inherent jitters by using the concept of interpolation in [24]. A supply noise cancellation scheme in PLL is presented in [25] where three-level current-mode digital-to-analog converter has been implemented in order to eliminate quantization error and better performance. Using the principle of transition of sleep transistor to operational mode, a noise reduction technique has been shown using variable frequency clock in [26]. In [27], a technique has been described where a fully integrated low-jitter and low-noise compensating PLL design using static CMOS methodology is shown. A technique is proposed in [28] using data-jitter mixing forwarded-clock receiver for high jitter correlation between data and a high-speed clock. Lee et al. [29] use digitalcontrolled oscillator circuit for clock generation to design a 5-Gb/s digital clock and data recovery circuits. In a recent work, a high-speed, burst-mode clock and data recovery with jitter suppression technique have been shown in [30], which delivers shared Internet access rates up to 10 Gb/s. A complete chip consists of several circuit blocks and each component of a circuit gets affected differently due to clock jitter. Vercaemer and Rombout [31] presented the noise expression for different components due to clock jitter. In the proposed technique, flat frequency response with respect to power supply voltage variation (V P ) has been obtained. This flat frequency response is important considering high-volume manufacturing design. Even if the frequency remains constant with low jitter but the frequency exceeds the specified range, it cannot be considered as a good design. It is because in this case, the increased frequency will generate extra heat, and this heat eventually can damage or reduce the lifetime of the chip. In the proposed technique, frequency cannot exceed the specified value, no matter what the power supply voltage is. Here, as frequency remains constant and at the same time within the specified range, customers do not heat up the chip by increasing the operating frequency externally, which can cause hazardous condition due to increase in power. In the proposed work, a unique technique has been shown to reduce jitter noise using autocorrected feedback methodology,

and at the same time, the frequency is kept nearly independent of power supply voltage variation (V P ). III. M ODELING OF D ESIGN A PPROACH IN B RIEF In this section, a brief overview of designing approach has been discussed. Due to the impedance of the PDN (Fig. 2), the effective voltage applied to any chip represented by V P is not constant all the time. Due to this fluctuating voltage V P , the current flowing through the chip changes, which in turns changes the operating frequency of the chip. Here, Isystem is representing the current flowing through the ring oscillator and the output clock frequency of the ring oscillator is represented by f OSC . Now for a conventional ring oscillator circuit, Isystem depends upon supply voltage V P , which is not constant all the time due to PDN as discussed above. Hence, for a conventional ring oscillator circuit (time varying Isystem ), we can write f OSC = f OSC (V P (t)) = f OSC (Isystem (t)). This is the mathematical representation for the cause of clock jitter and also the cause of the fluctuation of the period of oscillation (as it is a function of time) for a conventional ring oscillator circuit. Our final objective is to make the oscillation frequency f OSC constant, and for that purpose current Isystem has to be made constant. To fulfill this requirement, we have generated a control voltage Vctrl using feedback, such that Vctrl increases when V P decreases and vice versa. Our design methodology is to generate Vctrl from V P such that they together maintain constant current Isystem flowing through the circuit and thus maintain constant output frequency f OSC . Hence, for proposed ring oscillator circuit (constant Isystem ), we can write f OSC = f OSC (V P (t), Vctrl (t)) = f OSC (Isystem ) = constant. It is noticed that output clock frequency f OSC is constant and not a function of time using the proposed methodology, even though V P is fluctuating 10% around V0 . In this section, only a brief overview of design approach has been presented. However, the actual operation of the proposed circuit is not discussed in this section. Operating principle of the proposed circuit and outcomes have been discussed in later sections. IV. S YSTEM A RCHITECTURE The oscillation frequency of a ring oscillator depends on how many inverters there are, how much time it takes in order to switch each transistor (switching delay), and the temperature of the device. The number of inverters is a structural parameter that is kept constant in this design. The oscillation frequency of ring oscillator decreases with the increase in temperature, but we are not dealing with temperature issue here. In our methodology, the temperature is kept constant at 27 °C while checking the performance. The switching delay of a CMOS device significantly controls the oscillation frequency of ring oscillator, and this delay can be controlled by controlling the system current Isystem through the circuit from V P to ground; this is the key designing approach of the proposed technique. In Fig. 3, the structural diagram of the proposed ring oscillator


1835

Fig. 5. Current and output frequency waveform using conventional technique. Fig. 3.

Schematic of the proposed ring oscillator circuit.

Fig. 4. Generated similar inverted signal (Vctrl ) for a random power supply V P .

circuit is shown. In the proposed technique, additional two resistors R1 and R2 , five MOSFETs—M1 , M2 , M3 , M4 , M5 — and one extra power supply pin Vext for external supply voltage are needed. From Fig. 3, it is seen that when the voltage is higher at the gate terminal of M1, current (I1 ) through the resistance R1 is higher. Hence, the voltage drop R1 I1 increases with the increase of chip power supply voltage V P , which is gate voltage of M1 . Mathematically, when V P increases, I1 increases; when I1 increases, voltage drop I1 R1 increases and node voltage of Z (Vext –I1 R1 ), which is Vctrl , decreases; and vice versa. Resistance R2 is used for biasing the transistor M1 . Thus, a similar inverted signal of chip power supply voltage V P is generated at node Z, which is used as feedback to control the current through the oscillator. No matter what type of random fluctuation occurs in the supply voltage V P , this circuit gives similar inverted signal Vctrl , and the simulated waveform for a random signal is shown in Fig. 4. Now when the power supply voltage V P is lower due to noise, oscillation frequency is supposed to be less, and when power supply voltage is higher, oscillation frequency is supposed to be high. However with this technique, generated feedback signal controls the current flowing through the circuit Isystem and thus controls the oscillation frequency. When power supply voltage V P is low, the current flowing through the circuit Isystem is also low. In this case, generated higher control voltage Vctrl allows more current to pass through the circuit. Because when Vctrl is higher, nMOSs (M4, M5) allow more

current to pass. Due to this, pMOSs (M2, M3) also pass the same amount of current as they are connected in currentmirror configuration. Similarly, when power supply voltage V P is higher, the current flowing through the circuit Isystem is also higher and in this case generated lower control voltage Vctrl , allowing less current to pass through the circuit. Thus, an autocorrected feedback system maintains constant current flow through the oscillator and thus produces the constant frequency clock f clock . This is shown in Figs. 5 and 6. From Figs. 4 and 6, it is noticed that inverted V P (Vctrl ) and constant Isystem can be obtained almost instantaneously using the proposed technique. It takes 11 ps for generating selfcorrecting control voltage Vctrl , which eventually makes Isystem constant. This time has been calculated as the delay between Vctrl and V P (Fig. 4). For this purpose, timing difference between two corresponding peak values of both V P and Vctrl has been taken. This indicates that this technique takes very less time to stabilize the system, and this extra feedback loop does not affect the lock-in time, which is due to the low-input capacitance of the feedback circuit. It can be easily noticed that for the conventional technique, as shown in Fig. 5, both the signals f clock and Isystem are dependent on supply voltage V P . Whenever V P goes down, Isystem reduces and therefore fclock also reduces. Similarly, when V P goes up for conventional technique, Isystem increases and therefore f clock also increases. On the other hand, using the proposed technique as shown in Fig. 6, both the signals f clock (output clock frequency of ring oscillator) and Isystem (system current flowing from V P to ground) are independent of supply voltage V P and remain almost constant over the entire time. In Fig. 3, “en” represents enable signal. This means whenever this signal goes HIGH, ring oscillator circuit works. The rest of the time it stays in disable state. An extra power supply, which is represented by Vext in Fig. 3, supplies 1.2-V dc, and this external power supply has two separate power and ground pins isolated from the main power bus of the whole silicon chip. The inductance of that power supply (Vext ) to the external world is taken as 5 nH, which is the trace and pin inductance of the organic land grid array packages while connecting to the PCB. This large inductance has little impact on the noise on Vext since the current drawn by the transistor M1 is very small and is in μA range, compared to the total system current that can be as high as 100 A for present day’s high-performance CPU. It is

1836


Fig. 6. Current and output frequency waveform using the proposed technique.

important to mention that the physical location of transistor M1 has to be very close to the power bus (V P ) so that gate input of M1 gets the same voltage V P with minimum voltage drop. It is also important to mention that if the process file is for 1 V for 45-nm technology, then the voltage across the transistors can never exceed more than 1 V due to reliability reasons. Using the proposed methodology also, Vctrl (voltage at node Z) does not exceed 1 V, which can be noticed from Fig. 4. It is noticed from Figs. 5 and 6 that Isystem for the conventional method varies almost from 10 to 50 μA, whereas for the proposed technique using autogenerated control feedback system, the current Isystem varies from 10 to 20 μA. Due to less variation in current with the proposed methodology, generated clock pulses also have almost constant clock frequency at any point of time. It is also interesting to note in Fig. 5 that the output frequency of the ring oscillator has various widths and amplitudes, which cause functional failures at high frequencies. Our objective is to minimize the variation of the width in order to prevent the functional failure, and this portion has been discussed in Section V.

Fig. 7. Timing diagram for ideal case-constant power supply voltage, V P = 1 V (Case 1).

Fig. 8. Timing diagram for real case-fluctuating power supply voltage with conventional technique showing functional failure (Case 2).

V. I MPLEMENTING D ESIGN IN L OGIC B LOCK To verify the improvement in performance using the proposed methodology, we have implemented a proposed logic circuit for functionality test. Here, c17 circuit of ISCAS’85 [33] is taken for this purpose. For implementing the design, the c17 circuit is represented as the functional block in Fig. 2. Current I (t) is being drawn by our design, as shown in Fig. 2. The current increases up to 100 A in few clock cycles. That is equivalent to a case when millions of transistors, which are cramped inside a silicon chip, start drawing current from the power supply. So it does not matter how many transistors are there in benchmark circuit—if the method works for a small circuit, it definitely works for a large circuit as well. Here, three input signals (Q, R, S) and two output signals (X, Y) have been shown in each case. Input data have been taken after passing through latch so that input gets synchronized with clock edges. The performance of this same logic circuit has been tested for three different cases: Case 1) Ideal Case (constant power supply voltage); Case 2) Real case with fluctuating power supply voltage using the conventional technique; Case 3) Real case with fluctuating power supply voltage using the proposed autogenerated control feedback technique. In Fig. 7, ideal case (no noise in the system) has

Fig. 9. Timing diagram for real case-fluctuating power supply voltage with the proposed technique showing no functional failure (Case 3).

been shown where constant 1 V (V0 = V P ) power supply has been supplied for core logic and correspondingly we get output clock and logic output of the functional circuit, which is the desired output when there is no power supply noise. All these are illustrated in Fig. 7. In Fig. 8, it is shown how the power supply voltage fluctuation changes oscillator output frequency and causes functional failure of a logic circuit. Fig. 8 shows the output Y when it is supposed to be zero, but it becomes logic 1, the same for output X. They are marked by x 1 and x 2 . In Fig. 9, it is shown how the proposed autofeedback technique generates improved output clock frequency even if the power supply voltage (V P ) is fluctuating. It can be noticed that there is no functional failure observed in Fig. 9, which is obtained by the proposed technique. If we consider input waveform, Q from Fig. 7 which is the ideal case, it is seen that input Q gets detected at the positive edge of the first clock pulse. After detection, input Q remains high for three clock pulses and then goes low for the next two


clock pulses. Now if we consider input R, it gets detected in the second clock pulse, then remains high for two clock pulses and goes low for the next three clock pulses. For input S, it gets detected in the third clock pulse then remains high for one clock pulse and goes low for the next four clock pulses. From the waveform of Fig. 7, it is observed that the above-discussed cycles repeat for the rest of the time. Depending upon the input combinations, benchmark logic circuit c17 generates output waveform X and Y. It is observed that output waveform X is detected in second clock pulse, stays high for two clock pulses, goes low for the next three clock pulses, and then this cycle repeats for the rest of the time. Output waveform Y is detected in the first clock pulse, stays high for one clock pulse, goes low for the next four clock pulses, and then this cycle repeats for the rest of the time. Now if we look Fig. 8, which is the real case with fluctuating supply voltage, it is noticed that there are so many differences with the ideal case, as shown in Fig. 7. First of all, output clock frequency (pulse period) is not the same for the entire time. If we consider input Q, it is detected in the first clock pulse, but remains high for four clock pulses, then goes low for the next three clock pulses, then goes high for three clock pulses, and then goes low for two clock pulses. In summary, latched input Q is neither repeating nor similar to the ideal-case waveform (Fig. 7). From Fig. 8, the same problems can be observed for input R, S and output X, Y also. On the other hand, if we observe properly, waveforms in Fig. 9 (real case with the proposed autofeedback technique) are very similar to the waveforms of Fig. 7 (Ideal Case). For all the three cases, such input combination has been applied to a logic circuit (c17) that least common multiple of all the time periods is 3 ns. So no matter what are the input combination and the logic circuit being used, each output waveform will also have the time period of 3 ns. In Figs. 7–9, two parameters x 1 and x 2 are introduced for the purpose of better understanding the prevention of functional failure. For output waveform X, the parameter is x 1 , and for the output waveform Y, it is x 2 . It can be noticed that for ideal case (Fig. 7), it is maintaining a constant x 1 and constant x 2 over the time. In the real case with power supply noise (Fig. 8), it is noticed that transition occurs before x 1 time for signal X and for signal Y, the transition occurs before x 2 time, which is denoting functional failure of the logic block. This problem is overcome using the proposed technique, and it is seen from the timing diagram (Fig. 9) where it is maintaining constant x 1 and constant x 2 . VI. S CHEMATIC AND L AYOUT OF PLL D ESIGN U SING AUTOFEEDBACK M ETHODOLOGY PLL-based clock generator provides an efficient technique to generate different frequency (clock) that are required in today’s technology. PLL is an autocorrected electronic system that is used for generating clock, and these clocks control several peripherals and functional chips [34]. PLL circuitry mainly consists of charge pump, phase frequency detector, low-pass filter (loop filter), VCO, and finally frequency divider block as a feedback loop. Phase frequency detector is for detecting the phase difference between the input clock and feedback clock (output of the frequency divider block). Charge pump generates an equivalent waveform from the phase

1837

Fig. 10.

PLL circuit with the conventional ring oscillator-type VCO.

Fig. 11.

PLL circuit with the proposed VCO.

detector output. If the generated waveform has higher components of frequency, then it passes through a low-pass filter to reduce the fluctuation of charge pump output. After that, it goes to VCO, which is the most significant block of PLL. It is an oscillator whose output frequency depends on the input voltage [35]. There are several techniques to design VCO. Among those techniques, one is ring-oscillator-type VCO. In the proposed work, while designing the VCO, proposed ring oscillator is used inside. When the output of the charge pump (and LPF) has higher voltage level, output oscillation frequency is higher, and when the voltage level is low-output, frequency is low and thus it acts as a VCO. In Fig. 10, schematic of conventional PLL circuit is shown [32]. In Fig. 11, schematic of the proposed PLL circuit using autogenerated control feedback to compensate the power supply voltage fluctuations is shown. Here, the values of R1 and R2 are taken to be 9 and 2 K, respectively. These values have been chosen after performing Monte–Carlo simulation, which has been discussed in Section VIII. By using the proposed ring-oscillator-based PLL, clock jitter at the output is reduced significantly and is discussed in Section VIII. Proposed VCO block, shown in Fig. 11 is designed using the concept of the proposed ring oscillator circuit (Fig. 3), where autogenerated control feedback methodology is used. This design has two more extra nMOS transistors (M6 and M7) to control the current through ring oscillator, as shown in Fig. 11. The output voltage of the loop filter VCOin , shown in Fig. 11, is pretty much a dc signal that controls the current through these two nMOS transistors M6 and M7. Therefore now we have three pairs of nMOS transistors—one pair M6 and M7

1838


Fig. 13. Fig. 12.

Proposed jitter detector circuit with timing diagram.

Layout of proposed low-jitter VCO.

is controlled by filtered dc, another pair M4 and M5 is being controlled by the Vcrtl signal generated by our autogenerated feedback methodology, and the other pair M1 and M2 is used for the current mirror. The purpose of all these transistors is to control the current through the VCO, independent of the voltage variation of the power supply as a function of time. Vext is a separate power supply pin, and for including the effect of noise in Vext , coupling capacitance of 2 pF and pin inductance of 5 nH [36] have been considered, which is shown in Figs. 3 and 11. Mutual coupling between the node V P and the package pin, which supplies Vext , is taken as 0.5 nH. This Vext pin pumps very low current (less than 0.5 μA). Therefore, for a trace having inductance 5 nH, the noise generated due to the sudden change in this current is in the range of μV, which is very small. This pin supplies power to only one transistor, M1, as shown in Fig. 11. The only noise that can come into this Vext pin is due to the coupling of this Vext pin with the power and ground metallization of the core power supply as well as from p-type silicon substrate, which is grounded in our case. This coupling will generate noise in Vext pin due to sudden current change by the core logic, which can be very large. In some existing PLL designs [37], a separate power supply generally called VDDa is used for VCO. Vext of the proposed design is less noisy compared to this VDDa because VDDa is directly connected to all the transistors inside VCO, which are large in numbers, whereas Vext is directly connected to only one transistor M1 (Fig. 11) and two resistors, as described in Fig. 11 of the proposed technique. Response time for self-correction using the proposed feedback loop technique is found to be 11 ps for 45-nm process that we have used. The operating frequency of the PLL is about 1.7 GHz (time period is about 588 ps). Therefore, the response time of the present feedback loop is about 2%. If one uses VDDa and also Vext , which may require an additional four pins (two power and two grounds), then the present days PLL design can be made more robust. Because in that case, the noise in VDDa will be less compared to core logic and Vext power supply with feedback loop may eliminate the jitter and the variation of clock period completely. The layout has been verified using design rule check and layout versus schematic LVS check using Layout XL tool of

Cadence. Schematic and layout of the proposed PLL circuit are shown in Figs. 11 and 12, respectively. Area of the layout of the proposed VCO is found to be 32.6 μm2 , whereas for the conventional technique area is 24.8 μm2 . It is important to mention that the nMOS transistor M1, which operates at voltage 1.2 V, is within a micrometer distance from the complete PLL circuit and it is not physically very far from the PLL circuit and, therefore, we can assume V P is almost constant around this small neighborhood. This is important because if the chip size is 0.4 in × 0.4 in, then the values of V P can be different from one end of the chip to the other end. This is an important design criterion for our design to work. For implementing the extra control logic in the proposed technique, one extra nMOS and two resistances are required. This extra area is about 8 μm2 , which will have very little impact on the cost of the product. VII. T ESTING T ECHNIQUE TO U NDERSTAND THE P ERFORMANCE I MPROVEMENT There are some existing techniques for analyzing clock jitter of a circuit. Among those, the technique in [38] is notable, where on-chip jitter detection scheme is presented for high-performance microprocessors by reusing the same ring oscillator over the time for low cost. In another work [39], a programming algorithm has been presented to calculate the numerical value of jitter due to electromagnetic interference on the power supply. This work shows the nonlinear behavior of clock jitter due to electromagnetic interference on the power supply. In our paper, to detect the clock jitter and observe the waveform pattern, a circuit has been proposed with the help of a delay element and a XOR gate. When there is no jitter in clock pulse, then each and every clock pulse has exactly the same time period (T ). This means if we start a jitter-free clock after one complete clock pulse and then we overlap it with the original clock, it will be exactly overlapped with no jitter. On the other hand for jittered clock, there will be some mismatch after overlapping. The width of the output from XOR gate changes depending on the magnitude of the jitter. This is denoted by D in Fig. 13. The design objective is to minimize the average value of D. For proper analysis, the standard deviation of the average clock period (T ) using both the techniques, denoted by σT ,


1839

TABLE I C OMPARATIVE D ATA A NALYSIS

is compared in Table I. In Fig. 13, C(t), which is the input of jitter detector circuit, is actually the output of the proposed PLL circuit as shown in Fig. 11. This detection is done by comparing two signals using a XOR gate. One of the input signals in the XOR gate is the distorted fluctuating clock signal. We call it C(t), and the other one is the same signal but shifted by an amount of the desired clock period (T ), which is our design parameter for PLL clock output. This is to check how many times (N) the clock edges are different for these two signals. The appropriate value of T minimizes the number of N. This T corresponds to the best operating frequency for performance of a highly reliable design. In ideal design, N = 0 means all clock edges are aligned perfectly. Here, C(t) is the actual generated clock from the clock circuit of the PLL as shown in Figs. 11 and 13. Delay element produces a delay of time T (expected time period of the clock), and the delayed signal is represented by C(t + T ) here. After that, C(t) and C(t + T ) are fed to a two-input XOR gate. Property of the XOR gate is that it produces HIGH value only when two inputs are at different logic level. In Fig. 13, second-clock pulse has less width compared to other clocks. So after shifting the clock by time T when compared with the original clock by XOR gate, jittered clock is detected as shown in Fig. 13. Using this technique, number of jittered clock for both the cases has been determined by simulating in cadence, and corresponding waveforms have been shown in Figs. 14 and 15. It is important to mention that the jitter detector circuit, which is shown in Fig. 13, is a circuit that has been designed to check the simulation result for performance analysis. This circuit is like a “thought experiment” for an ideal circuit to determine the clock width and jitter due to the voltage fluctuation of the power supply. VIII. C OMPARISON AND A NALYSIS Comparative study and analysis are presented in this section to understand the actual improvement in system performance using the proposed scheme compared to conventional technique. Fig. 14 presents the waveform of the circuit where all the parameters of Fig. 14 are described in Fig. 10, whereas Fig. 15 presents the waveforms related to Fig. 11. For comparative analysis between conventional technique and the proposed technique, the number of spikes has been detected using both techniques for PLL circuit that presented in Section VII. From Figs. 14 and 15, it is noticed that less number of spike (N) is detected by the

Fig. 14.

Detected jitter using test circuit for conventional technique.

Fig. 15.

Detected jitter using test circuit for the proposed technique.

Fig. 16.

Frequency variation comparison with respect to applied voltage.

proposed technique (Fig. 15) compared to the conventional technique (Fig. 14). It is important to mention that due to the propagation delay of XOR gate, the width of the detected spikes is different. So here, spikes having at least 20% of the supply voltage, that is 200 mV, are considered to be detected. When there is more fluctuation in the supply voltage (V P ), the number of detected spikes is also more. In Fig. 16, it is shown how operating frequency changes with the change in supply voltage. Two resistances are used in the proposed technique, and value of these resistances can change with the change of temperature and process. The curve having the solid blue diamond (marked as “proposed”) in Fig. 16 shows the circuit characteristics consisting of the exact value of the each parameter used. However, due to silicon process, these parameter values may change. For that purpose, Monte–Carlo simulation was performed to observe how

1840


Fig. 17. Effect on standard deviation of jitter period (Table I), due to ±10% variation of Vext .

the performance of proposed technique can be affected. It is noticed that for conventional clock circuit, operating frequency is directly proportional to supply voltage. However, for the proposed technique, operating frequency stays almost constant even with the fluctuation in supply voltage. Even after adding Monte–Carlo deviation, the proposed circuit produces better output with respect to conventional technique. This can be attributed to the flatness of the curves compared to the conventional method, as shown in Fig. 16. Thus, the proposed methodology generates a flat frequency clock output of the PLL. So these new methods use an additional nMOS (M1) transistor for the generation of Vctrl signal and then to feed into different transistors, for the purpose of controlling the system current Isystem , which in turn stabilizes the frequency spectrum of the output clock of the PLL. For proper data analysis, we have injected power supply V P , from 0.9 to 1.1 V (±10% of 1 V), and corresponding operating frequencies have been noted down for both conventional and the proposed methods as shown in Fig. 16. It is noticed from Fig. 16 that rate of change of operating frequency with respect to voltage fluctuation is much more in conventional technique compared to the proposed technique. The standard deviation of the operating frequency of conventional technique and the proposed technique is found to be 315.54 and 77.65 MHz, respectively. For the proposed method, the variation is less, and therefore it is a more reliable method and the new method will generate less functional failure of the chip. The less the value of standard deviation (σT ), the better the system performance is going to be. For proper analysis, Vext has been varied by ±10% around the specified typical-typical (TT) value and corresponding σT values have been noted down, which is shown in Fig. 17. From Fig. 17 and Table I, tolerance margin of ±10% for Vext can be considered for the proposed technique, and it can be noticed that, even with the variation of Vext , proposed technique still gives the better result. It is worth mentioning that new method gives a better result at a higher voltage since σT remains flat, but at low voltages, σT starts increasing but is still better than the conventional method. The value of σT for the conventional method at 1.2 V is 31.19 ps, whereas for the proposed method when the voltage drops below 10%, the value of σT is around 24 ps (from Fig. 17). In Table I, data have been taken for 50 ns for both the conventional technique and the proposed technique. The standard

deviation of jitter period and average current has been taken from Virtuoso analysis calculator of Cadence tool. The number of detected Jitter spike (N) has been counted from Fig. 14 (for conventional method) and Fig. 15 (proposed autogenerated control feedback circuit). It is noted from both Figs. 14 and 15 that there are spikes of the different voltage level. In order to find the value of N, only those spikes have been counted that reached above 200 mV. For conventional technique and the proposed technique, these numbers are 96 and 39, respectively. The standard deviation of clock period σT , which represents jitter width, has been found to be 31.19 ps for conventional technique. Using the proposed technique, if we do not consider coupling effect on Vext , this value is found to be 14.63 ps, whereas if we consider the coupling effect on Vext by including 5-nH package inductance and 2-pF coupling capacitance as shown in Fig. 11, this value is 15.35 ps. We have also inserted 0.5-nH mutual coupling between V P and Vext . This indicates coupling effect on Vext with core logic is about 4%. Average currents for conventional method and the proposed method are 31 and 23 μA, respectively. The data shown in Table I represent that the proposed method is very effective to stabilize the clock frequency and to reduce the clock jitter of a system, caused by the power supply voltage variations. IX. C ONCLUSION In this paper, an innovative technique is presented by which constant flat frequency clock output is generated, even in the presence of power supply voltage fluctuations caused by a sudden current drawn by the device. It is observed that this proposed autogenerated feedback control technique reduces the standard deviation of the clock jitter by about 52% and also allows one to maintain nearly a flat frequency response independent of the value of noisy supply voltage. Proposed technique has been implemented in VCO inside the PLL for better system performance. It has also been shown that, using the proposed methodology, functional failure of various logic circuits can be prevented. R EFERENCES [1] K. Radhakrishnan, M. J. Hill, K. Aygun, C.-P. Chiu, and G. Choksi, Optimization of Package Power Delivery and Power Removal Solutions to Meet Platform Level Challenges, document ITRS004, Intel Developer Forum, 2005. [2] A. S. Sedra, K. C. Smith, and A. N. Chandorkar, Microelectronic Circuits: Theory and Applications. New Delhi, India: Oxford Univ. Press, 2013. [3] T.-H. Lee and P. A. Abshire, “Frequency-boost jitter reduction for voltage-controlled ring oscillators,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 24, no. 10, pp. 3156–3168, Oct. 2016, doi: 10.1109/TVLSI.2016.2541718. [4] Clock Jitter Definitions and Measurement Methods, document SiT-AN10007 Rev 1.2, The Smart Timing Choice, Jan. 2014. [5] P. K. Hanumolu, B. Casper, R. Mooney, G.-Y. Wei, and U.-K. Moon, “Analysis of PLL clock jitter in high-speed serial links,” IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process., vol. 50, no. 11, pp. 879–886, Nov. 2003, doi: 10.1109/TCSII.2003.819121. [6] P. Heydari, “Analysis of the PLL jitter due to power/ground and substrate noise,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 51, no. 12, pp. 2404–2416, Dec. 2004, doi: 10.1109/TCSI.2004.838240. [7] B. K. Bhattacharyya, A. Levin, and G. Huo, “A semi-empirical approach to determine the effective minimum current pulse width (T) for an operating silicon chip,” in Proc. Int. Power Eng. Conf. (IPEC), Dec. 2007, pp. 922–927.


[8] K. L. Wong et al., “Internal clock jitter detector,” U.S. Patents 6 208 169 B1, Mar. 27, 2001. [9] L. Smith, S. Sun, P. Boyle, and B. Krsnik, “System power distribution network theory and performance with various noise current stimuli including impacts on chip level timing,” in Proc. IEEE Custom Intergr. Circuits Conf. (CICC), Sep. 2009, pp. 621–628. [10] J. Rius, “Supply noise and impedance of on-chip power distribution networks in ICs with nonuniform power consumption and interblock decoupling capacitors,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 23, no. 6, pp. 993–1004, Jun. 2015, doi: 10.1109/TVLSI.2014.2332189. [11] R. Shukla, V. Murali, and A. Bhansali, “Flip chip CPU package technology at Intel: A technology and manufacturing overview,” in Proc. 49th Electron. Compon. Technol. Conf., San Diego, CA, USA, Jun. 1999, pp. 945–949, doi: 10.1109/ECTC.1999.776299. [12] H. Y. Loo, B. H. Oh, P. T. Oh, and E. K. Lee, “CPU package design optimization for performance improvement and package cost reduction,” in Proc. Int. Conf. Electron. Mater. Packag., Dec. 2006, pp. 1–5. [13] J. Wang, J. Lu, Y. Liu, X. Chu, and Y. Li, “Effective radii of on-chip decoupling capacitors under noise constraint,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 24, no. 12, pp. 3415–3423, Dec. 2016, doi: 10.1109/TVLSI.2016.2559585. [14] B. K. Bhattacharyya, N. Laskar, S. Debnath, and D. Baral, “Innovative scaling method to minimize cost of integrated circuit packages and devices,” IEEE Trans. Compon., Packag., Manuf. Technol., vol. 4, no. 9, pp. 1489–1494, Sep. 2014, doi: 10.1109/TCPMT.2014.2339272. [15] B. K. Bhattacharyya, N. Laskar, S. Debnath, and S. Bhattacharya, “Determination of rate of change of current inside the 3 GHz silicon chip for any given noise at 100 AMP maximum saturation current,” Int. J. Electr. Energy, vol. 1, no. 2, pp. 67–71, Jun. 2013, doi: 10.12720/ ijoee.1.2.67-71. [16] B. K. Bhattacharyya and G. Huo, “A mathematical technique to estimate the high frequency current inside the silicon die from the noise measurements,” in Proc. Int. Conf. Thermal, Mech. Multi-Phys. Simulation Experim. Microelectron. Micro-Syst. (EuroSime), London, U.K., Apr. 2007, pp. 1–4, doi: 10.1109/ESIME.2007.359959. [17] H. Kim, B. Achkir, J. Kim, C. Yoon, and J. Fan, “On-chip voltage regulator module (VRM) effect on power/ground noise and jitter at highspeed output buffer,” in Proc. IEEE Int. Symp. Electromagn. Compat., Raleigh, NC, USA, Aug. 2014, pp. 75–80. [18] B. K. Bhattacharyya and D. Baral, “Method to simulate rise time of current drawn by a microprocessor,” IEEE Trans. Compon., Packag., Manuf. Technol., vol. 3, no. 10, pp. 1731–1736, Oct. 2013, doi: 10.1109/ TCPMT.2013.2245945. [19] Y.-S. Son, J.-H. Lim, J.-Y. Jeon, W.-Y. Jung, S. Lee, and J.-K. Wee, “PLL jitter analysis with various power delivery networks on a board,” in Proc. 12th IEEE Workshop Signal Propag. Interconnects (SPI), Avignon, France, May 2008, pp. 1–4, doi: 10.1109/SPI.2008.4558358. [20] T. Kawamoto, M. Suzuki, and T. Noto, “1.9-ps jitter, 10.0-dBm-EMI reduction spread-spectrum clock generator with autocalibration VCO technique for serial-ATA application,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 22, no. 5, pp. 1118–1126, May 2014, doi: 10.1109/TVLSI.2013.2257901. [21] P. Larsson, “Measurements and analysis of PLL jitter caused by digital switching noise,” in Proc. 26rd Eur. Solid-State Circuits Conf. (ESSCIRC), Stockholm, Sweden, Sep. 2000, pp. 204–207. [22] G. Pauls and T. S. Kalkur, “PLL jitter reduction by utilizing a ferroelectric capacitor as a VCO timing element,” IEEE Trans. Ultrason., Ferroelect., Freq. Control, vol. 54, no. 6, pp. 1096–1102, Jun. 2007, doi: 10.1109/TUFFC.2007.363. [23] M.-S. Lee, T.-S. Cheung, and W.-Y. Choi, “A novel charge pump PLL with reduced jitter characteristics,” in Proc. 6th Int. Conf. VLSI CAD (ICVC), Seoul, South Korea, Oct. 1999, pp. 596–598. [24] F. Kobayashi, Y. Egashira, and H. Kondoh, “A PLL configuration for reducing both incoming and inherent jitters,” in Proc. 16th IEEE Int. Conf. Electron., Circuits, Syst. (ICECS), Hammamet, Tunisia, Dec. 2009, pp. 93–96, doi: 10.1109/ICECS.2009.5410931. [25] A. Elshazly, R. Inti, W. Yin, B. Young, and P. K. Hanumolu, “A 0.4-to-3 GHz digital PLL with supply-noise cancellation using deterministic background calibration,” in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, San Francisco, CA, USA, Feb. 2011, pp. 92–94, doi: 10.1109/ISSCC.2011.5746233. [26] S. Bhowmik, D. Deb, S. N. Pradhan, and B. K. Bhattacharyya, “Reduction of noise using continuously changing variable clock and clock gating for IC chips,” IEEE Trans. Compon., Packag., Manuf. Technol., vol. 6, no. 6, pp. 886–896, Jun. 2016, doi: 10.1109/ TCPMT.2016.2562143.

1841

[27] M. Mansuri and C. K. K. Yang, “A low-power adaptive bandwidth PLL and clock buffer with supply-noise compensation,” IEEE J. Solid-State Circuits, vol. 38, no. 11, pp. 1804–1812, Nov. 2003. [28] S. H. Chung and L. S. Kim, “A 9.6-Gb/s 1.22-mW/Gb/s data-jitter mixing forwarded-clock receiver in 65-nm CMOS,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 23, no. 10, pp. 2023–2033, Oct. 2015, doi: 10.1109/TVLSI.2014.2355840. [29] T. Lee, Y.-H. Kim, and L.-S. Kim, “A 5-Gb/s digital clock and data recovery circuit with reduced DCO supply noise sensitivity utilizing coupling network,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 25, no. 1, pp. 380–384, Jan. 2017. [30] M.-C. Su, W.-Z. Chen, P.-S. Wu, Y.-H. Chen, C.-C. Lee, and S.-J. Jou, “A 10-Gb/s, 1.24 pJ/bit, burst-mode clock and data recovery with jitter suppression,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 62, no. 3, pp. 743–751, Mar. 2015, doi: 10.1109/TCSI.2014.2367573. [31] D. Vercaemer and P. Rombouts, “Analyzing the effect of clock jitter on self-oscillating sigma delta modulators,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 63, no. 2, pp. 200–210, Feb. 2016, doi: 10.1109/TCSI. 2015.2512738. [32] R. E. Best, Phase Locked Loops. New York, NY, USA: McGraw-Hill, 2007. [33] Benchmark Circuits ISCAS’85. Accessed: Aug. 5, 2017. [Online]. Available: http://pld.ttu.ee/~maksim/benchmarks/ [34] AN-1006 Phase-Locked Loop Based Clock Generators, Texas Instruments, Dallas, TX, USA, Literature Number: SNOA351, 1995. [35] B. P. Panda, “Design and analysis of an efficient phase locked loop for fast phase and frequency acquisition,” M.S. thesis, Nat. Inst. Technol., Rourkela, Rourkela, India, 2011. [36] “Performance characteristics of IC packages,” in Packaging Data Book. Santa Clara, CA, USA: Intel Corporation, 2000, ch. 4, p. 12. [37] Intel Core i7-900 Desktop Processor Extreme Edition Series and Intel Core i7-900 Desktop Processor Series, 2010, vol. 1. [38] M. Omana et al., “Low-cost on-chip clock jitter measurement scheme,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 23, no. 3, pp. 435–443, Mar. 2015, doi: 10.1109/TVLSI.2014.2312431. [39] Z. Huang, S. Yang, and T. Su, “Nonlinear jitter of a clock path due to electromagnetic interference on the supply,” IEEE Trans. Electromagn. Compat., to be published, doi: 10.1109/TEMC.2017.2707301. Suman Bhowmik is pursuing the Ph.D. degree with the Department of Electronics and Communication Engineering, NIT Agartala, Agartala, India. He is currently an intern with Intel, Bangalore, India, where he is involved in floating point unit design. His current research interests include phaselocked-loop-based clock generator, power delivery network analysis, RTL synthesis, library analysis, power supply noise reduction technique, and lowpower VLSI Design.

Sambhu Nath Pradhan received the M.Tech. degree from BESU, Shibpur, India, and the Ph.D. degree from IIT Kharagpur, Kharagpur, India. He is currently an Assistant Professor with the Department of Electronics and Communication Engineering, NIT Agartala, Agartala, India. His current research interests include low-power VLSI design and synthesis, thermal-aware design, computer-aided design for VLSI, and optimization techniques.

Bidyut K. Bhattacharyya (M’88–SM’98–F’00) received the Ph.D. degree from the Department of Physics, The State University of New York, Buffalo, NY, USA, in 1983. He was at Intel, Chandler, AZ, USA, for 23 years and with TORIT at San Jose, CA, USA, for remaining years. Dr. Bhattacharyya was selected as an IEEE Fellow in 2000 for his contribution in electronics packaging.